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arm64: Add support for DMA_ATTR_SKIP_CPU_SYNC attribute to swiotlb
[linux-2.6-block.git] / arch / arm64 / kernel / cpufeature.c
CommitLineData
359b7064
MZ		 1/*
2 * Contains CPU feature definitions
3 *
4 * Copyright (C) 2015 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
9cdf8ec4 19#define pr_fmt(fmt) "CPU features: " fmt
359b7064 20
3c739b57 21#include <linux/bsearch.h>
2a6dcb2b 22#include <linux/cpumask.h>
3c739b57 23#include <linux/sort.h>
2a6dcb2b 24#include <linux/stop_machine.h>
359b7064 25#include <linux/types.h>
2077be67 26#include <linux/mm.h>
359b7064
MZ		 27#include <asm/cpu.h>
28#include <asm/cpufeature.h>
dbb4e152 29#include <asm/cpu_ops.h>
13f417f3 30#include <asm/mmu_context.h>
338d4f49 31#include <asm/processor.h>
cdcf817b 32#include <asm/sysreg.h>
77c97b4e 33#include <asm/traps.h>
d88701be 34#include <asm/virt.h>
359b7064 35
9cdf8ec4
SP		 36unsigned long elf_hwcap __read_mostly;
37EXPORT_SYMBOL_GPL(elf_hwcap);
38
39#ifdef CONFIG_COMPAT
40#define COMPAT_ELF_HWCAP_DEFAULT \
41 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
42 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
43 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
44 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
45 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
46 COMPAT_HWCAP_LPAE)
47unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
48unsigned int compat_elf_hwcap2 __read_mostly;
49#endif
50
51DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
4b65a5db 52EXPORT_SYMBOL(cpu_hwcaps);
9cdf8ec4 53
efd9e03f
CM		 54DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
55EXPORT_SYMBOL(cpu_hwcap_keys);
56
fe4fbdbc 57#define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
3c739b57 58 { \
4f0a606b 59 .sign = SIGNED, \
fe4fbdbc 60 .visible = VISIBLE, \
3c739b57
SP		 61 .strict = STRICT, \
62 .type = TYPE, \
63 .shift = SHIFT, \
64 .width = WIDTH, \
65 .safe_val = SAFE_VAL, \
66 }
67
0710cfdb 68/* Define a feature with unsigned values */
fe4fbdbc
SP		 69#define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
70 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
4f0a606b 71
0710cfdb 72/* Define a feature with a signed value */
fe4fbdbc
SP		 73#define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
74 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
0710cfdb 75
3c739b57
SP		 76#define ARM64_FTR_END \
77 { \
78 .width = 0, \
79 }
80
70544196
JM		 81/* meta feature for alternatives */
82static bool __maybe_unused
92406f0c
SP		 83cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
84
70544196 85
4aa8a472
SP		 86/*
87 * NOTE: Any changes to the visibility of features should be kept in
88 * sync with the documentation of the CPU feature register ABI.
89 */
5e49d73c 90static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
fe4fbdbc
SP		 91 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
92 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
93 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
94 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
95 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
96 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
3c739b57
SP		 97 ARM64_FTR_END,
98};
99
5e49d73c 100static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
fe4fbdbc
SP		 101 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
102 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
103 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
3c739b57 104 /* Linux doesn't care about the EL3 */
fe4fbdbc
SP		 105 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
106 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
107 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
108 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
3c739b57
SP		 109 ARM64_FTR_END,
110};
111
5e49d73c 112static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
fe4fbdbc
SP		 113 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
114 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
115 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
116 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
3c739b57 117 /* Linux shouldn't care about secure memory */
fe4fbdbc
SP		 118 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
119 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
120 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
3c739b57
SP		 121 /*
122 * Differing PARange is fine as long as all peripherals and memory are mapped
123 * within the minimum PARange of all CPUs
124 */
fe4fbdbc 125 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
3c739b57
SP		 126 ARM64_FTR_END,
127};
128
5e49d73c 129static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
fe4fbdbc
SP		 130 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
131 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
132 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
133 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
134 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
135 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
3c739b57
SP		 136 ARM64_FTR_END,
137};
138
5e49d73c 139static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
fe4fbdbc
SP		 140 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
141 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
142 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
143 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
144 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
406e3087
JM		 145 ARM64_FTR_END,
146};
147
5e49d73c 148static const struct arm64_ftr_bits ftr_ctr[] = {
fe4fbdbc
SP		 149 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */
150 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
151 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
152 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
3c739b57
SP		 153 /*
154 * Linux can handle differing I-cache policies. Userspace JITs will
ee7bc638
SP		 155 * make use of *minLine.
156 * If we have differing I-cache policies, report it as the weakest - AIVIVT.
3c739b57 157 */
fe4fbdbc
SP		 158 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_AIVIVT), /* L1Ip */
159 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
3c739b57
SP		 160 ARM64_FTR_END,
161};
162
675b0563
AB		 163struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
164 .name = "SYS_CTR_EL0",
165 .ftr_bits = ftr_ctr
166};
167
5e49d73c 168static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
fe4fbdbc
SP		 169 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 28, 4, 0xf), /* InnerShr */
170 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */
171 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
172 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 16, 4, 0), /* TCM */
173 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 12, 4, 0), /* ShareLvl */
174 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 8, 4, 0xf), /* OuterShr */
175 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
176 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
3c739b57
SP		 177 ARM64_FTR_END,
178};
179
5e49d73c 180static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
fe4fbdbc
SP		 181 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
182 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
183 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
184 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
185 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
b20d1ba3
WD		 186 /*
187 * We can instantiate multiple PMU instances with different levels
188 * of support.
fe4fbdbc
SP		 189 */
190 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
191 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
192 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
3c739b57
SP		 193 ARM64_FTR_END,
194};
195
5e49d73c 196static const struct arm64_ftr_bits ftr_mvfr2[] = {
fe4fbdbc
SP		 197 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */
198 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */
3c739b57
SP		 199 ARM64_FTR_END,
200};
201
5e49d73c 202static const struct arm64_ftr_bits ftr_dczid[] = {
fe4fbdbc
SP		 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
3c739b57
SP		 205 ARM64_FTR_END,
206};
207
208
5e49d73c 209static const struct arm64_ftr_bits ftr_id_isar5[] = {
fe4fbdbc
SP		 210 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
211 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
212 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
213 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
214 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
3c739b57
SP		 216 ARM64_FTR_END,
217};
218
5e49d73c 219static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
fe4fbdbc 220 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */
3c739b57
SP		 221 ARM64_FTR_END,
222};
223
5e49d73c 224static const struct arm64_ftr_bits ftr_id_pfr0[] = {
fe4fbdbc
SP		 225 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */
226 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */
227 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */
228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0), /* State0 */
3c739b57
SP		 229 ARM64_FTR_END,
230};
231
5e49d73c 232static const struct arm64_ftr_bits ftr_id_dfr0[] = {
fe4fbdbc
SP		 233 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
234 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
235 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
237 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
238 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
239 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
240 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
e5343503
SP		 241 ARM64_FTR_END,
242};
243
3c739b57
SP		 244/*
245 * Common ftr bits for a 32bit register with all hidden, strict
246 * attributes, with 4bit feature fields and a default safe value of
247 * 0. Covers the following 32bit registers:
248 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
249 */
5e49d73c 250static const struct arm64_ftr_bits ftr_generic_32bits[] = {
fe4fbdbc
SP		 251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
252 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
253 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
254 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
255 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
256 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
257 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
258 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
3c739b57
SP		 259 ARM64_FTR_END,
260};
261
eab43e88
SP		 262/* Table for a single 32bit feature value */
263static const struct arm64_ftr_bits ftr_single32[] = {
fe4fbdbc 264 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
3c739b57
SP		 265 ARM64_FTR_END,
266};
267
eab43e88 268static const struct arm64_ftr_bits ftr_raz[] = {
3c739b57
SP		 269 ARM64_FTR_END,
270};
271
6f2b7eef
AB		 272#define ARM64_FTR_REG(id, table) { \
273 .sys_id = id, \
274 .reg = &(struct arm64_ftr_reg){ \
3c739b57
SP		 275 .name = #id, \
276 .ftr_bits = &((table)[0]), \
6f2b7eef 277 }}
3c739b57 278
6f2b7eef
AB		 279static const struct __ftr_reg_entry {
280 u32 sys_id;
281 struct arm64_ftr_reg *reg;
282} arm64_ftr_regs[] = {
3c739b57
SP		 283
284 /* Op1 = 0, CRn = 0, CRm = 1 */
285 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
286 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
e5343503 287 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
3c739b57
SP		 288 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
289 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
290 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
291 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
292
293 /* Op1 = 0, CRn = 0, CRm = 2 */
294 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
295 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
296 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
297 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
298 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
299 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
300 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
301
302 /* Op1 = 0, CRn = 0, CRm = 3 */
303 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
304 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
305 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
306
307 /* Op1 = 0, CRn = 0, CRm = 4 */
308 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
eab43e88 309 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_raz),
3c739b57
SP		 310
311 /* Op1 = 0, CRn = 0, CRm = 5 */
312 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
eab43e88 313 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
3c739b57
SP		 314
315 /* Op1 = 0, CRn = 0, CRm = 6 */
316 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
eab43e88 317 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_raz),
3c739b57
SP		 318
319 /* Op1 = 0, CRn = 0, CRm = 7 */
320 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
321 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
406e3087 322 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
3c739b57
SP		 323
324 /* Op1 = 3, CRn = 0, CRm = 0 */
675b0563 325 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
3c739b57
SP		 326 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
327
328 /* Op1 = 3, CRn = 14, CRm = 0 */
eab43e88 329 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
3c739b57
SP		 330};
331
332static int search_cmp_ftr_reg(const void *id, const void *regp)
333{
6f2b7eef 334 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
3c739b57
SP		 335}
336
337/*
338 * get_arm64_ftr_reg - Lookup a feature register entry using its
339 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
340 * ascending order of sys_id , we use binary search to find a matching
341 * entry.
342 *
343 * returns - Upon success, matching ftr_reg entry for id.
344 * - NULL on failure. It is upto the caller to decide
345 * the impact of a failure.
346 */
347static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
348{
6f2b7eef
AB		 349 const struct __ftr_reg_entry *ret;
350
351 ret = bsearch((const void *)(unsigned long)sys_id,
3c739b57
SP		 352 arm64_ftr_regs,
353 ARRAY_SIZE(arm64_ftr_regs),
354 sizeof(arm64_ftr_regs[0]),
355 search_cmp_ftr_reg);
6f2b7eef
AB		 356 if (ret)
357 return ret->reg;
358 return NULL;
3c739b57
SP		 359}
360
5e49d73c
AB		 361static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
362 s64 ftr_val)
3c739b57
SP		 363{
364 u64 mask = arm64_ftr_mask(ftrp);
365
366 reg &= ~mask;
367 reg |= (ftr_val << ftrp->shift) & mask;
368 return reg;
369}
370
5e49d73c
AB		 371static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
372 s64 cur)
3c739b57
SP		 373{
374 s64 ret = 0;
375
376 switch (ftrp->type) {
377 case FTR_EXACT:
378 ret = ftrp->safe_val;
379 break;
380 case FTR_LOWER_SAFE:
381 ret = new < cur ? new : cur;
382 break;
383 case FTR_HIGHER_SAFE:
384 ret = new > cur ? new : cur;
385 break;
386 default:
387 BUG();
388 }
389
390 return ret;
391}
392
3c739b57
SP		 393static void __init sort_ftr_regs(void)
394{
6f2b7eef
AB		 395 int i;
396
397 /* Check that the array is sorted so that we can do the binary search */
398 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
399 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
3c739b57
SP		 400}
401
402/*
403 * Initialise the CPU feature register from Boot CPU values.
404 * Also initiliases the strict_mask for the register.
b389d799
MR		 405 * Any bits that are not covered by an arm64_ftr_bits entry are considered
406 * RES0 for the system-wide value, and must strictly match.
3c739b57
SP		 407 */
408static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
409{
410 u64 val = 0;
411 u64 strict_mask = ~0x0ULL;
fe4fbdbc 412 u64 user_mask = 0;
b389d799
MR		 413 u64 valid_mask = 0;
414
5e49d73c 415 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 416 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
417
418 BUG_ON(!reg);
419
420 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
b389d799 421 u64 ftr_mask = arm64_ftr_mask(ftrp);
3c739b57
SP		 422 s64 ftr_new = arm64_ftr_value(ftrp, new);
423
424 val = arm64_ftr_set_value(ftrp, val, ftr_new);
b389d799
MR		 425
426 valid_mask |= ftr_mask;
3c739b57 427 if (!ftrp->strict)
b389d799 428 strict_mask &= ~ftr_mask;
fe4fbdbc
SP		 429 if (ftrp->visible)
430 user_mask |= ftr_mask;
431 else
432 reg->user_val = arm64_ftr_set_value(ftrp,
433 reg->user_val,
434 ftrp->safe_val);
3c739b57 435 }
b389d799
MR		 436
437 val &= valid_mask;
438
3c739b57
SP		 439 reg->sys_val = val;
440 reg->strict_mask = strict_mask;
fe4fbdbc 441 reg->user_mask = user_mask;
3c739b57
SP		 442}
443
444void __init init_cpu_features(struct cpuinfo_arm64 *info)
445{
446 /* Before we start using the tables, make sure it is sorted */
447 sort_ftr_regs();
448
449 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
450 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
451 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
452 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
453 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
454 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
455 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
456 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
457 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
406e3087 458 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
3c739b57
SP		 459 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
460 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
a6dc3cd7
SP		 461
462 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
463 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
464 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
465 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
466 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
467 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
468 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
469 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
470 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
471 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
472 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
473 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
474 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
475 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
476 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
477 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
478 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
479 }
480
3c739b57
SP		 481}
482
3086d391 483static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
3c739b57 484{
5e49d73c 485 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 486
487 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
488 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
489 s64 ftr_new = arm64_ftr_value(ftrp, new);
490
491 if (ftr_cur == ftr_new)
492 continue;
493 /* Find a safe value */
494 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
495 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
496 }
497
498}
499
3086d391 500static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
cdcf817b 501{
3086d391
SP		 502 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
503
504 BUG_ON(!regp);
505 update_cpu_ftr_reg(regp, val);
506 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
507 return 0;
508 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
509 regp->name, boot, cpu, val);
510 return 1;
511}
512
513/*
514 * Update system wide CPU feature registers with the values from a
515 * non-boot CPU. Also performs SANITY checks to make sure that there
516 * aren't any insane variations from that of the boot CPU.
517 */
518void update_cpu_features(int cpu,
519 struct cpuinfo_arm64 *info,
520 struct cpuinfo_arm64 *boot)
521{
522 int taint = 0;
523
524 /*
525 * The kernel can handle differing I-cache policies, but otherwise
526 * caches should look identical. Userspace JITs will make use of
527 * *minLine.
528 */
529 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
530 info->reg_ctr, boot->reg_ctr);
531
532 /*
533 * Userspace may perform DC ZVA instructions. Mismatched block sizes
534 * could result in too much or too little memory being zeroed if a
535 * process is preempted and migrated between CPUs.
536 */
537 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
538 info->reg_dczid, boot->reg_dczid);
539
540 /* If different, timekeeping will be broken (especially with KVM) */
541 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
542 info->reg_cntfrq, boot->reg_cntfrq);
543
544 /*
545 * The kernel uses self-hosted debug features and expects CPUs to
546 * support identical debug features. We presently need CTX_CMPs, WRPs,
547 * and BRPs to be identical.
548 * ID_AA64DFR1 is currently RES0.
549 */
550 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
551 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
552 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
553 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
554 /*
555 * Even in big.LITTLE, processors should be identical instruction-set
556 * wise.
557 */
558 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
559 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
560 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
561 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
562
563 /*
564 * Differing PARange support is fine as long as all peripherals and
565 * memory are mapped within the minimum PARange of all CPUs.
566 * Linux should not care about secure memory.
567 */
568 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
569 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
570 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
571 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
406e3087
JM		 572 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
573 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
3086d391
SP		 574
575 /*
576 * EL3 is not our concern.
577 * ID_AA64PFR1 is currently RES0.
578 */
579 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
580 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
581 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
582 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
583
584 /*
a6dc3cd7
SP		 585 * If we have AArch32, we care about 32-bit features for compat.
586 * If the system doesn't support AArch32, don't update them.
3086d391 587 */
a6dc3cd7
SP		 588 if (id_aa64pfr0_32bit_el0(read_system_reg(SYS_ID_AA64PFR0_EL1)) &&
589 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
590
591 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
3086d391 592 info->reg_id_dfr0, boot->reg_id_dfr0);
a6dc3cd7 593 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
3086d391 594 info->reg_id_isar0, boot->reg_id_isar0);
a6dc3cd7 595 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
3086d391 596 info->reg_id_isar1, boot->reg_id_isar1);
a6dc3cd7 597 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
3086d391 598 info->reg_id_isar2, boot->reg_id_isar2);
a6dc3cd7 599 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
3086d391 600 info->reg_id_isar3, boot->reg_id_isar3);
a6dc3cd7 601 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
3086d391 602 info->reg_id_isar4, boot->reg_id_isar4);
a6dc3cd7 603 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
3086d391
SP		 604 info->reg_id_isar5, boot->reg_id_isar5);
605
a6dc3cd7
SP		 606 /*
607 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
608 * ACTLR formats could differ across CPUs and therefore would have to
609 * be trapped for virtualization anyway.
610 */
611 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
3086d391 612 info->reg_id_mmfr0, boot->reg_id_mmfr0);
a6dc3cd7 613 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
3086d391 614 info->reg_id_mmfr1, boot->reg_id_mmfr1);
a6dc3cd7 615 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
3086d391 616 info->reg_id_mmfr2, boot->reg_id_mmfr2);
a6dc3cd7 617 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
3086d391 618 info->reg_id_mmfr3, boot->reg_id_mmfr3);
a6dc3cd7 619 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
3086d391 620 info->reg_id_pfr0, boot->reg_id_pfr0);
a6dc3cd7 621 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
3086d391 622 info->reg_id_pfr1, boot->reg_id_pfr1);
a6dc3cd7 623 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
3086d391 624 info->reg_mvfr0, boot->reg_mvfr0);
a6dc3cd7 625 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
3086d391 626 info->reg_mvfr1, boot->reg_mvfr1);
a6dc3cd7 627 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
3086d391 628 info->reg_mvfr2, boot->reg_mvfr2);
a6dc3cd7 629 }
3086d391
SP		 630
631 /*
632 * Mismatched CPU features are a recipe for disaster. Don't even
633 * pretend to support them.
634 */
635 WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
636 "Unsupported CPU feature variation.\n");
cdcf817b
SP		 637}
638
b3f15378
SP		 639u64 read_system_reg(u32 id)
640{
641 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
642
643 /* We shouldn't get a request for an unsupported register */
644 BUG_ON(!regp);
645 return regp->sys_val;
646}
359b7064 647
92406f0c
SP		 648/*
649 * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
650 * Read the system register on the current CPU
651 */
652static u64 __raw_read_system_reg(u32 sys_id)
653{
654 switch (sys_id) {
655 case SYS_ID_PFR0_EL1: return read_cpuid(ID_PFR0_EL1);
656 case SYS_ID_PFR1_EL1: return read_cpuid(ID_PFR1_EL1);
657 case SYS_ID_DFR0_EL1: return read_cpuid(ID_DFR0_EL1);
658 case SYS_ID_MMFR0_EL1: return read_cpuid(ID_MMFR0_EL1);
659 case SYS_ID_MMFR1_EL1: return read_cpuid(ID_MMFR1_EL1);
660 case SYS_ID_MMFR2_EL1: return read_cpuid(ID_MMFR2_EL1);
661 case SYS_ID_MMFR3_EL1: return read_cpuid(ID_MMFR3_EL1);
662 case SYS_ID_ISAR0_EL1: return read_cpuid(ID_ISAR0_EL1);
663 case SYS_ID_ISAR1_EL1: return read_cpuid(ID_ISAR1_EL1);
664 case SYS_ID_ISAR2_EL1: return read_cpuid(ID_ISAR2_EL1);
665 case SYS_ID_ISAR3_EL1: return read_cpuid(ID_ISAR3_EL1);
666 case SYS_ID_ISAR4_EL1: return read_cpuid(ID_ISAR4_EL1);
667 case SYS_ID_ISAR5_EL1: return read_cpuid(ID_ISAR4_EL1);
668 case SYS_MVFR0_EL1: return read_cpuid(MVFR0_EL1);
669 case SYS_MVFR1_EL1: return read_cpuid(MVFR1_EL1);
670 case SYS_MVFR2_EL1: return read_cpuid(MVFR2_EL1);
671
672 case SYS_ID_AA64PFR0_EL1: return read_cpuid(ID_AA64PFR0_EL1);
673 case SYS_ID_AA64PFR1_EL1: return read_cpuid(ID_AA64PFR0_EL1);
674 case SYS_ID_AA64DFR0_EL1: return read_cpuid(ID_AA64DFR0_EL1);
675 case SYS_ID_AA64DFR1_EL1: return read_cpuid(ID_AA64DFR0_EL1);
676 case SYS_ID_AA64MMFR0_EL1: return read_cpuid(ID_AA64MMFR0_EL1);
677 case SYS_ID_AA64MMFR1_EL1: return read_cpuid(ID_AA64MMFR1_EL1);
678 case SYS_ID_AA64MMFR2_EL1: return read_cpuid(ID_AA64MMFR2_EL1);
679 case SYS_ID_AA64ISAR0_EL1: return read_cpuid(ID_AA64ISAR0_EL1);
680 case SYS_ID_AA64ISAR1_EL1: return read_cpuid(ID_AA64ISAR1_EL1);
681
682 case SYS_CNTFRQ_EL0: return read_cpuid(CNTFRQ_EL0);
683 case SYS_CTR_EL0: return read_cpuid(CTR_EL0);
684 case SYS_DCZID_EL0: return read_cpuid(DCZID_EL0);
685 default:
686 BUG();
687 return 0;
688 }
689}
690
963fcd40
MZ		 691#include <linux/irqchip/arm-gic-v3.h>
692
18ffa046
JM		 693static bool
694feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
695{
28c5dcb2 696 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
18ffa046
JM		 697
698 return val >= entry->min_field_value;
699}
700
da8d02d1 701static bool
92406f0c 702has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
da8d02d1
SP		 703{
704 u64 val;
94a9e04a 705
92406f0c
SP		 706 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
707 if (scope == SCOPE_SYSTEM)
708 val = read_system_reg(entry->sys_reg);
709 else
710 val = __raw_read_system_reg(entry->sys_reg);
711
da8d02d1
SP		 712 return feature_matches(val, entry);
713}
338d4f49 714
92406f0c 715static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
963fcd40
MZ		 716{
717 bool has_sre;
718
92406f0c 719 if (!has_cpuid_feature(entry, scope))
963fcd40
MZ		 720 return false;
721
722 has_sre = gic_enable_sre();
723 if (!has_sre)
724 pr_warn_once("%s present but disabled by higher exception level\n",
725 entry->desc);
726
727 return has_sre;
728}
729
92406f0c 730static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
d5370f75
WD		 731{
732 u32 midr = read_cpuid_id();
733 u32 rv_min, rv_max;
734
735 /* Cavium ThunderX pass 1.x and 2.x */
736 rv_min = 0;
737 rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK;
738
739 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
740}
741
92406f0c 742static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
d88701be
MZ		 743{
744 return is_kernel_in_hyp_mode();
745}
746
d1745910
MZ		 747static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry,
748 int __unused)
749{
2077be67 750 phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start);
d1745910
MZ		 751
752 /*
753 * Activate the lower HYP offset only if:
754 * - the idmap doesn't clash with it,
755 * - the kernel is not running at EL2.
756 */
757 return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode();
758}
759
82e0191a
SP		 760static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
761{
762 u64 pfr0 = read_system_reg(SYS_ID_AA64PFR0_EL1);
763
764 return cpuid_feature_extract_signed_field(pfr0,
765 ID_AA64PFR0_FP_SHIFT) < 0;
766}
767
359b7064 768static const struct arm64_cpu_capabilities arm64_features[] = {
94a9e04a
MZ		 769 {
770 .desc = "GIC system register CPU interface",
771 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
92406f0c 772 .def_scope = SCOPE_SYSTEM,
963fcd40 773 .matches = has_useable_gicv3_cpuif,
da8d02d1
SP		 774 .sys_reg = SYS_ID_AA64PFR0_EL1,
775 .field_pos = ID_AA64PFR0_GIC_SHIFT,
ff96f7bc 776 .sign = FTR_UNSIGNED,
18ffa046 777 .min_field_value = 1,
94a9e04a 778 },
338d4f49
JM		 779#ifdef CONFIG_ARM64_PAN
780 {
781 .desc = "Privileged Access Never",
782 .capability = ARM64_HAS_PAN,
92406f0c 783 .def_scope = SCOPE_SYSTEM,
da8d02d1
SP		 784 .matches = has_cpuid_feature,
785 .sys_reg = SYS_ID_AA64MMFR1_EL1,
786 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
ff96f7bc 787 .sign = FTR_UNSIGNED,
338d4f49
JM		 788 .min_field_value = 1,
789 .enable = cpu_enable_pan,
790 },
791#endif /* CONFIG_ARM64_PAN */
2e94da13
WD		 792#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
793 {
794 .desc = "LSE atomic instructions",
795 .capability = ARM64_HAS_LSE_ATOMICS,
92406f0c 796 .def_scope = SCOPE_SYSTEM,
da8d02d1
SP		 797 .matches = has_cpuid_feature,
798 .sys_reg = SYS_ID_AA64ISAR0_EL1,
799 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
ff96f7bc 800 .sign = FTR_UNSIGNED,
2e94da13
WD		 801 .min_field_value = 2,
802 },
803#endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
d5370f75
WD		 804 {
805 .desc = "Software prefetching using PRFM",
806 .capability = ARM64_HAS_NO_HW_PREFETCH,
92406f0c 807 .def_scope = SCOPE_SYSTEM,
d5370f75
WD		 808 .matches = has_no_hw_prefetch,
809 },
57f4959b
JM		 810#ifdef CONFIG_ARM64_UAO
811 {
812 .desc = "User Access Override",
813 .capability = ARM64_HAS_UAO,
92406f0c 814 .def_scope = SCOPE_SYSTEM,
57f4959b
JM		 815 .matches = has_cpuid_feature,
816 .sys_reg = SYS_ID_AA64MMFR2_EL1,
817 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
818 .min_field_value = 1,
c8b06e3f
JM		 819 /*
820 * We rely on stop_machine() calling uao_thread_switch() to set
821 * UAO immediately after patching.
822 */
57f4959b
JM		 823 },
824#endif /* CONFIG_ARM64_UAO */
70544196
JM		 825#ifdef CONFIG_ARM64_PAN
826 {
827 .capability = ARM64_ALT_PAN_NOT_UAO,
92406f0c 828 .def_scope = SCOPE_SYSTEM,
70544196
JM		 829 .matches = cpufeature_pan_not_uao,
830 },
831#endif /* CONFIG_ARM64_PAN */
d88701be
MZ		 832 {
833 .desc = "Virtualization Host Extensions",
834 .capability = ARM64_HAS_VIRT_HOST_EXTN,
92406f0c 835 .def_scope = SCOPE_SYSTEM,
d88701be
MZ		 836 .matches = runs_at_el2,
837 },
042446a3
SP		 838 {
839 .desc = "32-bit EL0 Support",
840 .capability = ARM64_HAS_32BIT_EL0,
92406f0c 841 .def_scope = SCOPE_SYSTEM,
042446a3
SP		 842 .matches = has_cpuid_feature,
843 .sys_reg = SYS_ID_AA64PFR0_EL1,
844 .sign = FTR_UNSIGNED,
845 .field_pos = ID_AA64PFR0_EL0_SHIFT,
846 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
847 },
d1745910
MZ		 848 {
849 .desc = "Reduced HYP mapping offset",
850 .capability = ARM64_HYP_OFFSET_LOW,
851 .def_scope = SCOPE_SYSTEM,
852 .matches = hyp_offset_low,
853 },
82e0191a
SP		 854 {
855 /* FP/SIMD is not implemented */
856 .capability = ARM64_HAS_NO_FPSIMD,
857 .def_scope = SCOPE_SYSTEM,
858 .min_field_value = 0,
859 .matches = has_no_fpsimd,
860 },
359b7064
MZ		 861 {},
862};
863
ff96f7bc 864#define HWCAP_CAP(reg, field, s, min_value, type, cap) \
37b01d53
SP		 865 { \
866 .desc = #cap, \
92406f0c 867 .def_scope = SCOPE_SYSTEM, \
37b01d53
SP		 868 .matches = has_cpuid_feature, \
869 .sys_reg = reg, \
870 .field_pos = field, \
ff96f7bc 871 .sign = s, \
37b01d53
SP		 872 .min_field_value = min_value, \
873 .hwcap_type = type, \
874 .hwcap = cap, \
875 }
876
f3efb675 877static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
ff96f7bc
SP		 878 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
879 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
880 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
881 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
882 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
883 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
884 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
bf500618 885 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
ff96f7bc 886 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
bf500618 887 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
75283501
SP		 888 {},
889};
890
891static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
37b01d53 892#ifdef CONFIG_COMPAT
ff96f7bc
SP		 893 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
894 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
895 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
896 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
897 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
37b01d53
SP		 898#endif
899 {},
900};
901
f3efb675 902static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 903{
904 switch (cap->hwcap_type) {
905 case CAP_HWCAP:
906 elf_hwcap |= cap->hwcap;
907 break;
908#ifdef CONFIG_COMPAT
909 case CAP_COMPAT_HWCAP:
910 compat_elf_hwcap |= (u32)cap->hwcap;
911 break;
912 case CAP_COMPAT_HWCAP2:
913 compat_elf_hwcap2 |= (u32)cap->hwcap;
914 break;
915#endif
916 default:
917 WARN_ON(1);
918 break;
919 }
920}
921
922/* Check if we have a particular HWCAP enabled */
f3efb675 923static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 924{
925 bool rc;
926
927 switch (cap->hwcap_type) {
928 case CAP_HWCAP:
929 rc = (elf_hwcap & cap->hwcap) != 0;
930 break;
931#ifdef CONFIG_COMPAT
932 case CAP_COMPAT_HWCAP:
933 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
934 break;
935 case CAP_COMPAT_HWCAP2:
936 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
937 break;
938#endif
939 default:
940 WARN_ON(1);
941 rc = false;
942 }
943
944 return rc;
945}
946
75283501 947static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
37b01d53 948{
77c97b4e
SP		 949 /* We support emulation of accesses to CPU ID feature registers */
950 elf_hwcap |= HWCAP_CPUID;
75283501 951 for (; hwcaps->matches; hwcaps++)
92406f0c 952 if (hwcaps->matches(hwcaps, hwcaps->def_scope))
75283501 953 cap_set_elf_hwcap(hwcaps);
37b01d53
SP		 954}
955
ce8b602c 956void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
359b7064
MZ		 957 const char *info)
958{
75283501 959 for (; caps->matches; caps++) {
92406f0c 960 if (!caps->matches(caps, caps->def_scope))
359b7064
MZ		 961 continue;
962
75283501
SP		 963 if (!cpus_have_cap(caps->capability) && caps->desc)
964 pr_info("%s %s\n", info, caps->desc);
965 cpus_set_cap(caps->capability);
359b7064 966 }
ce8b602c
SP		 967}
968
969/*
dbb4e152
SP		 970 * Run through the enabled capabilities and enable() it on all active
971 * CPUs
ce8b602c 972 */
8e231852 973void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
ce8b602c 974{
75283501
SP		 975 for (; caps->matches; caps++)
976 if (caps->enable && cpus_have_cap(caps->capability))
2a6dcb2b
JM		 977 /*
978 * Use stop_machine() as it schedules the work allowing
979 * us to modify PSTATE, instead of on_each_cpu() which
980 * uses an IPI, giving us a PSTATE that disappears when
981 * we return.
982 */
983 stop_machine(caps->enable, NULL, cpu_online_mask);
dbb4e152
SP		 984}
985
dbb4e152
SP		 986/*
987 * Flag to indicate if we have computed the system wide
988 * capabilities based on the boot time active CPUs. This
989 * will be used to determine if a new booting CPU should
990 * go through the verification process to make sure that it
991 * supports the system capabilities, without using a hotplug
992 * notifier.
993 */
994static bool sys_caps_initialised;
995
996static inline void set_sys_caps_initialised(void)
997{
998 sys_caps_initialised = true;
999}
1000
1001/*
13f417f3
SP		 1002 * Check for CPU features that are used in early boot
1003 * based on the Boot CPU value.
dbb4e152 1004 */
13f417f3 1005static void check_early_cpu_features(void)
dbb4e152 1006{
ac1ad20f 1007 verify_cpu_run_el();
13f417f3 1008 verify_cpu_asid_bits();
dbb4e152 1009}
1c076303 1010
75283501
SP		 1011static void
1012verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1013{
1014
92406f0c
SP		 1015 for (; caps->matches; caps++)
1016 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP		 1017 pr_crit("CPU%d: missing HWCAP: %s\n",
1018 smp_processor_id(), caps->desc);
1019 cpu_die_early();
1020 }
75283501
SP		 1021}
1022
1023static void
1024verify_local_cpu_features(const struct arm64_cpu_capabilities *caps)
1025{
1026 for (; caps->matches; caps++) {
92406f0c 1027 if (!cpus_have_cap(caps->capability))
75283501
SP		 1028 continue;
1029 /*
1030 * If the new CPU misses an advertised feature, we cannot proceed
1031 * further, park the cpu.
1032 */
92406f0c 1033 if (!caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP		 1034 pr_crit("CPU%d: missing feature: %s\n",
1035 smp_processor_id(), caps->desc);
1036 cpu_die_early();
1037 }
1038 if (caps->enable)
1039 caps->enable(NULL);
1040 }
1041}
1042
dbb4e152
SP		 1043/*
1044 * Run through the enabled system capabilities and enable() it on this CPU.
1045 * The capabilities were decided based on the available CPUs at the boot time.
1046 * Any new CPU should match the system wide status of the capability. If the
1047 * new CPU doesn't have a capability which the system now has enabled, we
1048 * cannot do anything to fix it up and could cause unexpected failures. So
1049 * we park the CPU.
1050 */
c47a1900 1051static void verify_local_cpu_capabilities(void)
dbb4e152 1052{
c47a1900
SP		 1053 verify_local_cpu_errata_workarounds();
1054 verify_local_cpu_features(arm64_features);
1055 verify_local_elf_hwcaps(arm64_elf_hwcaps);
1056 if (system_supports_32bit_el0())
1057 verify_local_elf_hwcaps(compat_elf_hwcaps);
1058}
dbb4e152 1059
c47a1900
SP		 1060void check_local_cpu_capabilities(void)
1061{
1062 /*
1063 * All secondary CPUs should conform to the early CPU features
1064 * in use by the kernel based on boot CPU.
1065 */
13f417f3
SP		 1066 check_early_cpu_features();
1067
dbb4e152 1068 /*
c47a1900
SP		 1069 * If we haven't finalised the system capabilities, this CPU gets
1070 * a chance to update the errata work arounds.
1071 * Otherwise, this CPU should verify that it has all the system
1072 * advertised capabilities.
dbb4e152
SP		 1073 */
1074 if (!sys_caps_initialised)
c47a1900
SP		 1075 update_cpu_errata_workarounds();
1076 else
1077 verify_local_cpu_capabilities();
359b7064
MZ		 1078}
1079
a7c61a34 1080static void __init setup_feature_capabilities(void)
359b7064 1081{
ce8b602c
SP		 1082 update_cpu_capabilities(arm64_features, "detected feature:");
1083 enable_cpu_capabilities(arm64_features);
359b7064
MZ		 1084}
1085
e3661b12
MZ		 1086/*
1087 * Check if the current CPU has a given feature capability.
1088 * Should be called from non-preemptible context.
1089 */
1090bool this_cpu_has_cap(unsigned int cap)
1091{
1092 const struct arm64_cpu_capabilities *caps;
1093
1094 if (WARN_ON(preemptible()))
1095 return false;
1096
1097 for (caps = arm64_features; caps->desc; caps++)
1098 if (caps->capability == cap && caps->matches)
1099 return caps->matches(caps, SCOPE_LOCAL_CPU);
1100
1101 return false;
1102}
1103
9cdf8ec4 1104void __init setup_cpu_features(void)
359b7064 1105{
9cdf8ec4
SP		 1106 u32 cwg;
1107 int cls;
1108
dbb4e152
SP		 1109 /* Set the CPU feature capabilies */
1110 setup_feature_capabilities();
8e231852 1111 enable_errata_workarounds();
75283501 1112 setup_elf_hwcaps(arm64_elf_hwcaps);
643d703d
SP		 1113
1114 if (system_supports_32bit_el0())
1115 setup_elf_hwcaps(compat_elf_hwcaps);
dbb4e152
SP		 1116
1117 /* Advertise that we have computed the system capabilities */
1118 set_sys_caps_initialised();
1119
9cdf8ec4
SP		 1120 /*
1121 * Check for sane CTR_EL0.CWG value.
1122 */
1123 cwg = cache_type_cwg();
1124 cls = cache_line_size();
1125 if (!cwg)
1126 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1127 cls);
1128 if (L1_CACHE_BYTES < cls)
1129 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1130 L1_CACHE_BYTES, cls);
359b7064 1131}
70544196
JM		 1132
1133static bool __maybe_unused
92406f0c 1134cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
70544196 1135{
a4023f68 1136 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
70544196 1137}
77c97b4e
SP		 1138
1139/*
1140 * We emulate only the following system register space.
1141 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1142 * See Table C5-6 System instruction encodings for System register accesses,
1143 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1144 */
1145static inline bool __attribute_const__ is_emulated(u32 id)
1146{
1147 return (sys_reg_Op0(id) == 0x3 &&
1148 sys_reg_CRn(id) == 0x0 &&
1149 sys_reg_Op1(id) == 0x0 &&
1150 (sys_reg_CRm(id) == 0 ||
1151 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
1152}
1153
1154/*
1155 * With CRm == 0, reg should be one of :
1156 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1157 */
1158static inline int emulate_id_reg(u32 id, u64 *valp)
1159{
1160 switch (id) {
1161 case SYS_MIDR_EL1:
1162 *valp = read_cpuid_id();
1163 break;
1164 case SYS_MPIDR_EL1:
1165 *valp = SYS_MPIDR_SAFE_VAL;
1166 break;
1167 case SYS_REVIDR_EL1:
1168 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1169 *valp = 0;
1170 break;
1171 default:
1172 return -EINVAL;
1173 }
1174
1175 return 0;
1176}
1177
1178static int emulate_sys_reg(u32 id, u64 *valp)
1179{
1180 struct arm64_ftr_reg *regp;
1181
1182 if (!is_emulated(id))
1183 return -EINVAL;
1184
1185 if (sys_reg_CRm(id) == 0)
1186 return emulate_id_reg(id, valp);
1187
1188 regp = get_arm64_ftr_reg(id);
1189 if (regp)
1190 *valp = arm64_ftr_reg_user_value(regp);
1191 else
1192 /*
1193 * The untracked registers are either IMPLEMENTATION DEFINED
1194 * (e.g, ID_AFR0_EL1) or reserved RAZ.
1195 */
1196 *valp = 0;
1197 return 0;
1198}
1199
1200static int emulate_mrs(struct pt_regs *regs, u32 insn)
1201{
1202 int rc;
1203 u32 sys_reg, dst;
1204 u64 val;
1205
1206 /*
1207 * sys_reg values are defined as used in mrs/msr instruction.
1208 * shift the imm value to get the encoding.
1209 */
1210 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
1211 rc = emulate_sys_reg(sys_reg, &val);
1212 if (!rc) {
1213 dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
1214 regs->user_regs.regs[dst] = val;
1215 regs->pc += 4;
1216 }
1217
1218 return rc;
1219}
1220
1221static struct undef_hook mrs_hook = {
1222 .instr_mask = 0xfff00000,
1223 .instr_val = 0xd5300000,
1224 .pstate_mask = COMPAT_PSR_MODE_MASK,
1225 .pstate_val = PSR_MODE_EL0t,
1226 .fn = emulate_mrs,
1227};
1228
1229static int __init enable_mrs_emulation(void)
1230{
1231 register_undef_hook(&mrs_hook);
1232 return 0;
1233}
1234
1235late_initcall(enable_mrs_emulation);
Linux 6.x block layer and io_uring tree(s)