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arm64: capabilities: Add flags to handle the conflicts on late CPU
[linux-2.6-block.git] / arch / arm64 / kernel / cpufeature.c
CommitLineData
359b7064
MZ		 1/*
2 * Contains CPU feature definitions
3 *
4 * Copyright (C) 2015 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
9cdf8ec4 19#define pr_fmt(fmt) "CPU features: " fmt
359b7064 20
3c739b57 21#include <linux/bsearch.h>
2a6dcb2b 22#include <linux/cpumask.h>
3c739b57 23#include <linux/sort.h>
2a6dcb2b 24#include <linux/stop_machine.h>
359b7064 25#include <linux/types.h>
2077be67 26#include <linux/mm.h>
359b7064
MZ		 27#include <asm/cpu.h>
28#include <asm/cpufeature.h>
dbb4e152 29#include <asm/cpu_ops.h>
2e0f2478 30#include <asm/fpsimd.h>
13f417f3 31#include <asm/mmu_context.h>
338d4f49 32#include <asm/processor.h>
cdcf817b 33#include <asm/sysreg.h>
77c97b4e 34#include <asm/traps.h>
d88701be 35#include <asm/virt.h>
359b7064 36
9cdf8ec4
SP		 37unsigned long elf_hwcap __read_mostly;
38EXPORT_SYMBOL_GPL(elf_hwcap);
39
40#ifdef CONFIG_COMPAT
41#define COMPAT_ELF_HWCAP_DEFAULT \
42 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
43 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
44 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
45 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
46 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
47 COMPAT_HWCAP_LPAE)
48unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
49unsigned int compat_elf_hwcap2 __read_mostly;
50#endif
51
52DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
4b65a5db 53EXPORT_SYMBOL(cpu_hwcaps);
9cdf8ec4 54
8f1eec57
DM		 55/*
56 * Flag to indicate if we have computed the system wide
57 * capabilities based on the boot time active CPUs. This
58 * will be used to determine if a new booting CPU should
59 * go through the verification process to make sure that it
60 * supports the system capabilities, without using a hotplug
61 * notifier.
62 */
63static bool sys_caps_initialised;
64
65static inline void set_sys_caps_initialised(void)
66{
67 sys_caps_initialised = true;
68}
69
8effeaaf
MR		 70static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
71{
72 /* file-wide pr_fmt adds "CPU features: " prefix */
73 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
74 return 0;
75}
76
77static struct notifier_block cpu_hwcaps_notifier = {
78 .notifier_call = dump_cpu_hwcaps
79};
80
81static int __init register_cpu_hwcaps_dumper(void)
82{
83 atomic_notifier_chain_register(&panic_notifier_list,
84 &cpu_hwcaps_notifier);
85 return 0;
86}
87__initcall(register_cpu_hwcaps_dumper);
88
efd9e03f
CM		 89DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
90EXPORT_SYMBOL(cpu_hwcap_keys);
91
fe4fbdbc 92#define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
3c739b57 93 { \
4f0a606b 94 .sign = SIGNED, \
fe4fbdbc 95 .visible = VISIBLE, \
3c739b57
SP		 96 .strict = STRICT, \
97 .type = TYPE, \
98 .shift = SHIFT, \
99 .width = WIDTH, \
100 .safe_val = SAFE_VAL, \
101 }
102
0710cfdb 103/* Define a feature with unsigned values */
fe4fbdbc
SP		 104#define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
105 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
4f0a606b 106
0710cfdb 107/* Define a feature with a signed value */
fe4fbdbc
SP		 108#define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
109 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
0710cfdb 110
3c739b57
SP		 111#define ARM64_FTR_END \
112 { \
113 .width = 0, \
114 }
115
70544196
JM		 116/* meta feature for alternatives */
117static bool __maybe_unused
92406f0c
SP		 118cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
119
70544196 120
4aa8a472
SP		 121/*
122 * NOTE: Any changes to the visibility of features should be kept in
123 * sync with the documentation of the CPU feature register ABI.
124 */
5e49d73c 125static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
7206dc93 126 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
3b3b6810 127 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
5bdecb79
SP		 128 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
129 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
130 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
131 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
132 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
fe4fbdbc
SP		 133 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
134 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
135 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
136 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
137 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
3c739b57
SP		 138 ARM64_FTR_END,
139};
140
c8c3798d 141static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
5bdecb79
SP		 142 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
143 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
144 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
145 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
c8c3798d
SP		 146 ARM64_FTR_END,
147};
148
5e49d73c 149static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
179a56f6 150 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
0f15adbb 151 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
7206dc93 152 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
3fab3999
DM		 153 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
154 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
64c02720 155 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
5bdecb79 156 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
fe4fbdbc
SP		 157 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
158 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
3c739b57 159 /* Linux doesn't care about the EL3 */
5bdecb79
SP		 160 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
161 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
162 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
163 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
3c739b57
SP		 164 ARM64_FTR_END,
165};
166
5e49d73c 167static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
5bdecb79
SP		 168 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
169 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
170 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
171 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
3c739b57 172 /* Linux shouldn't care about secure memory */
5bdecb79
SP		 173 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
174 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
175 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
3c739b57
SP		 176 /*
177 * Differing PARange is fine as long as all peripherals and memory are mapped
178 * within the minimum PARange of all CPUs
179 */
fe4fbdbc 180 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
3c739b57
SP		 181 ARM64_FTR_END,
182};
183
5e49d73c 184static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
fe4fbdbc 185 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
5bdecb79
SP		 186 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
187 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
188 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
189 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
190 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
3c739b57
SP		 191 ARM64_FTR_END,
192};
193
5e49d73c 194static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
7206dc93 195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
5bdecb79
SP		 196 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
198 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
199 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
200 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
406e3087
JM		 201 ARM64_FTR_END,
202};
203
5e49d73c 204static const struct arm64_ftr_bits ftr_ctr[] = {
6ae4b6e0
SD		 205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
206 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
207 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
208 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_CWG_SHIFT, 4, 0),
209 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_ERG_SHIFT, 4, 0),
210 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
3c739b57
SP		 211 /*
212 * Linux can handle differing I-cache policies. Userspace JITs will
ee7bc638 213 * make use of *minLine.
155433cb 214 * If we have differing I-cache policies, report it as the weakest - VIPT.
3c739b57 215 */
155433cb 216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */
fe4fbdbc 217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
3c739b57
SP		 218 ARM64_FTR_END,
219};
220
675b0563
AB		 221struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
222 .name = "SYS_CTR_EL0",
223 .ftr_bits = ftr_ctr
224};
225
5e49d73c 226static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
5bdecb79
SP		 227 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */
228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */
fe4fbdbc 229 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
5bdecb79
SP		 230 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */
231 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */
232 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */
233 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */
234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */
3c739b57
SP		 235 ARM64_FTR_END,
236};
237
5e49d73c 238static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
fe4fbdbc
SP		 239 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
240 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
243 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
b20d1ba3
WD		 244 /*
245 * We can instantiate multiple PMU instances with different levels
246 * of support.
fe4fbdbc
SP		 247 */
248 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
3c739b57
SP		 251 ARM64_FTR_END,
252};
253
5e49d73c 254static const struct arm64_ftr_bits ftr_mvfr2[] = {
5bdecb79
SP		 255 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */
256 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */
3c739b57
SP		 257 ARM64_FTR_END,
258};
259
5e49d73c 260static const struct arm64_ftr_bits ftr_dczid[] = {
fe4fbdbc
SP		 261 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
262 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
3c739b57
SP		 263 ARM64_FTR_END,
264};
265
266
5e49d73c 267static const struct arm64_ftr_bits ftr_id_isar5[] = {
5bdecb79
SP		 268 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
269 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
270 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
271 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
272 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
273 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
3c739b57
SP		 274 ARM64_FTR_END,
275};
276
5e49d73c 277static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
5bdecb79 278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */
3c739b57
SP		 279 ARM64_FTR_END,
280};
281
5e49d73c 282static const struct arm64_ftr_bits ftr_id_pfr0[] = {
5bdecb79
SP		 283 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */
284 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */
285 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */
286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */
3c739b57
SP		 287 ARM64_FTR_END,
288};
289
5e49d73c 290static const struct arm64_ftr_bits ftr_id_dfr0[] = {
fe4fbdbc
SP		 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
292 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
297 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
e5343503
SP		 299 ARM64_FTR_END,
300};
301
2e0f2478
DM		 302static const struct arm64_ftr_bits ftr_zcr[] = {
303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
304 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
305 ARM64_FTR_END,
306};
307
3c739b57
SP		 308/*
309 * Common ftr bits for a 32bit register with all hidden, strict
310 * attributes, with 4bit feature fields and a default safe value of
311 * 0. Covers the following 32bit registers:
312 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
313 */
5e49d73c 314static const struct arm64_ftr_bits ftr_generic_32bits[] = {
fe4fbdbc
SP		 315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
317 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
318 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
319 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
3c739b57
SP		 323 ARM64_FTR_END,
324};
325
eab43e88
SP		 326/* Table for a single 32bit feature value */
327static const struct arm64_ftr_bits ftr_single32[] = {
fe4fbdbc 328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
3c739b57
SP		 329 ARM64_FTR_END,
330};
331
eab43e88 332static const struct arm64_ftr_bits ftr_raz[] = {
3c739b57
SP		 333 ARM64_FTR_END,
334};
335
6f2b7eef
AB		 336#define ARM64_FTR_REG(id, table) { \
337 .sys_id = id, \
338 .reg = &(struct arm64_ftr_reg){ \
3c739b57
SP		 339 .name = #id, \
340 .ftr_bits = &((table)[0]), \
6f2b7eef 341 }}
3c739b57 342
6f2b7eef
AB		 343static const struct __ftr_reg_entry {
344 u32 sys_id;
345 struct arm64_ftr_reg *reg;
346} arm64_ftr_regs[] = {
3c739b57
SP		 347
348 /* Op1 = 0, CRn = 0, CRm = 1 */
349 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
350 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
e5343503 351 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
3c739b57
SP		 352 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
353 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
354 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
355 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
356
357 /* Op1 = 0, CRn = 0, CRm = 2 */
358 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
359 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
360 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
361 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
362 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
363 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
364 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
365
366 /* Op1 = 0, CRn = 0, CRm = 3 */
367 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
368 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
369 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
370
371 /* Op1 = 0, CRn = 0, CRm = 4 */
372 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
eab43e88 373 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_raz),
2e0f2478 374 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz),
3c739b57
SP		 375
376 /* Op1 = 0, CRn = 0, CRm = 5 */
377 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
eab43e88 378 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
3c739b57
SP		 379
380 /* Op1 = 0, CRn = 0, CRm = 6 */
381 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
c8c3798d 382 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
3c739b57
SP		 383
384 /* Op1 = 0, CRn = 0, CRm = 7 */
385 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
386 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
406e3087 387 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
3c739b57 388
2e0f2478
DM		 389 /* Op1 = 0, CRn = 1, CRm = 2 */
390 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
391
3c739b57 392 /* Op1 = 3, CRn = 0, CRm = 0 */
675b0563 393 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
3c739b57
SP		 394 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
395
396 /* Op1 = 3, CRn = 14, CRm = 0 */
eab43e88 397 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
3c739b57
SP		 398};
399
400static int search_cmp_ftr_reg(const void *id, const void *regp)
401{
6f2b7eef 402 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
3c739b57
SP		 403}
404
405/*
406 * get_arm64_ftr_reg - Lookup a feature register entry using its
407 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
408 * ascending order of sys_id , we use binary search to find a matching
409 * entry.
410 *
411 * returns - Upon success, matching ftr_reg entry for id.
412 * - NULL on failure. It is upto the caller to decide
413 * the impact of a failure.
414 */
415static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
416{
6f2b7eef
AB		 417 const struct __ftr_reg_entry *ret;
418
419 ret = bsearch((const void *)(unsigned long)sys_id,
3c739b57
SP		 420 arm64_ftr_regs,
421 ARRAY_SIZE(arm64_ftr_regs),
422 sizeof(arm64_ftr_regs[0]),
423 search_cmp_ftr_reg);
6f2b7eef
AB		 424 if (ret)
425 return ret->reg;
426 return NULL;
3c739b57
SP		 427}
428
5e49d73c
AB		 429static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
430 s64 ftr_val)
3c739b57
SP		 431{
432 u64 mask = arm64_ftr_mask(ftrp);
433
434 reg &= ~mask;
435 reg |= (ftr_val << ftrp->shift) & mask;
436 return reg;
437}
438
5e49d73c
AB		 439static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
440 s64 cur)
3c739b57
SP		 441{
442 s64 ret = 0;
443
444 switch (ftrp->type) {
445 case FTR_EXACT:
446 ret = ftrp->safe_val;
447 break;
448 case FTR_LOWER_SAFE:
449 ret = new < cur ? new : cur;
450 break;
451 case FTR_HIGHER_SAFE:
452 ret = new > cur ? new : cur;
453 break;
454 default:
455 BUG();
456 }
457
458 return ret;
459}
460
3c739b57
SP		 461static void __init sort_ftr_regs(void)
462{
6f2b7eef
AB		 463 int i;
464
465 /* Check that the array is sorted so that we can do the binary search */
466 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
467 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
3c739b57
SP		 468}
469
470/*
471 * Initialise the CPU feature register from Boot CPU values.
472 * Also initiliases the strict_mask for the register.
b389d799
MR		 473 * Any bits that are not covered by an arm64_ftr_bits entry are considered
474 * RES0 for the system-wide value, and must strictly match.
3c739b57
SP		 475 */
476static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
477{
478 u64 val = 0;
479 u64 strict_mask = ~0x0ULL;
fe4fbdbc 480 u64 user_mask = 0;
b389d799
MR		 481 u64 valid_mask = 0;
482
5e49d73c 483 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 484 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
485
486 BUG_ON(!reg);
487
488 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
b389d799 489 u64 ftr_mask = arm64_ftr_mask(ftrp);
3c739b57
SP		 490 s64 ftr_new = arm64_ftr_value(ftrp, new);
491
492 val = arm64_ftr_set_value(ftrp, val, ftr_new);
b389d799
MR		 493
494 valid_mask |= ftr_mask;
3c739b57 495 if (!ftrp->strict)
b389d799 496 strict_mask &= ~ftr_mask;
fe4fbdbc
SP		 497 if (ftrp->visible)
498 user_mask |= ftr_mask;
499 else
500 reg->user_val = arm64_ftr_set_value(ftrp,
501 reg->user_val,
502 ftrp->safe_val);
3c739b57 503 }
b389d799
MR		 504
505 val &= valid_mask;
506
3c739b57
SP		 507 reg->sys_val = val;
508 reg->strict_mask = strict_mask;
fe4fbdbc 509 reg->user_mask = user_mask;
3c739b57
SP		 510}
511
1e89baed
SP		 512extern const struct arm64_cpu_capabilities arm64_errata[];
513static void update_cpu_errata_workarounds(void);
514
3c739b57
SP		 515void __init init_cpu_features(struct cpuinfo_arm64 *info)
516{
517 /* Before we start using the tables, make sure it is sorted */
518 sort_ftr_regs();
519
520 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
521 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
522 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
523 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
524 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
525 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
526 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
527 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
528 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
406e3087 529 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
3c739b57
SP		 530 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
531 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
2e0f2478 532 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
a6dc3cd7
SP		 533
534 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
535 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
536 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
537 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
538 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
539 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
540 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
541 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
542 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
543 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
544 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
545 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
546 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
547 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
548 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
549 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
550 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
551 }
552
2e0f2478
DM		 553 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
554 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
555 sve_init_vq_map();
556 }
5e91107b
SP		 557
558 /*
559 * Run the errata work around checks on the boot CPU, once we have
560 * initialised the cpu feature infrastructure.
561 */
562 update_cpu_errata_workarounds();
3c739b57
SP		 563}
564
3086d391 565static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
3c739b57 566{
5e49d73c 567 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 568
569 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
570 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
571 s64 ftr_new = arm64_ftr_value(ftrp, new);
572
573 if (ftr_cur == ftr_new)
574 continue;
575 /* Find a safe value */
576 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
577 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
578 }
579
580}
581
3086d391 582static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
cdcf817b 583{
3086d391
SP		 584 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
585
586 BUG_ON(!regp);
587 update_cpu_ftr_reg(regp, val);
588 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
589 return 0;
590 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
591 regp->name, boot, cpu, val);
592 return 1;
593}
594
595/*
596 * Update system wide CPU feature registers with the values from a
597 * non-boot CPU. Also performs SANITY checks to make sure that there
598 * aren't any insane variations from that of the boot CPU.
599 */
600void update_cpu_features(int cpu,
601 struct cpuinfo_arm64 *info,
602 struct cpuinfo_arm64 *boot)
603{
604 int taint = 0;
605
606 /*
607 * The kernel can handle differing I-cache policies, but otherwise
608 * caches should look identical. Userspace JITs will make use of
609 * *minLine.
610 */
611 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
612 info->reg_ctr, boot->reg_ctr);
613
614 /*
615 * Userspace may perform DC ZVA instructions. Mismatched block sizes
616 * could result in too much or too little memory being zeroed if a
617 * process is preempted and migrated between CPUs.
618 */
619 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
620 info->reg_dczid, boot->reg_dczid);
621
622 /* If different, timekeeping will be broken (especially with KVM) */
623 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
624 info->reg_cntfrq, boot->reg_cntfrq);
625
626 /*
627 * The kernel uses self-hosted debug features and expects CPUs to
628 * support identical debug features. We presently need CTX_CMPs, WRPs,
629 * and BRPs to be identical.
630 * ID_AA64DFR1 is currently RES0.
631 */
632 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
633 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
634 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
635 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
636 /*
637 * Even in big.LITTLE, processors should be identical instruction-set
638 * wise.
639 */
640 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
641 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
642 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
643 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
644
645 /*
646 * Differing PARange support is fine as long as all peripherals and
647 * memory are mapped within the minimum PARange of all CPUs.
648 * Linux should not care about secure memory.
649 */
650 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
651 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
652 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
653 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
406e3087
JM		 654 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
655 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
3086d391
SP		 656
657 /*
658 * EL3 is not our concern.
659 * ID_AA64PFR1 is currently RES0.
660 */
661 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
662 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
663 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
664 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
665
2e0f2478
DM		 666 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
667 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
668
3086d391 669 /*
a6dc3cd7
SP		 670 * If we have AArch32, we care about 32-bit features for compat.
671 * If the system doesn't support AArch32, don't update them.
3086d391 672 */
46823dd1 673 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
a6dc3cd7
SP		 674 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
675
676 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
3086d391 677 info->reg_id_dfr0, boot->reg_id_dfr0);
a6dc3cd7 678 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
3086d391 679 info->reg_id_isar0, boot->reg_id_isar0);
a6dc3cd7 680 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
3086d391 681 info->reg_id_isar1, boot->reg_id_isar1);
a6dc3cd7 682 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
3086d391 683 info->reg_id_isar2, boot->reg_id_isar2);
a6dc3cd7 684 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
3086d391 685 info->reg_id_isar3, boot->reg_id_isar3);
a6dc3cd7 686 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
3086d391 687 info->reg_id_isar4, boot->reg_id_isar4);
a6dc3cd7 688 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
3086d391
SP		 689 info->reg_id_isar5, boot->reg_id_isar5);
690
a6dc3cd7
SP		 691 /*
692 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
693 * ACTLR formats could differ across CPUs and therefore would have to
694 * be trapped for virtualization anyway.
695 */
696 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
3086d391 697 info->reg_id_mmfr0, boot->reg_id_mmfr0);
a6dc3cd7 698 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
3086d391 699 info->reg_id_mmfr1, boot->reg_id_mmfr1);
a6dc3cd7 700 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
3086d391 701 info->reg_id_mmfr2, boot->reg_id_mmfr2);
a6dc3cd7 702 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
3086d391 703 info->reg_id_mmfr3, boot->reg_id_mmfr3);
a6dc3cd7 704 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
3086d391 705 info->reg_id_pfr0, boot->reg_id_pfr0);
a6dc3cd7 706 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
3086d391 707 info->reg_id_pfr1, boot->reg_id_pfr1);
a6dc3cd7 708 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
3086d391 709 info->reg_mvfr0, boot->reg_mvfr0);
a6dc3cd7 710 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
3086d391 711 info->reg_mvfr1, boot->reg_mvfr1);
a6dc3cd7 712 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
3086d391 713 info->reg_mvfr2, boot->reg_mvfr2);
a6dc3cd7 714 }
3086d391 715
2e0f2478
DM		 716 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
717 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
718 info->reg_zcr, boot->reg_zcr);
719
720 /* Probe vector lengths, unless we already gave up on SVE */
721 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
722 !sys_caps_initialised)
723 sve_update_vq_map();
724 }
725
3086d391
SP		 726 /*
727 * Mismatched CPU features are a recipe for disaster. Don't even
728 * pretend to support them.
729 */
8dd0ee65
WD		 730 if (taint) {
731 pr_warn_once("Unsupported CPU feature variation detected.\n");
732 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
733 }
cdcf817b
SP		 734}
735
46823dd1 736u64 read_sanitised_ftr_reg(u32 id)
b3f15378
SP		 737{
738 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
739
740 /* We shouldn't get a request for an unsupported register */
741 BUG_ON(!regp);
742 return regp->sys_val;
743}
359b7064 744
965861d6
MR		 745#define read_sysreg_case(r) \
746 case r: return read_sysreg_s(r)
747
92406f0c 748/*
46823dd1 749 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
92406f0c
SP		 750 * Read the system register on the current CPU
751 */
46823dd1 752static u64 __read_sysreg_by_encoding(u32 sys_id)
92406f0c
SP		 753{
754 switch (sys_id) {
965861d6
MR		 755 read_sysreg_case(SYS_ID_PFR0_EL1);
756 read_sysreg_case(SYS_ID_PFR1_EL1);
757 read_sysreg_case(SYS_ID_DFR0_EL1);
758 read_sysreg_case(SYS_ID_MMFR0_EL1);
759 read_sysreg_case(SYS_ID_MMFR1_EL1);
760 read_sysreg_case(SYS_ID_MMFR2_EL1);
761 read_sysreg_case(SYS_ID_MMFR3_EL1);
762 read_sysreg_case(SYS_ID_ISAR0_EL1);
763 read_sysreg_case(SYS_ID_ISAR1_EL1);
764 read_sysreg_case(SYS_ID_ISAR2_EL1);
765 read_sysreg_case(SYS_ID_ISAR3_EL1);
766 read_sysreg_case(SYS_ID_ISAR4_EL1);
767 read_sysreg_case(SYS_ID_ISAR5_EL1);
768 read_sysreg_case(SYS_MVFR0_EL1);
769 read_sysreg_case(SYS_MVFR1_EL1);
770 read_sysreg_case(SYS_MVFR2_EL1);
771
772 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
773 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
774 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
775 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
776 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
777 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
778 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
779 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
780 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
781
782 read_sysreg_case(SYS_CNTFRQ_EL0);
783 read_sysreg_case(SYS_CTR_EL0);
784 read_sysreg_case(SYS_DCZID_EL0);
785
92406f0c
SP		 786 default:
787 BUG();
788 return 0;
789 }
790}
791
963fcd40
MZ		 792#include <linux/irqchip/arm-gic-v3.h>
793
18ffa046
JM		 794static bool
795feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
796{
28c5dcb2 797 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
18ffa046
JM		 798
799 return val >= entry->min_field_value;
800}
801
da8d02d1 802static bool
92406f0c 803has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
da8d02d1
SP		 804{
805 u64 val;
94a9e04a 806
92406f0c
SP		 807 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
808 if (scope == SCOPE_SYSTEM)
46823dd1 809 val = read_sanitised_ftr_reg(entry->sys_reg);
92406f0c 810 else
46823dd1 811 val = __read_sysreg_by_encoding(entry->sys_reg);
92406f0c 812
da8d02d1
SP		 813 return feature_matches(val, entry);
814}
338d4f49 815
92406f0c 816static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
963fcd40
MZ		 817{
818 bool has_sre;
819
92406f0c 820 if (!has_cpuid_feature(entry, scope))
963fcd40
MZ		 821 return false;
822
823 has_sre = gic_enable_sre();
824 if (!has_sre)
825 pr_warn_once("%s present but disabled by higher exception level\n",
826 entry->desc);
827
828 return has_sre;
829}
830
92406f0c 831static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
d5370f75
WD		 832{
833 u32 midr = read_cpuid_id();
d5370f75
WD		 834
835 /* Cavium ThunderX pass 1.x and 2.x */
fa5ce3d1
RR		 836 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
837 MIDR_CPU_VAR_REV(0, 0),
838 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
d5370f75
WD		 839}
840
92406f0c 841static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
d88701be
MZ		 842{
843 return is_kernel_in_hyp_mode();
844}
845
d1745910
MZ		 846static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry,
847 int __unused)
848{
2077be67 849 phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start);
d1745910
MZ		 850
851 /*
852 * Activate the lower HYP offset only if:
853 * - the idmap doesn't clash with it,
854 * - the kernel is not running at EL2.
855 */
856 return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode();
857}
858
82e0191a
SP		 859static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
860{
46823dd1 861 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
82e0191a
SP		 862
863 return cpuid_feature_extract_signed_field(pfr0,
864 ID_AA64PFR0_FP_SHIFT) < 0;
865}
866
6ae4b6e0
SD		 867static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
868 int __unused)
869{
870 return read_sanitised_ftr_reg(SYS_CTR_EL0) & BIT(CTR_IDC_SHIFT);
871}
872
873static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
874 int __unused)
875{
876 return read_sanitised_ftr_reg(SYS_CTR_EL0) & BIT(CTR_DIC_SHIFT);
877}
878
ea1e3de8
WD		 879#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
880static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
881
882static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
883 int __unused)
884{
6dc52b15 885 char const *str = "command line option";
179a56f6
WD		 886 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
887
6dc52b15
MZ		 888 /*
889 * For reasons that aren't entirely clear, enabling KPTI on Cavium
890 * ThunderX leads to apparent I-cache corruption of kernel text, which
891 * ends as well as you might imagine. Don't even try.
892 */
893 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
894 str = "ARM64_WORKAROUND_CAVIUM_27456";
895 __kpti_forced = -1;
896 }
897
898 /* Forced? */
ea1e3de8 899 if (__kpti_forced) {
6dc52b15
MZ		 900 pr_info_once("kernel page table isolation forced %s by %s\n",
901 __kpti_forced > 0 ? "ON" : "OFF", str);
ea1e3de8
WD		 902 return __kpti_forced > 0;
903 }
904
905 /* Useful for KASLR robustness */
906 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE))
907 return true;
908
0ba2e29c
J		 909 /* Don't force KPTI for CPUs that are not vulnerable */
910 switch (read_cpuid_id() & MIDR_CPU_MODEL_MASK) {
911 case MIDR_CAVIUM_THUNDERX2:
912 case MIDR_BRCM_VULCAN:
913 return false;
914 }
915
179a56f6
WD		 916 /* Defer to CPU feature registers */
917 return !cpuid_feature_extract_unsigned_field(pfr0,
918 ID_AA64PFR0_CSV3_SHIFT);
ea1e3de8
WD		 919}
920
c0cda3b8
DM		 921static void
922kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
f992b4df
WD		 923{
924 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
925 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
926 kpti_remap_fn *remap_fn;
927
928 static bool kpti_applied = false;
929 int cpu = smp_processor_id();
930
931 if (kpti_applied)
c0cda3b8 932 return;
f992b4df
WD		 933
934 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
935
936 cpu_install_idmap();
937 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
938 cpu_uninstall_idmap();
939
940 if (!cpu)
941 kpti_applied = true;
942
c0cda3b8 943 return;
f992b4df
WD		 944}
945
ea1e3de8
WD		 946static int __init parse_kpti(char *str)
947{
948 bool enabled;
949 int ret = strtobool(str, &enabled);
950
951 if (ret)
952 return ret;
953
954 __kpti_forced = enabled ? 1 : -1;
955 return 0;
956}
957__setup("kpti=", parse_kpti);
958#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
959
c0cda3b8 960static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
6d99b689
JM		 961{
962 /*
963 * Copy register values that aren't redirected by hardware.
964 *
965 * Before code patching, we only set tpidr_el1, all CPUs need to copy
966 * this value to tpidr_el2 before we patch the code. Once we've done
967 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
968 * do anything here.
969 */
970 if (!alternatives_applied)
971 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
6d99b689
JM		 972}
973
359b7064 974static const struct arm64_cpu_capabilities arm64_features[] = {
94a9e04a
MZ		 975 {
976 .desc = "GIC system register CPU interface",
977 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
5b4747c5 978 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
963fcd40 979 .matches = has_useable_gicv3_cpuif,
da8d02d1
SP		 980 .sys_reg = SYS_ID_AA64PFR0_EL1,
981 .field_pos = ID_AA64PFR0_GIC_SHIFT,
ff96f7bc 982 .sign = FTR_UNSIGNED,
18ffa046 983 .min_field_value = 1,
94a9e04a 984 },
338d4f49
JM		 985#ifdef CONFIG_ARM64_PAN
986 {
987 .desc = "Privileged Access Never",
988 .capability = ARM64_HAS_PAN,
5b4747c5 989 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
da8d02d1
SP		 990 .matches = has_cpuid_feature,
991 .sys_reg = SYS_ID_AA64MMFR1_EL1,
992 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
ff96f7bc 993 .sign = FTR_UNSIGNED,
338d4f49 994 .min_field_value = 1,
c0cda3b8 995 .cpu_enable = cpu_enable_pan,
338d4f49
JM		 996 },
997#endif /* CONFIG_ARM64_PAN */
2e94da13
WD		 998#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
999 {
1000 .desc = "LSE atomic instructions",
1001 .capability = ARM64_HAS_LSE_ATOMICS,
5b4747c5 1002 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
da8d02d1
SP		 1003 .matches = has_cpuid_feature,
1004 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1005 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
ff96f7bc 1006 .sign = FTR_UNSIGNED,
2e94da13
WD		 1007 .min_field_value = 2,
1008 },
1009#endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
d5370f75
WD		 1010 {
1011 .desc = "Software prefetching using PRFM",
1012 .capability = ARM64_HAS_NO_HW_PREFETCH,
5b4747c5 1013 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
d5370f75
WD		 1014 .matches = has_no_hw_prefetch,
1015 },
57f4959b
JM		 1016#ifdef CONFIG_ARM64_UAO
1017 {
1018 .desc = "User Access Override",
1019 .capability = ARM64_HAS_UAO,
5b4747c5 1020 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
57f4959b
JM		 1021 .matches = has_cpuid_feature,
1022 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1023 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1024 .min_field_value = 1,
c8b06e3f
JM		 1025 /*
1026 * We rely on stop_machine() calling uao_thread_switch() to set
1027 * UAO immediately after patching.
1028 */
57f4959b
JM		 1029 },
1030#endif /* CONFIG_ARM64_UAO */
70544196
JM		 1031#ifdef CONFIG_ARM64_PAN
1032 {
1033 .capability = ARM64_ALT_PAN_NOT_UAO,
5b4747c5 1034 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
70544196
JM		 1035 .matches = cpufeature_pan_not_uao,
1036 },
1037#endif /* CONFIG_ARM64_PAN */
d88701be
MZ		 1038 {
1039 .desc = "Virtualization Host Extensions",
1040 .capability = ARM64_HAS_VIRT_HOST_EXTN,
5b4747c5 1041 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
d88701be 1042 .matches = runs_at_el2,
c0cda3b8 1043 .cpu_enable = cpu_copy_el2regs,
d88701be 1044 },
042446a3
SP		 1045 {
1046 .desc = "32-bit EL0 Support",
1047 .capability = ARM64_HAS_32BIT_EL0,
5b4747c5 1048 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
042446a3
SP		 1049 .matches = has_cpuid_feature,
1050 .sys_reg = SYS_ID_AA64PFR0_EL1,
1051 .sign = FTR_UNSIGNED,
1052 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1053 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1054 },
d1745910
MZ		 1055 {
1056 .desc = "Reduced HYP mapping offset",
1057 .capability = ARM64_HYP_OFFSET_LOW,
5b4747c5 1058 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
d1745910
MZ		 1059 .matches = hyp_offset_low,
1060 },
ea1e3de8
WD		 1061#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1062 {
179a56f6 1063 .desc = "Kernel page table isolation (KPTI)",
ea1e3de8 1064 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
5b4747c5 1065 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
ea1e3de8 1066 .matches = unmap_kernel_at_el0,
c0cda3b8 1067 .cpu_enable = kpti_install_ng_mappings,
ea1e3de8
WD		 1068 },
1069#endif
82e0191a
SP		 1070 {
1071 /* FP/SIMD is not implemented */
1072 .capability = ARM64_HAS_NO_FPSIMD,
5b4747c5 1073 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
82e0191a
SP		 1074 .min_field_value = 0,
1075 .matches = has_no_fpsimd,
1076 },
d50e071f
RM		 1077#ifdef CONFIG_ARM64_PMEM
1078 {
1079 .desc = "Data cache clean to Point of Persistence",
1080 .capability = ARM64_HAS_DCPOP,
5b4747c5 1081 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
d50e071f
RM		 1082 .matches = has_cpuid_feature,
1083 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1084 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1085 .min_field_value = 1,
1086 },
1087#endif
43994d82
DM		 1088#ifdef CONFIG_ARM64_SVE
1089 {
1090 .desc = "Scalable Vector Extension",
5b4747c5 1091 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
43994d82 1092 .capability = ARM64_SVE,
43994d82
DM		 1093 .sys_reg = SYS_ID_AA64PFR0_EL1,
1094 .sign = FTR_UNSIGNED,
1095 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1096 .min_field_value = ID_AA64PFR0_SVE,
1097 .matches = has_cpuid_feature,
c0cda3b8 1098 .cpu_enable = sve_kernel_enable,
43994d82
DM		 1099 },
1100#endif /* CONFIG_ARM64_SVE */
64c02720
XX		 1101#ifdef CONFIG_ARM64_RAS_EXTN
1102 {
1103 .desc = "RAS Extension Support",
1104 .capability = ARM64_HAS_RAS_EXTN,
5b4747c5 1105 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
64c02720
XX		 1106 .matches = has_cpuid_feature,
1107 .sys_reg = SYS_ID_AA64PFR0_EL1,
1108 .sign = FTR_UNSIGNED,
1109 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1110 .min_field_value = ID_AA64PFR0_RAS_V1,
c0cda3b8 1111 .cpu_enable = cpu_clear_disr,
64c02720
XX		 1112 },
1113#endif /* CONFIG_ARM64_RAS_EXTN */
6ae4b6e0
SD		 1114 {
1115 .desc = "Data cache clean to the PoU not required for I/D coherence",
1116 .capability = ARM64_HAS_CACHE_IDC,
5b4747c5 1117 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
6ae4b6e0
SD		 1118 .matches = has_cache_idc,
1119 },
1120 {
1121 .desc = "Instruction cache invalidation not required for I/D coherence",
1122 .capability = ARM64_HAS_CACHE_DIC,
5b4747c5 1123 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
6ae4b6e0
SD		 1124 .matches = has_cache_dic,
1125 },
359b7064
MZ		 1126 {},
1127};
1128
143ba05d 1129#define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
37b01d53
SP		 1130 { \
1131 .desc = #cap, \
5b4747c5 1132 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
37b01d53
SP		 1133 .matches = has_cpuid_feature, \
1134 .sys_reg = reg, \
1135 .field_pos = field, \
ff96f7bc 1136 .sign = s, \
37b01d53 1137 .min_field_value = min_value, \
143ba05d 1138 .hwcap_type = cap_type, \
37b01d53
SP		 1139 .hwcap = cap, \
1140 }
1141
f3efb675 1142static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
ff96f7bc
SP		 1143 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
1144 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
1145 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
1146 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
f5e035f8 1147 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512),
ff96f7bc
SP		 1148 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
1149 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
f92f5ce0 1150 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM),
f5e035f8
SP		 1151 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3),
1152 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3),
1153 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4),
1154 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP),
3b3b6810 1155 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM),
7206dc93 1156 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FLAGM),
ff96f7bc 1157 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
bf500618 1158 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
ff96f7bc 1159 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
bf500618 1160 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
7206dc93 1161 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_DIT),
7aac405e 1162 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),
c8c3798d 1163 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
cb567e79 1164 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
c651aae5 1165 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
7206dc93
SP		 1166 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ILRCPC),
1167 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_USCAT),
43994d82
DM		 1168#ifdef CONFIG_ARM64_SVE
1169 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE),
1170#endif
75283501
SP		 1171 {},
1172};
1173
1174static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
37b01d53 1175#ifdef CONFIG_COMPAT
ff96f7bc
SP		 1176 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1177 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1178 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1179 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1180 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
37b01d53
SP		 1181#endif
1182 {},
1183};
1184
f3efb675 1185static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 1186{
1187 switch (cap->hwcap_type) {
1188 case CAP_HWCAP:
1189 elf_hwcap |= cap->hwcap;
1190 break;
1191#ifdef CONFIG_COMPAT
1192 case CAP_COMPAT_HWCAP:
1193 compat_elf_hwcap |= (u32)cap->hwcap;
1194 break;
1195 case CAP_COMPAT_HWCAP2:
1196 compat_elf_hwcap2 |= (u32)cap->hwcap;
1197 break;
1198#endif
1199 default:
1200 WARN_ON(1);
1201 break;
1202 }
1203}
1204
1205/* Check if we have a particular HWCAP enabled */
f3efb675 1206static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 1207{
1208 bool rc;
1209
1210 switch (cap->hwcap_type) {
1211 case CAP_HWCAP:
1212 rc = (elf_hwcap & cap->hwcap) != 0;
1213 break;
1214#ifdef CONFIG_COMPAT
1215 case CAP_COMPAT_HWCAP:
1216 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1217 break;
1218 case CAP_COMPAT_HWCAP2:
1219 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1220 break;
1221#endif
1222 default:
1223 WARN_ON(1);
1224 rc = false;
1225 }
1226
1227 return rc;
1228}
1229
75283501 1230static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
37b01d53 1231{
77c97b4e
SP		 1232 /* We support emulation of accesses to CPU ID feature registers */
1233 elf_hwcap |= HWCAP_CPUID;
75283501 1234 for (; hwcaps->matches; hwcaps++)
143ba05d 1235 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
75283501 1236 cap_set_elf_hwcap(hwcaps);
37b01d53
SP		 1237}
1238
67948af4
SP		 1239/*
1240 * Check if the current CPU has a given feature capability.
1241 * Should be called from non-preemptible context.
1242 */
1243static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array,
1244 unsigned int cap)
1245{
1246 const struct arm64_cpu_capabilities *caps;
1247
1248 if (WARN_ON(preemptible()))
1249 return false;
1250
edf298cf 1251 for (caps = cap_array; caps->matches; caps++)
67948af4 1252 if (caps->capability == cap &&
67948af4
SP		 1253 caps->matches(caps, SCOPE_LOCAL_CPU))
1254 return true;
1255 return false;
1256}
1257
1e89baed
SP		 1258static void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1259 const char *info)
359b7064 1260{
75283501 1261 for (; caps->matches; caps++) {
143ba05d 1262 if (!caps->matches(caps, cpucap_default_scope(caps)))
359b7064
MZ		 1263 continue;
1264
75283501
SP		 1265 if (!cpus_have_cap(caps->capability) && caps->desc)
1266 pr_info("%s %s\n", info, caps->desc);
1267 cpus_set_cap(caps->capability);
359b7064 1268 }
ce8b602c
SP		 1269}
1270
c0cda3b8
DM		 1271static int __enable_cpu_capability(void *arg)
1272{
1273 const struct arm64_cpu_capabilities *cap = arg;
1274
1275 cap->cpu_enable(cap);
1276 return 0;
1277}
1278
ce8b602c 1279/*
dbb4e152
SP		 1280 * Run through the enabled capabilities and enable() it on all active
1281 * CPUs
ce8b602c 1282 */
1e89baed
SP		 1283static void __init
1284enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
ce8b602c 1285{
63a1e1c9
MR		 1286 for (; caps->matches; caps++) {
1287 unsigned int num = caps->capability;
1288
1289 if (!cpus_have_cap(num))
1290 continue;
1291
1292 /* Ensure cpus_have_const_cap(num) works */
1293 static_branch_enable(&cpu_hwcap_keys[num]);
1294
c0cda3b8 1295 if (caps->cpu_enable) {
2a6dcb2b
JM		 1296 /*
1297 * Use stop_machine() as it schedules the work allowing
1298 * us to modify PSTATE, instead of on_each_cpu() which
1299 * uses an IPI, giving us a PSTATE that disappears when
1300 * we return.
1301 */
c0cda3b8
DM		 1302 stop_machine(__enable_cpu_capability, (void *)caps,
1303 cpu_online_mask);
63a1e1c9
MR		 1304 }
1305 }
dbb4e152
SP		 1306}
1307
dbb4e152 1308/*
13f417f3
SP		 1309 * Check for CPU features that are used in early boot
1310 * based on the Boot CPU value.
dbb4e152 1311 */
13f417f3 1312static void check_early_cpu_features(void)
dbb4e152 1313{
ac1ad20f 1314 verify_cpu_run_el();
13f417f3 1315 verify_cpu_asid_bits();
dbb4e152 1316}
1c076303 1317
75283501
SP		 1318static void
1319verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1320{
1321
92406f0c
SP		 1322 for (; caps->matches; caps++)
1323 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP		 1324 pr_crit("CPU%d: missing HWCAP: %s\n",
1325 smp_processor_id(), caps->desc);
1326 cpu_die_early();
1327 }
75283501
SP		 1328}
1329
1330static void
67948af4 1331verify_local_cpu_features(const struct arm64_cpu_capabilities *caps_list)
75283501 1332{
67948af4 1333 const struct arm64_cpu_capabilities *caps = caps_list;
75283501 1334 for (; caps->matches; caps++) {
92406f0c 1335 if (!cpus_have_cap(caps->capability))
75283501
SP		 1336 continue;
1337 /*
1338 * If the new CPU misses an advertised feature, we cannot proceed
1339 * further, park the cpu.
1340 */
67948af4 1341 if (!__this_cpu_has_cap(caps_list, caps->capability)) {
75283501
SP		 1342 pr_crit("CPU%d: missing feature: %s\n",
1343 smp_processor_id(), caps->desc);
1344 cpu_die_early();
1345 }
c0cda3b8
DM		 1346 if (caps->cpu_enable)
1347 caps->cpu_enable(caps);
75283501
SP		 1348 }
1349}
1350
2e0f2478
DM		 1351static void verify_sve_features(void)
1352{
1353 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1354 u64 zcr = read_zcr_features();
1355
1356 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1357 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1358
1359 if (len < safe_len || sve_verify_vq_map()) {
1360 pr_crit("CPU%d: SVE: required vector length(s) missing\n",
1361 smp_processor_id());
1362 cpu_die_early();
1363 }
1364
1365 /* Add checks on other ZCR bits here if necessary */
1366}
1367
1e89baed
SP		 1368/*
1369 * The CPU Errata work arounds are detected and applied at boot time
1370 * and the related information is freed soon after. If the new CPU requires
1371 * an errata not detected at boot, fail this CPU.
1372 */
1373static void verify_local_cpu_errata_workarounds(void)
1374{
1375 const struct arm64_cpu_capabilities *caps = arm64_errata;
1376
1377 for (; caps->matches; caps++) {
1378 if (cpus_have_cap(caps->capability)) {
1379 if (caps->cpu_enable)
1380 caps->cpu_enable(caps);
1381 } else if (caps->matches(caps, SCOPE_LOCAL_CPU)) {
1382 pr_crit("CPU%d: Requires work around for %s, not detected"
1383 " at boot time\n",
1384 smp_processor_id(),
1385 caps->desc ? : "an erratum");
1386 cpu_die_early();
1387 }
1388 }
1389}
1390
1391static void update_cpu_errata_workarounds(void)
1392{
1393 update_cpu_capabilities(arm64_errata, "enabling workaround for");
1394}
1395
1396static void __init enable_errata_workarounds(void)
1397{
1398 enable_cpu_capabilities(arm64_errata);
1399}
1400
dbb4e152
SP		 1401/*
1402 * Run through the enabled system capabilities and enable() it on this CPU.
1403 * The capabilities were decided based on the available CPUs at the boot time.
1404 * Any new CPU should match the system wide status of the capability. If the
1405 * new CPU doesn't have a capability which the system now has enabled, we
1406 * cannot do anything to fix it up and could cause unexpected failures. So
1407 * we park the CPU.
1408 */
c47a1900 1409static void verify_local_cpu_capabilities(void)
dbb4e152 1410{
c47a1900
SP		 1411 verify_local_cpu_errata_workarounds();
1412 verify_local_cpu_features(arm64_features);
1413 verify_local_elf_hwcaps(arm64_elf_hwcaps);
2e0f2478 1414
c47a1900
SP		 1415 if (system_supports_32bit_el0())
1416 verify_local_elf_hwcaps(compat_elf_hwcaps);
2e0f2478
DM		 1417
1418 if (system_supports_sve())
1419 verify_sve_features();
c47a1900 1420}
dbb4e152 1421
c47a1900
SP		 1422void check_local_cpu_capabilities(void)
1423{
1424 /*
1425 * All secondary CPUs should conform to the early CPU features
1426 * in use by the kernel based on boot CPU.
1427 */
13f417f3
SP		 1428 check_early_cpu_features();
1429
dbb4e152 1430 /*
c47a1900
SP		 1431 * If we haven't finalised the system capabilities, this CPU gets
1432 * a chance to update the errata work arounds.
1433 * Otherwise, this CPU should verify that it has all the system
1434 * advertised capabilities.
dbb4e152
SP		 1435 */
1436 if (!sys_caps_initialised)
c47a1900
SP		 1437 update_cpu_errata_workarounds();
1438 else
1439 verify_local_cpu_capabilities();
359b7064
MZ		 1440}
1441
a7c61a34 1442static void __init setup_feature_capabilities(void)
359b7064 1443{
e0f6429d 1444 update_cpu_capabilities(arm64_features, "detected:");
ce8b602c 1445 enable_cpu_capabilities(arm64_features);
359b7064
MZ		 1446}
1447
63a1e1c9
MR		 1448DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1449EXPORT_SYMBOL(arm64_const_caps_ready);
1450
1451static void __init mark_const_caps_ready(void)
1452{
1453 static_branch_enable(&arm64_const_caps_ready);
1454}
1455
8f413758
MZ		 1456extern const struct arm64_cpu_capabilities arm64_errata[];
1457
1458bool this_cpu_has_cap(unsigned int cap)
1459{
1460 return (__this_cpu_has_cap(arm64_features, cap) ||
1461 __this_cpu_has_cap(arm64_errata, cap));
1462}
1463
9cdf8ec4 1464void __init setup_cpu_features(void)
359b7064 1465{
9cdf8ec4 1466 u32 cwg;
9cdf8ec4 1467
dbb4e152
SP		 1468 /* Set the CPU feature capabilies */
1469 setup_feature_capabilities();
8e231852 1470 enable_errata_workarounds();
63a1e1c9 1471 mark_const_caps_ready();
75283501 1472 setup_elf_hwcaps(arm64_elf_hwcaps);
643d703d
SP		 1473
1474 if (system_supports_32bit_el0())
1475 setup_elf_hwcaps(compat_elf_hwcaps);
dbb4e152 1476
2e6f549f
KC		 1477 if (system_uses_ttbr0_pan())
1478 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
1479
2e0f2478
DM		 1480 sve_setup();
1481
dbb4e152
SP		 1482 /* Advertise that we have computed the system capabilities */
1483 set_sys_caps_initialised();
1484
9cdf8ec4
SP		 1485 /*
1486 * Check for sane CTR_EL0.CWG value.
1487 */
1488 cwg = cache_type_cwg();
9cdf8ec4 1489 if (!cwg)
1f85b42a
CM		 1490 pr_warn("No Cache Writeback Granule information, assuming %d\n",
1491 ARCH_DMA_MINALIGN);
359b7064 1492}
70544196
JM		 1493
1494static bool __maybe_unused
92406f0c 1495cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
70544196 1496{
a4023f68 1497 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
70544196 1498}
77c97b4e
SP		 1499
1500/*
1501 * We emulate only the following system register space.
1502 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1503 * See Table C5-6 System instruction encodings for System register accesses,
1504 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1505 */
1506static inline bool __attribute_const__ is_emulated(u32 id)
1507{
1508 return (sys_reg_Op0(id) == 0x3 &&
1509 sys_reg_CRn(id) == 0x0 &&
1510 sys_reg_Op1(id) == 0x0 &&
1511 (sys_reg_CRm(id) == 0 ||
1512 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
1513}
1514
1515/*
1516 * With CRm == 0, reg should be one of :
1517 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1518 */
1519static inline int emulate_id_reg(u32 id, u64 *valp)
1520{
1521 switch (id) {
1522 case SYS_MIDR_EL1:
1523 *valp = read_cpuid_id();
1524 break;
1525 case SYS_MPIDR_EL1:
1526 *valp = SYS_MPIDR_SAFE_VAL;
1527 break;
1528 case SYS_REVIDR_EL1:
1529 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1530 *valp = 0;
1531 break;
1532 default:
1533 return -EINVAL;
1534 }
1535
1536 return 0;
1537}
1538
1539static int emulate_sys_reg(u32 id, u64 *valp)
1540{
1541 struct arm64_ftr_reg *regp;
1542
1543 if (!is_emulated(id))
1544 return -EINVAL;
1545
1546 if (sys_reg_CRm(id) == 0)
1547 return emulate_id_reg(id, valp);
1548
1549 regp = get_arm64_ftr_reg(id);
1550 if (regp)
1551 *valp = arm64_ftr_reg_user_value(regp);
1552 else
1553 /*
1554 * The untracked registers are either IMPLEMENTATION DEFINED
1555 * (e.g, ID_AFR0_EL1) or reserved RAZ.
1556 */
1557 *valp = 0;
1558 return 0;
1559}
1560
1561static int emulate_mrs(struct pt_regs *regs, u32 insn)
1562{
1563 int rc;
1564 u32 sys_reg, dst;
1565 u64 val;
1566
1567 /*
1568 * sys_reg values are defined as used in mrs/msr instruction.
1569 * shift the imm value to get the encoding.
1570 */
1571 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
1572 rc = emulate_sys_reg(sys_reg, &val);
1573 if (!rc) {
1574 dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
521c6461 1575 pt_regs_write_reg(regs, dst, val);
6436beee 1576 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
77c97b4e
SP		 1577 }
1578
1579 return rc;
1580}
1581
1582static struct undef_hook mrs_hook = {
1583 .instr_mask = 0xfff00000,
1584 .instr_val = 0xd5300000,
1585 .pstate_mask = COMPAT_PSR_MODE_MASK,
1586 .pstate_val = PSR_MODE_EL0t,
1587 .fn = emulate_mrs,
1588};
1589
1590static int __init enable_mrs_emulation(void)
1591{
1592 register_undef_hook(&mrs_hook);
1593 return 0;
1594}
1595
c0d8832e 1596core_initcall(enable_mrs_emulation);
68ddbf09 1597
c0cda3b8 1598void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
68ddbf09
JM		 1599{
1600 /* Firmware may have left a deferred SError in this register. */
1601 write_sysreg_s(0, SYS_DISR_EL1);
68ddbf09 1602}
Linux 6.x block layer and io_uring tree(s)