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Linux 4.18-rc4
[linux-2.6-block.git] / arch / arm64 / kernel / cpufeature.c
CommitLineData
359b7064
MZ		 1/*
2 * Contains CPU feature definitions
3 *
4 * Copyright (C) 2015 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
9cdf8ec4 19#define pr_fmt(fmt) "CPU features: " fmt
359b7064 20
3c739b57 21#include <linux/bsearch.h>
2a6dcb2b 22#include <linux/cpumask.h>
3c739b57 23#include <linux/sort.h>
2a6dcb2b 24#include <linux/stop_machine.h>
359b7064 25#include <linux/types.h>
2077be67 26#include <linux/mm.h>
359b7064
MZ		 27#include <asm/cpu.h>
28#include <asm/cpufeature.h>
dbb4e152 29#include <asm/cpu_ops.h>
2e0f2478 30#include <asm/fpsimd.h>
13f417f3 31#include <asm/mmu_context.h>
338d4f49 32#include <asm/processor.h>
cdcf817b 33#include <asm/sysreg.h>
77c97b4e 34#include <asm/traps.h>
d88701be 35#include <asm/virt.h>
359b7064 36
9cdf8ec4
SP		 37unsigned long elf_hwcap __read_mostly;
38EXPORT_SYMBOL_GPL(elf_hwcap);
39
40#ifdef CONFIG_COMPAT
41#define COMPAT_ELF_HWCAP_DEFAULT \
42 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
43 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
44 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
45 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
46 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
47 COMPAT_HWCAP_LPAE)
48unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
49unsigned int compat_elf_hwcap2 __read_mostly;
50#endif
51
52DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
4b65a5db 53EXPORT_SYMBOL(cpu_hwcaps);
9cdf8ec4 54
8f1eec57
DM		 55/*
56 * Flag to indicate if we have computed the system wide
57 * capabilities based on the boot time active CPUs. This
58 * will be used to determine if a new booting CPU should
59 * go through the verification process to make sure that it
60 * supports the system capabilities, without using a hotplug
61 * notifier.
62 */
63static bool sys_caps_initialised;
64
65static inline void set_sys_caps_initialised(void)
66{
67 sys_caps_initialised = true;
68}
69
8effeaaf
MR		 70static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
71{
72 /* file-wide pr_fmt adds "CPU features: " prefix */
73 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
74 return 0;
75}
76
77static struct notifier_block cpu_hwcaps_notifier = {
78 .notifier_call = dump_cpu_hwcaps
79};
80
81static int __init register_cpu_hwcaps_dumper(void)
82{
83 atomic_notifier_chain_register(&panic_notifier_list,
84 &cpu_hwcaps_notifier);
85 return 0;
86}
87__initcall(register_cpu_hwcaps_dumper);
88
efd9e03f
CM		 89DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
90EXPORT_SYMBOL(cpu_hwcap_keys);
91
fe4fbdbc 92#define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
3c739b57 93 { \
4f0a606b 94 .sign = SIGNED, \
fe4fbdbc 95 .visible = VISIBLE, \
3c739b57
SP		 96 .strict = STRICT, \
97 .type = TYPE, \
98 .shift = SHIFT, \
99 .width = WIDTH, \
100 .safe_val = SAFE_VAL, \
101 }
102
0710cfdb 103/* Define a feature with unsigned values */
fe4fbdbc
SP		 104#define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
105 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
4f0a606b 106
0710cfdb 107/* Define a feature with a signed value */
fe4fbdbc
SP		 108#define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
109 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
0710cfdb 110
3c739b57
SP		 111#define ARM64_FTR_END \
112 { \
113 .width = 0, \
114 }
115
70544196
JM		 116/* meta feature for alternatives */
117static bool __maybe_unused
92406f0c
SP		 118cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
119
70544196 120
4aa8a472
SP		 121/*
122 * NOTE: Any changes to the visibility of features should be kept in
123 * sync with the documentation of the CPU feature register ABI.
124 */
5e49d73c 125static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
7206dc93 126 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
3b3b6810 127 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
5bdecb79
SP		 128 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
129 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
130 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
131 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
132 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
fe4fbdbc
SP		 133 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
134 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
135 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
136 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
137 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
3c739b57
SP		 138 ARM64_FTR_END,
139};
140
c8c3798d 141static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
5bdecb79
SP		 142 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
143 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
144 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
145 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
c8c3798d
SP		 146 ARM64_FTR_END,
147};
148
5e49d73c 149static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
179a56f6 150 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
0f15adbb 151 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
7206dc93 152 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
3fab3999
DM		 153 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
154 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
64c02720 155 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
5bdecb79 156 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
fe4fbdbc
SP		 157 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
158 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
3c739b57 159 /* Linux doesn't care about the EL3 */
5bdecb79
SP		 160 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
161 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
162 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
163 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
3c739b57
SP		 164 ARM64_FTR_END,
165};
166
5e49d73c 167static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
5bdecb79
SP		 168 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
169 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
170 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
171 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
3c739b57 172 /* Linux shouldn't care about secure memory */
5bdecb79
SP		 173 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
174 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
175 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
3c739b57
SP		 176 /*
177 * Differing PARange is fine as long as all peripherals and memory are mapped
178 * within the minimum PARange of all CPUs
179 */
fe4fbdbc 180 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
3c739b57
SP		 181 ARM64_FTR_END,
182};
183
5e49d73c 184static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
fe4fbdbc 185 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
5bdecb79
SP		 186 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
187 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
188 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
189 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
190 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
3c739b57
SP		 191 ARM64_FTR_END,
192};
193
5e49d73c 194static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
7206dc93 195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
5bdecb79
SP		 196 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
198 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
199 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
200 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
406e3087
JM		 201 ARM64_FTR_END,
202};
203
5e49d73c 204static const struct arm64_ftr_bits ftr_ctr[] = {
6ae4b6e0
SD		 205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
206 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
207 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
208 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_CWG_SHIFT, 4, 0),
209 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_ERG_SHIFT, 4, 0),
210 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
3c739b57
SP		 211 /*
212 * Linux can handle differing I-cache policies. Userspace JITs will
ee7bc638 213 * make use of *minLine.
155433cb 214 * If we have differing I-cache policies, report it as the weakest - VIPT.
3c739b57 215 */
155433cb 216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */
fe4fbdbc 217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
3c739b57
SP		 218 ARM64_FTR_END,
219};
220
675b0563
AB		 221struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
222 .name = "SYS_CTR_EL0",
223 .ftr_bits = ftr_ctr
224};
225
5e49d73c 226static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
5bdecb79
SP		 227 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */
228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */
fe4fbdbc 229 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
5bdecb79
SP		 230 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */
231 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */
232 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */
233 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */
234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */
3c739b57
SP		 235 ARM64_FTR_END,
236};
237
5e49d73c 238static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
fe4fbdbc
SP		 239 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
240 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
243 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
b20d1ba3
WD		 244 /*
245 * We can instantiate multiple PMU instances with different levels
246 * of support.
fe4fbdbc
SP		 247 */
248 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
3c739b57
SP		 251 ARM64_FTR_END,
252};
253
5e49d73c 254static const struct arm64_ftr_bits ftr_mvfr2[] = {
5bdecb79
SP		 255 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */
256 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */
3c739b57
SP		 257 ARM64_FTR_END,
258};
259
5e49d73c 260static const struct arm64_ftr_bits ftr_dczid[] = {
fe4fbdbc
SP		 261 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
262 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
3c739b57
SP		 263 ARM64_FTR_END,
264};
265
266
5e49d73c 267static const struct arm64_ftr_bits ftr_id_isar5[] = {
5bdecb79
SP		 268 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
269 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
270 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
271 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
272 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
273 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
3c739b57
SP		 274 ARM64_FTR_END,
275};
276
5e49d73c 277static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
5bdecb79 278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */
3c739b57
SP		 279 ARM64_FTR_END,
280};
281
5e49d73c 282static const struct arm64_ftr_bits ftr_id_pfr0[] = {
5bdecb79
SP		 283 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */
284 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */
285 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */
286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */
3c739b57
SP		 287 ARM64_FTR_END,
288};
289
5e49d73c 290static const struct arm64_ftr_bits ftr_id_dfr0[] = {
fe4fbdbc
SP		 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
292 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
297 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
e5343503
SP		 299 ARM64_FTR_END,
300};
301
2e0f2478
DM		 302static const struct arm64_ftr_bits ftr_zcr[] = {
303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
304 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
305 ARM64_FTR_END,
306};
307
3c739b57
SP		 308/*
309 * Common ftr bits for a 32bit register with all hidden, strict
310 * attributes, with 4bit feature fields and a default safe value of
311 * 0. Covers the following 32bit registers:
312 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
313 */
5e49d73c 314static const struct arm64_ftr_bits ftr_generic_32bits[] = {
fe4fbdbc
SP		 315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
317 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
318 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
319 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
3c739b57
SP		 323 ARM64_FTR_END,
324};
325
eab43e88
SP		 326/* Table for a single 32bit feature value */
327static const struct arm64_ftr_bits ftr_single32[] = {
fe4fbdbc 328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
3c739b57
SP		 329 ARM64_FTR_END,
330};
331
eab43e88 332static const struct arm64_ftr_bits ftr_raz[] = {
3c739b57
SP		 333 ARM64_FTR_END,
334};
335
6f2b7eef
AB		 336#define ARM64_FTR_REG(id, table) { \
337 .sys_id = id, \
338 .reg = &(struct arm64_ftr_reg){ \
3c739b57
SP		 339 .name = #id, \
340 .ftr_bits = &((table)[0]), \
6f2b7eef 341 }}
3c739b57 342
6f2b7eef
AB		 343static const struct __ftr_reg_entry {
344 u32 sys_id;
345 struct arm64_ftr_reg *reg;
346} arm64_ftr_regs[] = {
3c739b57
SP		 347
348 /* Op1 = 0, CRn = 0, CRm = 1 */
349 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
350 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
e5343503 351 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
3c739b57
SP		 352 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
353 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
354 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
355 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
356
357 /* Op1 = 0, CRn = 0, CRm = 2 */
358 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
359 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
360 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
361 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
362 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
363 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
364 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
365
366 /* Op1 = 0, CRn = 0, CRm = 3 */
367 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
368 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
369 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
370
371 /* Op1 = 0, CRn = 0, CRm = 4 */
372 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
eab43e88 373 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_raz),
2e0f2478 374 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz),
3c739b57
SP		 375
376 /* Op1 = 0, CRn = 0, CRm = 5 */
377 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
eab43e88 378 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
3c739b57
SP		 379
380 /* Op1 = 0, CRn = 0, CRm = 6 */
381 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
c8c3798d 382 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
3c739b57
SP		 383
384 /* Op1 = 0, CRn = 0, CRm = 7 */
385 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
386 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
406e3087 387 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
3c739b57 388
2e0f2478
DM		 389 /* Op1 = 0, CRn = 1, CRm = 2 */
390 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
391
3c739b57 392 /* Op1 = 3, CRn = 0, CRm = 0 */
675b0563 393 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
3c739b57
SP		 394 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
395
396 /* Op1 = 3, CRn = 14, CRm = 0 */
eab43e88 397 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
3c739b57
SP		 398};
399
400static int search_cmp_ftr_reg(const void *id, const void *regp)
401{
6f2b7eef 402 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
3c739b57
SP		 403}
404
405/*
406 * get_arm64_ftr_reg - Lookup a feature register entry using its
407 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
408 * ascending order of sys_id , we use binary search to find a matching
409 * entry.
410 *
411 * returns - Upon success, matching ftr_reg entry for id.
412 * - NULL on failure. It is upto the caller to decide
413 * the impact of a failure.
414 */
415static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
416{
6f2b7eef
AB		 417 const struct __ftr_reg_entry *ret;
418
419 ret = bsearch((const void *)(unsigned long)sys_id,
3c739b57
SP		 420 arm64_ftr_regs,
421 ARRAY_SIZE(arm64_ftr_regs),
422 sizeof(arm64_ftr_regs[0]),
423 search_cmp_ftr_reg);
6f2b7eef
AB		 424 if (ret)
425 return ret->reg;
426 return NULL;
3c739b57
SP		 427}
428
5e49d73c
AB		 429static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
430 s64 ftr_val)
3c739b57
SP		 431{
432 u64 mask = arm64_ftr_mask(ftrp);
433
434 reg &= ~mask;
435 reg |= (ftr_val << ftrp->shift) & mask;
436 return reg;
437}
438
5e49d73c
AB		 439static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
440 s64 cur)
3c739b57
SP		 441{
442 s64 ret = 0;
443
444 switch (ftrp->type) {
445 case FTR_EXACT:
446 ret = ftrp->safe_val;
447 break;
448 case FTR_LOWER_SAFE:
449 ret = new < cur ? new : cur;
450 break;
451 case FTR_HIGHER_SAFE:
452 ret = new > cur ? new : cur;
453 break;
454 default:
455 BUG();
456 }
457
458 return ret;
459}
460
3c739b57
SP		 461static void __init sort_ftr_regs(void)
462{
6f2b7eef
AB		 463 int i;
464
465 /* Check that the array is sorted so that we can do the binary search */
466 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
467 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
3c739b57
SP		 468}
469
470/*
471 * Initialise the CPU feature register from Boot CPU values.
472 * Also initiliases the strict_mask for the register.
b389d799
MR		 473 * Any bits that are not covered by an arm64_ftr_bits entry are considered
474 * RES0 for the system-wide value, and must strictly match.
3c739b57
SP		 475 */
476static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
477{
478 u64 val = 0;
479 u64 strict_mask = ~0x0ULL;
fe4fbdbc 480 u64 user_mask = 0;
b389d799
MR		 481 u64 valid_mask = 0;
482
5e49d73c 483 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 484 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
485
486 BUG_ON(!reg);
487
488 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
b389d799 489 u64 ftr_mask = arm64_ftr_mask(ftrp);
3c739b57
SP		 490 s64 ftr_new = arm64_ftr_value(ftrp, new);
491
492 val = arm64_ftr_set_value(ftrp, val, ftr_new);
b389d799
MR		 493
494 valid_mask |= ftr_mask;
3c739b57 495 if (!ftrp->strict)
b389d799 496 strict_mask &= ~ftr_mask;
fe4fbdbc
SP		 497 if (ftrp->visible)
498 user_mask |= ftr_mask;
499 else
500 reg->user_val = arm64_ftr_set_value(ftrp,
501 reg->user_val,
502 ftrp->safe_val);
3c739b57 503 }
b389d799
MR		 504
505 val &= valid_mask;
506
3c739b57
SP		 507 reg->sys_val = val;
508 reg->strict_mask = strict_mask;
fe4fbdbc 509 reg->user_mask = user_mask;
3c739b57
SP		 510}
511
1e89baed 512extern const struct arm64_cpu_capabilities arm64_errata[];
fd9d63da 513static void __init setup_boot_cpu_capabilities(void);
1e89baed 514
3c739b57
SP		 515void __init init_cpu_features(struct cpuinfo_arm64 *info)
516{
517 /* Before we start using the tables, make sure it is sorted */
518 sort_ftr_regs();
519
520 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
521 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
522 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
523 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
524 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
525 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
526 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
527 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
528 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
406e3087 529 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
3c739b57
SP		 530 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
531 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
2e0f2478 532 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
a6dc3cd7
SP		 533
534 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
535 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
536 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
537 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
538 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
539 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
540 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
541 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
542 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
543 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
544 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
545 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
546 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
547 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
548 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
549 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
550 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
551 }
552
2e0f2478
DM		 553 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
554 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
555 sve_init_vq_map();
556 }
5e91107b
SP		 557
558 /*
fd9d63da
SP		 559 * Detect and enable early CPU capabilities based on the boot CPU,
560 * after we have initialised the CPU feature infrastructure.
5e91107b 561 */
fd9d63da 562 setup_boot_cpu_capabilities();
3c739b57
SP		 563}
564
3086d391 565static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
3c739b57 566{
5e49d73c 567 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 568
569 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
570 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
571 s64 ftr_new = arm64_ftr_value(ftrp, new);
572
573 if (ftr_cur == ftr_new)
574 continue;
575 /* Find a safe value */
576 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
577 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
578 }
579
580}
581
3086d391 582static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
cdcf817b 583{
3086d391
SP		 584 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
585
586 BUG_ON(!regp);
587 update_cpu_ftr_reg(regp, val);
588 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
589 return 0;
590 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
591 regp->name, boot, cpu, val);
592 return 1;
593}
594
595/*
596 * Update system wide CPU feature registers with the values from a
597 * non-boot CPU. Also performs SANITY checks to make sure that there
598 * aren't any insane variations from that of the boot CPU.
599 */
600void update_cpu_features(int cpu,
601 struct cpuinfo_arm64 *info,
602 struct cpuinfo_arm64 *boot)
603{
604 int taint = 0;
605
606 /*
607 * The kernel can handle differing I-cache policies, but otherwise
608 * caches should look identical. Userspace JITs will make use of
609 * *minLine.
610 */
611 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
612 info->reg_ctr, boot->reg_ctr);
613
614 /*
615 * Userspace may perform DC ZVA instructions. Mismatched block sizes
616 * could result in too much or too little memory being zeroed if a
617 * process is preempted and migrated between CPUs.
618 */
619 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
620 info->reg_dczid, boot->reg_dczid);
621
622 /* If different, timekeeping will be broken (especially with KVM) */
623 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
624 info->reg_cntfrq, boot->reg_cntfrq);
625
626 /*
627 * The kernel uses self-hosted debug features and expects CPUs to
628 * support identical debug features. We presently need CTX_CMPs, WRPs,
629 * and BRPs to be identical.
630 * ID_AA64DFR1 is currently RES0.
631 */
632 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
633 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
634 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
635 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
636 /*
637 * Even in big.LITTLE, processors should be identical instruction-set
638 * wise.
639 */
640 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
641 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
642 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
643 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
644
645 /*
646 * Differing PARange support is fine as long as all peripherals and
647 * memory are mapped within the minimum PARange of all CPUs.
648 * Linux should not care about secure memory.
649 */
650 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
651 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
652 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
653 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
406e3087
JM		 654 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
655 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
3086d391
SP		 656
657 /*
658 * EL3 is not our concern.
659 * ID_AA64PFR1 is currently RES0.
660 */
661 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
662 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
663 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
664 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
665
2e0f2478
DM		 666 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
667 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
668
3086d391 669 /*
a6dc3cd7
SP		 670 * If we have AArch32, we care about 32-bit features for compat.
671 * If the system doesn't support AArch32, don't update them.
3086d391 672 */
46823dd1 673 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
a6dc3cd7
SP		 674 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
675
676 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
3086d391 677 info->reg_id_dfr0, boot->reg_id_dfr0);
a6dc3cd7 678 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
3086d391 679 info->reg_id_isar0, boot->reg_id_isar0);
a6dc3cd7 680 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
3086d391 681 info->reg_id_isar1, boot->reg_id_isar1);
a6dc3cd7 682 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
3086d391 683 info->reg_id_isar2, boot->reg_id_isar2);
a6dc3cd7 684 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
3086d391 685 info->reg_id_isar3, boot->reg_id_isar3);
a6dc3cd7 686 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
3086d391 687 info->reg_id_isar4, boot->reg_id_isar4);
a6dc3cd7 688 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
3086d391
SP		 689 info->reg_id_isar5, boot->reg_id_isar5);
690
a6dc3cd7
SP		 691 /*
692 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
693 * ACTLR formats could differ across CPUs and therefore would have to
694 * be trapped for virtualization anyway.
695 */
696 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
3086d391 697 info->reg_id_mmfr0, boot->reg_id_mmfr0);
a6dc3cd7 698 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
3086d391 699 info->reg_id_mmfr1, boot->reg_id_mmfr1);
a6dc3cd7 700 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
3086d391 701 info->reg_id_mmfr2, boot->reg_id_mmfr2);
a6dc3cd7 702 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
3086d391 703 info->reg_id_mmfr3, boot->reg_id_mmfr3);
a6dc3cd7 704 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
3086d391 705 info->reg_id_pfr0, boot->reg_id_pfr0);
a6dc3cd7 706 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
3086d391 707 info->reg_id_pfr1, boot->reg_id_pfr1);
a6dc3cd7 708 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
3086d391 709 info->reg_mvfr0, boot->reg_mvfr0);
a6dc3cd7 710 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
3086d391 711 info->reg_mvfr1, boot->reg_mvfr1);
a6dc3cd7 712 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
3086d391 713 info->reg_mvfr2, boot->reg_mvfr2);
a6dc3cd7 714 }
3086d391 715
2e0f2478
DM		 716 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
717 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
718 info->reg_zcr, boot->reg_zcr);
719
720 /* Probe vector lengths, unless we already gave up on SVE */
721 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
722 !sys_caps_initialised)
723 sve_update_vq_map();
724 }
725
3086d391
SP		 726 /*
727 * Mismatched CPU features are a recipe for disaster. Don't even
728 * pretend to support them.
729 */
8dd0ee65
WD		 730 if (taint) {
731 pr_warn_once("Unsupported CPU feature variation detected.\n");
732 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
733 }
cdcf817b
SP		 734}
735
46823dd1 736u64 read_sanitised_ftr_reg(u32 id)
b3f15378
SP		 737{
738 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
739
740 /* We shouldn't get a request for an unsupported register */
741 BUG_ON(!regp);
742 return regp->sys_val;
743}
359b7064 744
965861d6
MR		 745#define read_sysreg_case(r) \
746 case r: return read_sysreg_s(r)
747
92406f0c 748/*
46823dd1 749 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
92406f0c
SP		 750 * Read the system register on the current CPU
751 */
46823dd1 752static u64 __read_sysreg_by_encoding(u32 sys_id)
92406f0c
SP		 753{
754 switch (sys_id) {
965861d6
MR		 755 read_sysreg_case(SYS_ID_PFR0_EL1);
756 read_sysreg_case(SYS_ID_PFR1_EL1);
757 read_sysreg_case(SYS_ID_DFR0_EL1);
758 read_sysreg_case(SYS_ID_MMFR0_EL1);
759 read_sysreg_case(SYS_ID_MMFR1_EL1);
760 read_sysreg_case(SYS_ID_MMFR2_EL1);
761 read_sysreg_case(SYS_ID_MMFR3_EL1);
762 read_sysreg_case(SYS_ID_ISAR0_EL1);
763 read_sysreg_case(SYS_ID_ISAR1_EL1);
764 read_sysreg_case(SYS_ID_ISAR2_EL1);
765 read_sysreg_case(SYS_ID_ISAR3_EL1);
766 read_sysreg_case(SYS_ID_ISAR4_EL1);
767 read_sysreg_case(SYS_ID_ISAR5_EL1);
768 read_sysreg_case(SYS_MVFR0_EL1);
769 read_sysreg_case(SYS_MVFR1_EL1);
770 read_sysreg_case(SYS_MVFR2_EL1);
771
772 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
773 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
774 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
775 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
776 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
777 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
778 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
779 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
780 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
781
782 read_sysreg_case(SYS_CNTFRQ_EL0);
783 read_sysreg_case(SYS_CTR_EL0);
784 read_sysreg_case(SYS_DCZID_EL0);
785
92406f0c
SP		 786 default:
787 BUG();
788 return 0;
789 }
790}
791
963fcd40
MZ		 792#include <linux/irqchip/arm-gic-v3.h>
793
18ffa046
JM		 794static bool
795feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
796{
28c5dcb2 797 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
18ffa046
JM		 798
799 return val >= entry->min_field_value;
800}
801
da8d02d1 802static bool
92406f0c 803has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
da8d02d1
SP		 804{
805 u64 val;
94a9e04a 806
92406f0c
SP		 807 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
808 if (scope == SCOPE_SYSTEM)
46823dd1 809 val = read_sanitised_ftr_reg(entry->sys_reg);
92406f0c 810 else
46823dd1 811 val = __read_sysreg_by_encoding(entry->sys_reg);
92406f0c 812
da8d02d1
SP		 813 return feature_matches(val, entry);
814}
338d4f49 815
92406f0c 816static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
963fcd40
MZ		 817{
818 bool has_sre;
819
92406f0c 820 if (!has_cpuid_feature(entry, scope))
963fcd40
MZ		 821 return false;
822
823 has_sre = gic_enable_sre();
824 if (!has_sre)
825 pr_warn_once("%s present but disabled by higher exception level\n",
826 entry->desc);
827
828 return has_sre;
829}
830
92406f0c 831static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
d5370f75
WD		 832{
833 u32 midr = read_cpuid_id();
d5370f75
WD		 834
835 /* Cavium ThunderX pass 1.x and 2.x */
fa5ce3d1
RR		 836 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
837 MIDR_CPU_VAR_REV(0, 0),
838 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
d5370f75
WD		 839}
840
82e0191a
SP		 841static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
842{
46823dd1 843 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
82e0191a
SP		 844
845 return cpuid_feature_extract_signed_field(pfr0,
846 ID_AA64PFR0_FP_SHIFT) < 0;
847}
848
6ae4b6e0
SD		 849static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
850 int __unused)
851{
852 return read_sanitised_ftr_reg(SYS_CTR_EL0) & BIT(CTR_IDC_SHIFT);
853}
854
855static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
856 int __unused)
857{
858 return read_sanitised_ftr_reg(SYS_CTR_EL0) & BIT(CTR_DIC_SHIFT);
859}
860
ea1e3de8
WD		 861#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
862static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
863
864static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
d3aec8a2 865 int scope)
ea1e3de8 866{
be5b2998
SP		 867 /* List of CPUs that are not vulnerable and don't need KPTI */
868 static const struct midr_range kpti_safe_list[] = {
869 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
870 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
71c751f2 871 { /* sentinel */ }
be5b2998 872 };
6dc52b15 873 char const *str = "command line option";
179a56f6 874
6dc52b15
MZ		 875 /*
876 * For reasons that aren't entirely clear, enabling KPTI on Cavium
877 * ThunderX leads to apparent I-cache corruption of kernel text, which
878 * ends as well as you might imagine. Don't even try.
879 */
880 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
881 str = "ARM64_WORKAROUND_CAVIUM_27456";
882 __kpti_forced = -1;
883 }
884
885 /* Forced? */
ea1e3de8 886 if (__kpti_forced) {
6dc52b15
MZ		 887 pr_info_once("kernel page table isolation forced %s by %s\n",
888 __kpti_forced > 0 ? "ON" : "OFF", str);
ea1e3de8
WD		 889 return __kpti_forced > 0;
890 }
891
892 /* Useful for KASLR robustness */
893 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE))
894 return true;
895
0ba2e29c 896 /* Don't force KPTI for CPUs that are not vulnerable */
be5b2998 897 if (is_midr_in_range_list(read_cpuid_id(), kpti_safe_list))
0ba2e29c 898 return false;
0ba2e29c 899
179a56f6 900 /* Defer to CPU feature registers */
d3aec8a2 901 return !has_cpuid_feature(entry, scope);
ea1e3de8
WD		 902}
903
c0cda3b8
DM		 904static void
905kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
f992b4df
WD		 906{
907 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
908 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
909 kpti_remap_fn *remap_fn;
910
911 static bool kpti_applied = false;
912 int cpu = smp_processor_id();
913
914 if (kpti_applied)
c0cda3b8 915 return;
f992b4df
WD		 916
917 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
918
919 cpu_install_idmap();
920 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
921 cpu_uninstall_idmap();
922
923 if (!cpu)
924 kpti_applied = true;
925
c0cda3b8 926 return;
f992b4df
WD		 927}
928
ea1e3de8
WD		 929static int __init parse_kpti(char *str)
930{
931 bool enabled;
932 int ret = strtobool(str, &enabled);
933
934 if (ret)
935 return ret;
936
937 __kpti_forced = enabled ? 1 : -1;
938 return 0;
939}
b5b7dd64 940early_param("kpti", parse_kpti);
ea1e3de8
WD		 941#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
942
05abb595
SP		 943#ifdef CONFIG_ARM64_HW_AFDBM
944static inline void __cpu_enable_hw_dbm(void)
945{
946 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
947
948 write_sysreg(tcr, tcr_el1);
949 isb();
950}
951
ece1397c
SP		 952static bool cpu_has_broken_dbm(void)
953{
954 /* List of CPUs which have broken DBM support. */
955 static const struct midr_range cpus[] = {
956#ifdef CONFIG_ARM64_ERRATUM_1024718
957 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
958#endif
959 {},
960 };
961
962 return is_midr_in_range_list(read_cpuid_id(), cpus);
963}
964
05abb595
SP		 965static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
966{
ece1397c
SP		 967 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
968 !cpu_has_broken_dbm();
05abb595
SP		 969}
970
971static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
972{
973 if (cpu_can_use_dbm(cap))
974 __cpu_enable_hw_dbm();
975}
976
977static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
978 int __unused)
979{
980 static bool detected = false;
981 /*
982 * DBM is a non-conflicting feature. i.e, the kernel can safely
983 * run a mix of CPUs with and without the feature. So, we
984 * unconditionally enable the capability to allow any late CPU
985 * to use the feature. We only enable the control bits on the
986 * CPU, if it actually supports.
987 *
988 * We have to make sure we print the "feature" detection only
989 * when at least one CPU actually uses it. So check if this CPU
990 * can actually use it and print the message exactly once.
991 *
992 * This is safe as all CPUs (including secondary CPUs - due to the
993 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
994 * goes through the "matches" check exactly once. Also if a CPU
995 * matches the criteria, it is guaranteed that the CPU will turn
996 * the DBM on, as the capability is unconditionally enabled.
997 */
998 if (!detected && cpu_can_use_dbm(cap)) {
999 detected = true;
1000 pr_info("detected: Hardware dirty bit management\n");
1001 }
1002
1003 return true;
1004}
1005
1006#endif
1007
12eb3691
WD		 1008#ifdef CONFIG_ARM64_VHE
1009static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1010{
1011 return is_kernel_in_hyp_mode();
1012}
1013
c0cda3b8 1014static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
6d99b689
JM		 1015{
1016 /*
1017 * Copy register values that aren't redirected by hardware.
1018 *
1019 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1020 * this value to tpidr_el2 before we patch the code. Once we've done
1021 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1022 * do anything here.
1023 */
1024 if (!alternatives_applied)
1025 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
6d99b689 1026}
12eb3691 1027#endif
6d99b689 1028
359b7064 1029static const struct arm64_cpu_capabilities arm64_features[] = {
94a9e04a
MZ		 1030 {
1031 .desc = "GIC system register CPU interface",
1032 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
5b4747c5 1033 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
963fcd40 1034 .matches = has_useable_gicv3_cpuif,
da8d02d1
SP		 1035 .sys_reg = SYS_ID_AA64PFR0_EL1,
1036 .field_pos = ID_AA64PFR0_GIC_SHIFT,
ff96f7bc 1037 .sign = FTR_UNSIGNED,
18ffa046 1038 .min_field_value = 1,
94a9e04a 1039 },
338d4f49
JM		 1040#ifdef CONFIG_ARM64_PAN
1041 {
1042 .desc = "Privileged Access Never",
1043 .capability = ARM64_HAS_PAN,
5b4747c5 1044 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
da8d02d1
SP		 1045 .matches = has_cpuid_feature,
1046 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1047 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
ff96f7bc 1048 .sign = FTR_UNSIGNED,
338d4f49 1049 .min_field_value = 1,
c0cda3b8 1050 .cpu_enable = cpu_enable_pan,
338d4f49
JM		 1051 },
1052#endif /* CONFIG_ARM64_PAN */
2e94da13
WD		 1053#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1054 {
1055 .desc = "LSE atomic instructions",
1056 .capability = ARM64_HAS_LSE_ATOMICS,
5b4747c5 1057 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
da8d02d1
SP		 1058 .matches = has_cpuid_feature,
1059 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1060 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
ff96f7bc 1061 .sign = FTR_UNSIGNED,
2e94da13
WD		 1062 .min_field_value = 2,
1063 },
1064#endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
d5370f75
WD		 1065 {
1066 .desc = "Software prefetching using PRFM",
1067 .capability = ARM64_HAS_NO_HW_PREFETCH,
5c137714 1068 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
d5370f75
WD		 1069 .matches = has_no_hw_prefetch,
1070 },
57f4959b
JM		 1071#ifdef CONFIG_ARM64_UAO
1072 {
1073 .desc = "User Access Override",
1074 .capability = ARM64_HAS_UAO,
5b4747c5 1075 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
57f4959b
JM		 1076 .matches = has_cpuid_feature,
1077 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1078 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1079 .min_field_value = 1,
c8b06e3f
JM		 1080 /*
1081 * We rely on stop_machine() calling uao_thread_switch() to set
1082 * UAO immediately after patching.
1083 */
57f4959b
JM		 1084 },
1085#endif /* CONFIG_ARM64_UAO */
70544196
JM		 1086#ifdef CONFIG_ARM64_PAN
1087 {
1088 .capability = ARM64_ALT_PAN_NOT_UAO,
5b4747c5 1089 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
70544196
JM		 1090 .matches = cpufeature_pan_not_uao,
1091 },
1092#endif /* CONFIG_ARM64_PAN */
830dcc9f 1093#ifdef CONFIG_ARM64_VHE
d88701be
MZ		 1094 {
1095 .desc = "Virtualization Host Extensions",
1096 .capability = ARM64_HAS_VIRT_HOST_EXTN,
830dcc9f 1097 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
d88701be 1098 .matches = runs_at_el2,
c0cda3b8 1099 .cpu_enable = cpu_copy_el2regs,
d88701be 1100 },
830dcc9f 1101#endif /* CONFIG_ARM64_VHE */
042446a3
SP		 1102 {
1103 .desc = "32-bit EL0 Support",
1104 .capability = ARM64_HAS_32BIT_EL0,
5b4747c5 1105 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
042446a3
SP		 1106 .matches = has_cpuid_feature,
1107 .sys_reg = SYS_ID_AA64PFR0_EL1,
1108 .sign = FTR_UNSIGNED,
1109 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1110 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1111 },
ea1e3de8
WD		 1112#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1113 {
179a56f6 1114 .desc = "Kernel page table isolation (KPTI)",
ea1e3de8 1115 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
d3aec8a2
SP		 1116 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1117 /*
1118 * The ID feature fields below are used to indicate that
1119 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1120 * more details.
1121 */
1122 .sys_reg = SYS_ID_AA64PFR0_EL1,
1123 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1124 .min_field_value = 1,
ea1e3de8 1125 .matches = unmap_kernel_at_el0,
c0cda3b8 1126 .cpu_enable = kpti_install_ng_mappings,
ea1e3de8
WD		 1127 },
1128#endif
82e0191a
SP		 1129 {
1130 /* FP/SIMD is not implemented */
1131 .capability = ARM64_HAS_NO_FPSIMD,
5b4747c5 1132 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
82e0191a
SP		 1133 .min_field_value = 0,
1134 .matches = has_no_fpsimd,
1135 },
d50e071f
RM		 1136#ifdef CONFIG_ARM64_PMEM
1137 {
1138 .desc = "Data cache clean to Point of Persistence",
1139 .capability = ARM64_HAS_DCPOP,
5b4747c5 1140 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
d50e071f
RM		 1141 .matches = has_cpuid_feature,
1142 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1143 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1144 .min_field_value = 1,
1145 },
1146#endif
43994d82
DM		 1147#ifdef CONFIG_ARM64_SVE
1148 {
1149 .desc = "Scalable Vector Extension",
5b4747c5 1150 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
43994d82 1151 .capability = ARM64_SVE,
43994d82
DM		 1152 .sys_reg = SYS_ID_AA64PFR0_EL1,
1153 .sign = FTR_UNSIGNED,
1154 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1155 .min_field_value = ID_AA64PFR0_SVE,
1156 .matches = has_cpuid_feature,
c0cda3b8 1157 .cpu_enable = sve_kernel_enable,
43994d82
DM		 1158 },
1159#endif /* CONFIG_ARM64_SVE */
64c02720
XX		 1160#ifdef CONFIG_ARM64_RAS_EXTN
1161 {
1162 .desc = "RAS Extension Support",
1163 .capability = ARM64_HAS_RAS_EXTN,
5b4747c5 1164 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
64c02720
XX		 1165 .matches = has_cpuid_feature,
1166 .sys_reg = SYS_ID_AA64PFR0_EL1,
1167 .sign = FTR_UNSIGNED,
1168 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1169 .min_field_value = ID_AA64PFR0_RAS_V1,
c0cda3b8 1170 .cpu_enable = cpu_clear_disr,
64c02720
XX		 1171 },
1172#endif /* CONFIG_ARM64_RAS_EXTN */
6ae4b6e0
SD		 1173 {
1174 .desc = "Data cache clean to the PoU not required for I/D coherence",
1175 .capability = ARM64_HAS_CACHE_IDC,
5b4747c5 1176 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
6ae4b6e0
SD		 1177 .matches = has_cache_idc,
1178 },
1179 {
1180 .desc = "Instruction cache invalidation not required for I/D coherence",
1181 .capability = ARM64_HAS_CACHE_DIC,
5b4747c5 1182 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
6ae4b6e0
SD		 1183 .matches = has_cache_dic,
1184 },
05abb595
SP		 1185#ifdef CONFIG_ARM64_HW_AFDBM
1186 {
1187 /*
1188 * Since we turn this on always, we don't want the user to
1189 * think that the feature is available when it may not be.
1190 * So hide the description.
1191 *
1192 * .desc = "Hardware pagetable Dirty Bit Management",
1193 *
1194 */
1195 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1196 .capability = ARM64_HW_DBM,
1197 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1198 .sign = FTR_UNSIGNED,
1199 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1200 .min_field_value = 2,
1201 .matches = has_hw_dbm,
1202 .cpu_enable = cpu_enable_hw_dbm,
1203 },
1204#endif
359b7064
MZ		 1205 {},
1206};
1207
143ba05d 1208#define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
37b01d53
SP		 1209 { \
1210 .desc = #cap, \
5b4747c5 1211 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
37b01d53
SP		 1212 .matches = has_cpuid_feature, \
1213 .sys_reg = reg, \
1214 .field_pos = field, \
ff96f7bc 1215 .sign = s, \
37b01d53 1216 .min_field_value = min_value, \
143ba05d 1217 .hwcap_type = cap_type, \
37b01d53
SP		 1218 .hwcap = cap, \
1219 }
1220
f3efb675 1221static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
ff96f7bc
SP		 1222 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
1223 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
1224 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
1225 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
f5e035f8 1226 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512),
ff96f7bc
SP		 1227 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
1228 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
f92f5ce0 1229 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM),
f5e035f8
SP		 1230 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3),
1231 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3),
1232 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4),
1233 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP),
3b3b6810 1234 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM),
7206dc93 1235 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FLAGM),
ff96f7bc 1236 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
bf500618 1237 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
ff96f7bc 1238 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
bf500618 1239 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
7206dc93 1240 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_DIT),
7aac405e 1241 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),
c8c3798d 1242 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
cb567e79 1243 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
c651aae5 1244 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
7206dc93
SP		 1245 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ILRCPC),
1246 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_USCAT),
43994d82
DM		 1247#ifdef CONFIG_ARM64_SVE
1248 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE),
1249#endif
75283501
SP		 1250 {},
1251};
1252
1253static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
37b01d53 1254#ifdef CONFIG_COMPAT
ff96f7bc
SP		 1255 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1256 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1257 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1258 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1259 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
37b01d53
SP		 1260#endif
1261 {},
1262};
1263
f3efb675 1264static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 1265{
1266 switch (cap->hwcap_type) {
1267 case CAP_HWCAP:
1268 elf_hwcap |= cap->hwcap;
1269 break;
1270#ifdef CONFIG_COMPAT
1271 case CAP_COMPAT_HWCAP:
1272 compat_elf_hwcap |= (u32)cap->hwcap;
1273 break;
1274 case CAP_COMPAT_HWCAP2:
1275 compat_elf_hwcap2 |= (u32)cap->hwcap;
1276 break;
1277#endif
1278 default:
1279 WARN_ON(1);
1280 break;
1281 }
1282}
1283
1284/* Check if we have a particular HWCAP enabled */
f3efb675 1285static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 1286{
1287 bool rc;
1288
1289 switch (cap->hwcap_type) {
1290 case CAP_HWCAP:
1291 rc = (elf_hwcap & cap->hwcap) != 0;
1292 break;
1293#ifdef CONFIG_COMPAT
1294 case CAP_COMPAT_HWCAP:
1295 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1296 break;
1297 case CAP_COMPAT_HWCAP2:
1298 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1299 break;
1300#endif
1301 default:
1302 WARN_ON(1);
1303 rc = false;
1304 }
1305
1306 return rc;
1307}
1308
75283501 1309static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
37b01d53 1310{
77c97b4e
SP		 1311 /* We support emulation of accesses to CPU ID feature registers */
1312 elf_hwcap |= HWCAP_CPUID;
75283501 1313 for (; hwcaps->matches; hwcaps++)
143ba05d 1314 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
75283501 1315 cap_set_elf_hwcap(hwcaps);
37b01d53
SP		 1316}
1317
67948af4
SP		 1318/*
1319 * Check if the current CPU has a given feature capability.
1320 * Should be called from non-preemptible context.
1321 */
1322static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array,
1323 unsigned int cap)
1324{
1325 const struct arm64_cpu_capabilities *caps;
1326
1327 if (WARN_ON(preemptible()))
1328 return false;
1329
edf298cf 1330 for (caps = cap_array; caps->matches; caps++)
ba7d9233
SP		 1331 if (caps->capability == cap)
1332 return caps->matches(caps, SCOPE_LOCAL_CPU);
1333
67948af4
SP		 1334 return false;
1335}
1336
ed478b3f
SP		 1337static void __update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1338 u16 scope_mask, const char *info)
359b7064 1339{
cce360b5 1340 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
75283501 1341 for (; caps->matches; caps++) {
cce360b5
SP		 1342 if (!(caps->type & scope_mask) ||
1343 !caps->matches(caps, cpucap_default_scope(caps)))
359b7064
MZ		 1344 continue;
1345
75283501
SP		 1346 if (!cpus_have_cap(caps->capability) && caps->desc)
1347 pr_info("%s %s\n", info, caps->desc);
1348 cpus_set_cap(caps->capability);
359b7064 1349 }
ce8b602c
SP		 1350}
1351
ed478b3f
SP		 1352static void update_cpu_capabilities(u16 scope_mask)
1353{
1354 __update_cpu_capabilities(arm64_features, scope_mask, "detected:");
1355 __update_cpu_capabilities(arm64_errata, scope_mask,
1356 "enabling workaround for");
1357}
1358
c0cda3b8
DM		 1359static int __enable_cpu_capability(void *arg)
1360{
1361 const struct arm64_cpu_capabilities *cap = arg;
1362
1363 cap->cpu_enable(cap);
1364 return 0;
1365}
1366
ce8b602c 1367/*
dbb4e152
SP		 1368 * Run through the enabled capabilities and enable() it on all active
1369 * CPUs
ce8b602c 1370 */
1e89baed 1371static void __init
ed478b3f
SP		 1372__enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1373 u16 scope_mask)
ce8b602c 1374{
cce360b5 1375 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
63a1e1c9
MR		 1376 for (; caps->matches; caps++) {
1377 unsigned int num = caps->capability;
1378
cce360b5 1379 if (!(caps->type & scope_mask) || !cpus_have_cap(num))
63a1e1c9
MR		 1380 continue;
1381
1382 /* Ensure cpus_have_const_cap(num) works */
1383 static_branch_enable(&cpu_hwcap_keys[num]);
1384
c0cda3b8 1385 if (caps->cpu_enable) {
2a6dcb2b 1386 /*
fd9d63da
SP		 1387 * Capabilities with SCOPE_BOOT_CPU scope are finalised
1388 * before any secondary CPU boots. Thus, each secondary
1389 * will enable the capability as appropriate via
1390 * check_local_cpu_capabilities(). The only exception is
1391 * the boot CPU, for which the capability must be
1392 * enabled here. This approach avoids costly
1393 * stop_machine() calls for this case.
1394 *
1395 * Otherwise, use stop_machine() as it schedules the
1396 * work allowing us to modify PSTATE, instead of
1397 * on_each_cpu() which uses an IPI, giving us a PSTATE
1398 * that disappears when we return.
2a6dcb2b 1399 */
fd9d63da
SP		 1400 if (scope_mask & SCOPE_BOOT_CPU)
1401 caps->cpu_enable(caps);
1402 else
1403 stop_machine(__enable_cpu_capability,
1404 (void *)caps, cpu_online_mask);
63a1e1c9
MR		 1405 }
1406 }
dbb4e152
SP		 1407}
1408
ed478b3f
SP		 1409static void __init enable_cpu_capabilities(u16 scope_mask)
1410{
1411 __enable_cpu_capabilities(arm64_features, scope_mask);
1412 __enable_cpu_capabilities(arm64_errata, scope_mask);
1413}
1414
eaac4d83
SP		 1415/*
1416 * Run through the list of capabilities to check for conflicts.
1417 * If the system has already detected a capability, take necessary
1418 * action on this CPU.
1419 *
1420 * Returns "false" on conflicts.
1421 */
1422static bool
ba7d9233 1423__verify_local_cpu_caps(const struct arm64_cpu_capabilities *caps,
cce360b5 1424 u16 scope_mask)
eaac4d83
SP		 1425{
1426 bool cpu_has_cap, system_has_cap;
eaac4d83 1427
cce360b5
SP		 1428 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1429
ba7d9233 1430 for (; caps->matches; caps++) {
cce360b5
SP		 1431 if (!(caps->type & scope_mask))
1432 continue;
1433
ba7d9233 1434 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
eaac4d83
SP		 1435 system_has_cap = cpus_have_cap(caps->capability);
1436
1437 if (system_has_cap) {
1438 /*
1439 * Check if the new CPU misses an advertised feature,
1440 * which is not safe to miss.
1441 */
1442 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1443 break;
1444 /*
1445 * We have to issue cpu_enable() irrespective of
1446 * whether the CPU has it or not, as it is enabeld
1447 * system wide. It is upto the call back to take
1448 * appropriate action on this CPU.
1449 */
1450 if (caps->cpu_enable)
1451 caps->cpu_enable(caps);
1452 } else {
1453 /*
1454 * Check if the CPU has this capability if it isn't
1455 * safe to have when the system doesn't.
1456 */
1457 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1458 break;
1459 }
1460 }
1461
1462 if (caps->matches) {
1463 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1464 smp_processor_id(), caps->capability,
1465 caps->desc, system_has_cap, cpu_has_cap);
1466 return false;
1467 }
1468
1469 return true;
1470}
1471
ed478b3f
SP		 1472static bool verify_local_cpu_caps(u16 scope_mask)
1473{
1474 return __verify_local_cpu_caps(arm64_errata, scope_mask) &&
1475 __verify_local_cpu_caps(arm64_features, scope_mask);
1476}
1477
dbb4e152 1478/*
13f417f3
SP		 1479 * Check for CPU features that are used in early boot
1480 * based on the Boot CPU value.
dbb4e152 1481 */
13f417f3 1482static void check_early_cpu_features(void)
dbb4e152 1483{
13f417f3 1484 verify_cpu_asid_bits();
fd9d63da
SP		 1485 /*
1486 * Early features are used by the kernel already. If there
1487 * is a conflict, we cannot proceed further.
1488 */
1489 if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1490 cpu_panic_kernel();
dbb4e152 1491}
1c076303 1492
75283501
SP		 1493static void
1494verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1495{
1496
92406f0c
SP		 1497 for (; caps->matches; caps++)
1498 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP		 1499 pr_crit("CPU%d: missing HWCAP: %s\n",
1500 smp_processor_id(), caps->desc);
1501 cpu_die_early();
1502 }
75283501
SP		 1503}
1504
2e0f2478
DM		 1505static void verify_sve_features(void)
1506{
1507 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1508 u64 zcr = read_zcr_features();
1509
1510 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1511 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1512
1513 if (len < safe_len || sve_verify_vq_map()) {
1514 pr_crit("CPU%d: SVE: required vector length(s) missing\n",
1515 smp_processor_id());
1516 cpu_die_early();
1517 }
1518
1519 /* Add checks on other ZCR bits here if necessary */
1520}
1521
1e89baed 1522
dbb4e152
SP		 1523/*
1524 * Run through the enabled system capabilities and enable() it on this CPU.
1525 * The capabilities were decided based on the available CPUs at the boot time.
1526 * Any new CPU should match the system wide status of the capability. If the
1527 * new CPU doesn't have a capability which the system now has enabled, we
1528 * cannot do anything to fix it up and could cause unexpected failures. So
1529 * we park the CPU.
1530 */
c47a1900 1531static void verify_local_cpu_capabilities(void)
dbb4e152 1532{
fd9d63da
SP		 1533 /*
1534 * The capabilities with SCOPE_BOOT_CPU are checked from
1535 * check_early_cpu_features(), as they need to be verified
1536 * on all secondary CPUs.
1537 */
1538 if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
600b9c91 1539 cpu_die_early();
ed478b3f 1540
c47a1900 1541 verify_local_elf_hwcaps(arm64_elf_hwcaps);
2e0f2478 1542
c47a1900
SP		 1543 if (system_supports_32bit_el0())
1544 verify_local_elf_hwcaps(compat_elf_hwcaps);
2e0f2478
DM		 1545
1546 if (system_supports_sve())
1547 verify_sve_features();
c47a1900 1548}
dbb4e152 1549
c47a1900
SP		 1550void check_local_cpu_capabilities(void)
1551{
1552 /*
1553 * All secondary CPUs should conform to the early CPU features
1554 * in use by the kernel based on boot CPU.
1555 */
13f417f3
SP		 1556 check_early_cpu_features();
1557
dbb4e152 1558 /*
c47a1900 1559 * If we haven't finalised the system capabilities, this CPU gets
fbd890b9 1560 * a chance to update the errata work arounds and local features.
c47a1900
SP		 1561 * Otherwise, this CPU should verify that it has all the system
1562 * advertised capabilities.
dbb4e152 1563 */
ed478b3f
SP		 1564 if (!sys_caps_initialised)
1565 update_cpu_capabilities(SCOPE_LOCAL_CPU);
1566 else
c47a1900 1567 verify_local_cpu_capabilities();
359b7064
MZ		 1568}
1569
fd9d63da
SP		 1570static void __init setup_boot_cpu_capabilities(void)
1571{
1572 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
1573 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
1574 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
1575 enable_cpu_capabilities(SCOPE_BOOT_CPU);
1576}
1577
63a1e1c9
MR		 1578DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1579EXPORT_SYMBOL(arm64_const_caps_ready);
1580
1581static void __init mark_const_caps_ready(void)
1582{
1583 static_branch_enable(&arm64_const_caps_ready);
1584}
1585
8f413758
MZ		 1586extern const struct arm64_cpu_capabilities arm64_errata[];
1587
1588bool this_cpu_has_cap(unsigned int cap)
1589{
1590 return (__this_cpu_has_cap(arm64_features, cap) ||
1591 __this_cpu_has_cap(arm64_errata, cap));
1592}
1593
ed478b3f
SP		 1594static void __init setup_system_capabilities(void)
1595{
1596 /*
1597 * We have finalised the system-wide safe feature
1598 * registers, finalise the capabilities that depend
fd9d63da
SP		 1599 * on it. Also enable all the available capabilities,
1600 * that are not enabled already.
ed478b3f
SP		 1601 */
1602 update_cpu_capabilities(SCOPE_SYSTEM);
fd9d63da 1603 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
ed478b3f
SP		 1604}
1605
9cdf8ec4 1606void __init setup_cpu_features(void)
359b7064 1607{
9cdf8ec4 1608 u32 cwg;
9cdf8ec4 1609
ed478b3f 1610 setup_system_capabilities();
63a1e1c9 1611 mark_const_caps_ready();
75283501 1612 setup_elf_hwcaps(arm64_elf_hwcaps);
643d703d
SP		 1613
1614 if (system_supports_32bit_el0())
1615 setup_elf_hwcaps(compat_elf_hwcaps);
dbb4e152 1616
2e6f549f
KC		 1617 if (system_uses_ttbr0_pan())
1618 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
1619
2e0f2478 1620 sve_setup();
94b07c1f 1621 minsigstksz_setup();
2e0f2478 1622
dbb4e152
SP		 1623 /* Advertise that we have computed the system capabilities */
1624 set_sys_caps_initialised();
1625
9cdf8ec4
SP		 1626 /*
1627 * Check for sane CTR_EL0.CWG value.
1628 */
1629 cwg = cache_type_cwg();
9cdf8ec4 1630 if (!cwg)
ebc7e21e
CM		 1631 pr_warn("No Cache Writeback Granule information, assuming %d\n",
1632 ARCH_DMA_MINALIGN);
359b7064 1633}
70544196
JM		 1634
1635static bool __maybe_unused
92406f0c 1636cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
70544196 1637{
a4023f68 1638 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
70544196 1639}
77c97b4e
SP		 1640
1641/*
1642 * We emulate only the following system register space.
1643 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1644 * See Table C5-6 System instruction encodings for System register accesses,
1645 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1646 */
1647static inline bool __attribute_const__ is_emulated(u32 id)
1648{
1649 return (sys_reg_Op0(id) == 0x3 &&
1650 sys_reg_CRn(id) == 0x0 &&
1651 sys_reg_Op1(id) == 0x0 &&
1652 (sys_reg_CRm(id) == 0 ||
1653 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
1654}
1655
1656/*
1657 * With CRm == 0, reg should be one of :
1658 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1659 */
1660static inline int emulate_id_reg(u32 id, u64 *valp)
1661{
1662 switch (id) {
1663 case SYS_MIDR_EL1:
1664 *valp = read_cpuid_id();
1665 break;
1666 case SYS_MPIDR_EL1:
1667 *valp = SYS_MPIDR_SAFE_VAL;
1668 break;
1669 case SYS_REVIDR_EL1:
1670 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1671 *valp = 0;
1672 break;
1673 default:
1674 return -EINVAL;
1675 }
1676
1677 return 0;
1678}
1679
1680static int emulate_sys_reg(u32 id, u64 *valp)
1681{
1682 struct arm64_ftr_reg *regp;
1683
1684 if (!is_emulated(id))
1685 return -EINVAL;
1686
1687 if (sys_reg_CRm(id) == 0)
1688 return emulate_id_reg(id, valp);
1689
1690 regp = get_arm64_ftr_reg(id);
1691 if (regp)
1692 *valp = arm64_ftr_reg_user_value(regp);
1693 else
1694 /*
1695 * The untracked registers are either IMPLEMENTATION DEFINED
1696 * (e.g, ID_AFR0_EL1) or reserved RAZ.
1697 */
1698 *valp = 0;
1699 return 0;
1700}
1701
1702static int emulate_mrs(struct pt_regs *regs, u32 insn)
1703{
1704 int rc;
1705 u32 sys_reg, dst;
1706 u64 val;
1707
1708 /*
1709 * sys_reg values are defined as used in mrs/msr instruction.
1710 * shift the imm value to get the encoding.
1711 */
1712 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
1713 rc = emulate_sys_reg(sys_reg, &val);
1714 if (!rc) {
1715 dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
521c6461 1716 pt_regs_write_reg(regs, dst, val);
6436beee 1717 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
77c97b4e
SP		 1718 }
1719
1720 return rc;
1721}
1722
1723static struct undef_hook mrs_hook = {
1724 .instr_mask = 0xfff00000,
1725 .instr_val = 0xd5300000,
1726 .pstate_mask = COMPAT_PSR_MODE_MASK,
1727 .pstate_val = PSR_MODE_EL0t,
1728 .fn = emulate_mrs,
1729};
1730
1731static int __init enable_mrs_emulation(void)
1732{
1733 register_undef_hook(&mrs_hook);
1734 return 0;
1735}
1736
c0d8832e 1737core_initcall(enable_mrs_emulation);
68ddbf09 1738
c0cda3b8 1739void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
68ddbf09
JM		 1740{
1741 /* Firmware may have left a deferred SError in this register. */
1742 write_sysreg_s(0, SYS_DISR_EL1);
68ddbf09 1743}
Linux 6.x block layer and io_uring tree(s)