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Linux 6.12-rc1
[linux-block.git] / arch / arm64 / kernel / cpu_errata.c
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caab277b 1// SPDX-License-Identifier: GPL-2.0-only
e116a375
AP		 2/*
3 * Contains CPU specific errata definitions
4 *
5 * Copyright (C) 2014 ARM Ltd.
e116a375
AP		 6 */
7
94a5d879 8#include <linux/arm-smccc.h>
e116a375 9#include <linux/types.h>
a111b7c0 10#include <linux/cpu.h>
e116a375
AP		 11#include <asm/cpu.h>
12#include <asm/cputype.h>
13#include <asm/cpufeature.h>
4db61fef 14#include <asm/kvm_asm.h>
93916beb 15#include <asm/smp_plat.h>
e116a375 16
301bcfac 17static bool __maybe_unused
92406f0c 18is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
301bcfac 19{
e8002e02
AB		 20 const struct arm64_midr_revidr *fix;
21 u32 midr = read_cpuid_id(), revidr;
22
92406f0c 23 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
1df31050 24 if (!is_midr_in_range(midr, &entry->midr_range))
e8002e02
AB		 25 return false;
26
27 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
28 revidr = read_cpuid(REVIDR_EL1);
29 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
30 if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
31 return false;
32
33 return true;
301bcfac
AP		 34}
35
be5b2998
SP		 36static bool __maybe_unused
37is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
38 int scope)
301bcfac 39{
92406f0c 40 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
be5b2998 41 return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
301bcfac
AP		 42}
43
bb487118
SB		 44static bool __maybe_unused
45is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
46{
47 u32 model;
48
49 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
50
51 model = read_cpuid_id();
52 model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
53 MIDR_ARCHITECTURE_MASK;
54
1df31050 55 return model == entry->midr_range.model;
bb487118
SB		 56}
57
116c81f4 58static bool
314d53d2
SP		 59has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
60 int scope)
116c81f4 61{
1602df02
SP		 62 u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
63 u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask;
64 u64 ctr_raw, ctr_real;
314d53d2 65
116c81f4 66 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
1602df02
SP		 67
68 /*
69 * We want to make sure that all the CPUs in the system expose
70 * a consistent CTR_EL0 to make sure that applications behaves
71 * correctly with migration.
72 *
73 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 :
74 *
75 * 1) It is safe if the system doesn't support IDC, as CPU anyway
76 * reports IDC = 0, consistent with the rest.
77 *
78 * 2) If the system has IDC, it is still safe as we trap CTR_EL0
79 * access on this CPU via the ARM64_HAS_CACHE_IDC capability.
80 *
81 * So, we need to make sure either the raw CTR_EL0 or the effective
82 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot.
83 */
84 ctr_raw = read_cpuid_cachetype() & mask;
85 ctr_real = read_cpuid_effective_cachetype() & mask;
86
87 return (ctr_real != sys) && (ctr_raw != sys);
116c81f4
SP		 88}
89
c0cda3b8 90static void
05460849 91cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap)
116c81f4 92{
4afe8e79 93 u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
05460849 94 bool enable_uct_trap = false;
4afe8e79
SP		 95
96 /* Trap CTR_EL0 access on this CPU, only if it has a mismatch */
97 if ((read_cpuid_cachetype() & mask) !=
98 (arm64_ftr_reg_ctrel0.sys_val & mask))
05460849
JM		 99 enable_uct_trap = true;
100
101 /* ... or if the system is affected by an erratum */
102 if (cap->capability == ARM64_WORKAROUND_1542419)
103 enable_uct_trap = true;
104
105 if (enable_uct_trap)
4afe8e79 106 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
116c81f4
SP		 107}
108
969f5ea6 109#ifdef CONFIG_ARM64_ERRATUM_1463225
969f5ea6
WD		 110static bool
111has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
112 int scope)
113{
a9e821b8 114 return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode();
969f5ea6
WD		 115}
116#endif
117
b8925ee2
WD		 118static void __maybe_unused
119cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
120{
121 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
122}
123
5e7951ce
SP		 124#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
125 .matches = is_affected_midr_range, \
1df31050 126 .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
5e7951ce
SP		 127
128#define CAP_MIDR_ALL_VERSIONS(model) \
129 .matches = is_affected_midr_range, \
1df31050 130 .midr_range = MIDR_ALL_VERSIONS(model)
06f1494f 131
e8002e02
AB		 132#define MIDR_FIXED(rev, revidr_mask) \
133 .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
134
5e7951ce
SP		 135#define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
136 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
137 CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
138
be5b2998
SP		 139#define CAP_MIDR_RANGE_LIST(list) \
140 .matches = is_affected_midr_range_list, \
141 .midr_range_list = list
142
5e7951ce
SP		 143/* Errata affecting a range of revisions of given model variant */
144#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
145 ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
146
147/* Errata affecting a single variant/revision of a model */
148#define ERRATA_MIDR_REV(model, var, rev) \
149 ERRATA_MIDR_RANGE(model, var, rev, var, rev)
150
151/* Errata affecting all variants/revisions of a given a model */
152#define ERRATA_MIDR_ALL_VERSIONS(model) \
153 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
154 CAP_MIDR_ALL_VERSIONS(model)
155
be5b2998
SP		 156/* Errata affecting a list of midr ranges, with same work around */
157#define ERRATA_MIDR_RANGE_LIST(midr_list) \
158 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
159 CAP_MIDR_RANGE_LIST(midr_list)
160
93916beb
MZ		 161static const __maybe_unused struct midr_range tx2_family_cpus[] = {
162 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
163 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
164 {},
165};
166
167static bool __maybe_unused
168needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,
169 int scope)
170{
171 int i;
172
173 if (!is_affected_midr_range_list(entry, scope) ||
174 !is_hyp_mode_available())
175 return false;
176
177 for_each_possible_cpu(i) {
178 if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0)
179 return true;
180 }
181
182 return false;
183}
184
05460849
JM		 185static bool __maybe_unused
186has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
187 int scope)
188{
189 u32 midr = read_cpuid_id();
5b345e39 190 bool has_dic = read_cpuid_cachetype() & BIT(CTR_EL0_DIC_SHIFT);
05460849
JM		 191 const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
192
193 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
194 return is_midr_in_range(midr, &range) && has_dic;
195}
8892b718 196
ce8c80c5 197#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
36c602dc 198static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
ce8c80c5 199#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
36c602dc
BA		 200 {
201 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)
202 },
203 {
204 .midr_range.model = MIDR_QCOM_KRYO,
205 .matches = is_kryo_midr,
206 },
ce8c80c5
CM		 207#endif
208#ifdef CONFIG_ARM64_ERRATUM_1286807
36c602dc
BA		 209 {
210 ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
5e1e0874
ZY		 211 },
212 {
51f559d6
S		 213 /* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */
214 ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),
36c602dc 215 },
39fdb65f 216#endif
171df580
JM		 217#ifdef CONFIG_ARM64_ERRATUM_2441007
218 {
219 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
220 },
221#endif
39fdb65f
JM		 222#ifdef CONFIG_ARM64_ERRATUM_2441009
223 {
224 /* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */
225 ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),
226 },
ce8c80c5
CM		 227#endif
228 {},
229};
ce8c80c5
CM		 230#endif
231
24a147bc 232#ifdef CONFIG_CAVIUM_ERRATUM_23154
710c8d6c 233static const struct midr_range cavium_erratum_23154_cpus[] = {
24a147bc
LC		 234 MIDR_ALL_VERSIONS(MIDR_THUNDERX),
235 MIDR_ALL_VERSIONS(MIDR_THUNDERX_81XX),
236 MIDR_ALL_VERSIONS(MIDR_THUNDERX_83XX),
237 MIDR_ALL_VERSIONS(MIDR_OCTX2_98XX),
238 MIDR_ALL_VERSIONS(MIDR_OCTX2_96XX),
239 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XX),
240 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXN),
241 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXMM),
242 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXO),
f90205b9 243 {},
24a147bc
LC		 244};
245#endif
246
f58cdf7e 247#ifdef CONFIG_CAVIUM_ERRATUM_27456
b89d82ef 248const struct midr_range cavium_erratum_27456_cpus[] = {
f58cdf7e
SP		 249 /* Cavium ThunderX, T88 pass 1.x - 2.1 */
250 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1),
251 /* Cavium ThunderX, T81 pass 1.0 */
252 MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
253 {},
254};
255#endif
256
257#ifdef CONFIG_CAVIUM_ERRATUM_30115
258static const struct midr_range cavium_erratum_30115_cpus[] = {
259 /* Cavium ThunderX, T88 pass 1.x - 2.2 */
260 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2),
261 /* Cavium ThunderX, T81 pass 1.0 - 1.2 */
262 MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
263 /* Cavium ThunderX, T83 pass 1.0 */
264 MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
265 {},
266};
267#endif
268
a3dcea2c
SP		 269#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
270static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {
271 {
272 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
273 },
274 {
275 .midr_range.model = MIDR_QCOM_KRYO,
276 .matches = is_kryo_midr,
277 },
278 {},
279};
280#endif
281
c9460dcb
SP		 282#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
283static const struct midr_range workaround_clean_cache[] = {
c0a01b84
AP		 284#if defined(CONFIG_ARM64_ERRATUM_826319) || \
285 defined(CONFIG_ARM64_ERRATUM_827319) || \
286 defined(CONFIG_ARM64_ERRATUM_824069)
c9460dcb
SP		 287 /* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */
288 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
289#endif
290#ifdef CONFIG_ARM64_ERRATUM_819472
291 /* Cortex-A53 r0p[01] : ARM errata 819472 */
292 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
c0a01b84 293#endif
c9460dcb
SP		 294 {},
295};
296#endif
297
a5325089
MZ		 298#ifdef CONFIG_ARM64_ERRATUM_1418040
299/*
300 * - 1188873 affects r0p0 to r2p0
301 * - 1418040 affects r0p0 to r3p1
302 */
303static const struct midr_range erratum_1418040_list[] = {
304 /* Cortex-A76 r0p0 to r3p1 */
305 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
306 /* Neoverse-N1 r0p0 to r3p1 */
307 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),
a9e821b8
SPR		 308 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
309 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
6989303a
MZ		 310 {},
311};
312#endif
313
bfc97f9f
DB		 314#ifdef CONFIG_ARM64_ERRATUM_845719
315static const struct midr_range erratum_845719_list[] = {
316 /* Cortex-A53 r0p[01234] */
317 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
318 /* Brahma-B53 r0p[0] */
319 MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
23c21641
KD		 320 /* Kryo2XX Silver rAp4 */
321 MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4),
bfc97f9f
DB		 322 {},
323};
324#endif
325
1cf45b8f
FF		 326#ifdef CONFIG_ARM64_ERRATUM_843419
327static const struct arm64_cpu_capabilities erratum_843419_list[] = {
328 {
329 /* Cortex-A53 r0p[01234] */
330 .matches = is_affected_midr_range,
331 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
332 MIDR_FIXED(0x4, BIT(8)),
333 },
334 {
335 /* Brahma-B53 r0p[0] */
336 .matches = is_affected_midr_range,
337 ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
338 },
339 {},
340};
341#endif
342
02ab1f50
AS		 343#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
344static const struct midr_range erratum_speculative_at_list[] = {
e85d68fa
SP		 345#ifdef CONFIG_ARM64_ERRATUM_1165522
346 /* Cortex A76 r0p0 to r2p0 */
347 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
275fa0ea 348#endif
02ab1f50
AS		 349#ifdef CONFIG_ARM64_ERRATUM_1319367
350 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
351 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
352#endif
275fa0ea
SP		 353#ifdef CONFIG_ARM64_ERRATUM_1530923
354 /* Cortex A55 r0p0 to r2p0 */
355 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
9b23d95c
SPR		 356 /* Kryo4xx Silver (rdpe => r1p0) */
357 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
e85d68fa
SP		 358#endif
359 {},
360};
361#endif
362
a9e821b8
SPR		 363#ifdef CONFIG_ARM64_ERRATUM_1463225
364static const struct midr_range erratum_1463225[] = {
365 /* Cortex-A76 r0p0 - r3p1 */
366 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
367 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
368 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
09c717c9 369 {},
a9e821b8
SPR		 370};
371#endif
372
b9d216fc
SP		 373#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
374static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
375#ifdef CONFIG_ARM64_ERRATUM_2139208
376 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
fb091ff3 377 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
b9d216fc
SP		 378#endif
379#ifdef CONFIG_ARM64_ERRATUM_2119858
380 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
eb30d838 381 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
b9d216fc
SP		 382#endif
383 {},
384};
385#endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */
386
fa82d0b4
SP		 387#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
388static const struct midr_range tsb_flush_fail_cpus[] = {
389#ifdef CONFIG_ARM64_ERRATUM_2067961
390 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
fb091ff3 391 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
fa82d0b4
SP		 392#endif
393#ifdef CONFIG_ARM64_ERRATUM_2054223
394 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
395#endif
396 {},
397};
398#endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */
399
8d81b2a3
SP		 400#ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
401static struct midr_range trbe_write_out_of_range_cpus[] = {
402#ifdef CONFIG_ARM64_ERRATUM_2253138
403 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
fb091ff3 404 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
8d81b2a3
SP		 405#endif
406#ifdef CONFIG_ARM64_ERRATUM_2224489
407 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
eb30d838 408 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
8d81b2a3
SP		 409#endif
410 {},
411};
412#endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */
413
44b3834b
JM		 414#ifdef CONFIG_ARM64_ERRATUM_1742098
415static struct midr_range broken_aarch32_aes[] = {
416 MIDR_RANGE(MIDR_CORTEX_A57, 0, 1, 0xf, 0xf),
417 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
418 {},
419};
420#endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */
421
f827bcda
RH		 422#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
423static const struct midr_range erratum_spec_unpriv_load_list[] = {
424#ifdef CONFIG_ARM64_ERRATUM_3117295
425 MIDR_ALL_VERSIONS(MIDR_CORTEX_A510),
426#endif
427#ifdef CONFIG_ARM64_ERRATUM_2966298
428 /* Cortex-A520 r0p0 to r0p1 */
429 MIDR_REV_RANGE(MIDR_CORTEX_A520, 0, 0, 1),
430#endif
431 {},
432};
433#endif
434
7187bb7d 435#ifdef CONFIG_ARM64_ERRATUM_3194386
ec768766 436static const struct midr_range erratum_spec_ssbs_list[] = {
adeec61a
MR		 437 MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),
438 MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),
439 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),
440 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),
75b3c43e
MR		 441 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
442 MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
adeec61a
MR		 443 MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
444 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
445 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),
75b3c43e
MR		 446 MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
447 MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
7187bb7d 448 MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
75b3c43e 449 MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),
adeec61a 450 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
75b3c43e 451 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
adeec61a 452 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
75b3c43e 453 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
adeec61a 454 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
7187bb7d
MR		 455 {}
456};
457#endif
458
db0d8a84
SP		 459#ifdef CONFIG_AMPERE_ERRATUM_AC03_CPU_38
460static const struct midr_range erratum_ac03_cpu_38_list[] = {
461 MIDR_ALL_VERSIONS(MIDR_AMPERE1),
462 MIDR_ALL_VERSIONS(MIDR_AMPERE1A),
463 {},
464};
465#endif
466
c9460dcb
SP		 467const struct arm64_cpu_capabilities arm64_errata[] = {
468#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
c0a01b84 469 {
357dd8a2 470 .desc = "ARM errata 826319, 827319, 824069, or 819472",
c0a01b84 471 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
c9460dcb 472 ERRATA_MIDR_RANGE_LIST(workaround_clean_cache),
c0cda3b8 473 .cpu_enable = cpu_enable_cache_maint_trap,
c0a01b84
AP		 474 },
475#endif
476#ifdef CONFIG_ARM64_ERRATUM_832075
301bcfac 477 {
5afaa1fc
AP		 478 /* Cortex-A57 r0p0 - r1p2 */
479 .desc = "ARM erratum 832075",
480 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
5e7951ce
SP		 481 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
482 0, 0,
483 1, 2),
5afaa1fc 484 },
905e8c5d 485#endif
498cd5c3
MZ		 486#ifdef CONFIG_ARM64_ERRATUM_834220
487 {
488 /* Cortex-A57 r0p0 - r1p2 */
489 .desc = "ARM erratum 834220",
490 .capability = ARM64_WORKAROUND_834220,
5e7951ce
SP		 491 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
492 0, 0,
493 1, 2),
498cd5c3
MZ		 494 },
495#endif
ca79acca
AB		 496#ifdef CONFIG_ARM64_ERRATUM_843419
497 {
ca79acca
AB		 498 .desc = "ARM erratum 843419",
499 .capability = ARM64_WORKAROUND_843419,
1cf45b8f
FF		 500 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
501 .matches = cpucap_multi_entry_cap_matches,
502 .match_list = erratum_843419_list,
498cd5c3
MZ		 503 },
504#endif
905e8c5d
WD		 505#ifdef CONFIG_ARM64_ERRATUM_845719
506 {
905e8c5d
WD		 507 .desc = "ARM erratum 845719",
508 .capability = ARM64_WORKAROUND_845719,
bfc97f9f 509 ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
905e8c5d 510 },
6d4e11c5
RR		 511#endif
512#ifdef CONFIG_CAVIUM_ERRATUM_23154
513 {
24a147bc 514 .desc = "Cavium errata 23154 and 38545",
6d4e11c5 515 .capability = ARM64_WORKAROUND_CAVIUM_23154,
24a147bc
LC		 516 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
517 ERRATA_MIDR_RANGE_LIST(cavium_erratum_23154_cpus),
6d4e11c5 518 },
104a0c02
AP		 519#endif
520#ifdef CONFIG_CAVIUM_ERRATUM_27456
521 {
47c459be
GK		 522 .desc = "Cavium erratum 27456",
523 .capability = ARM64_WORKAROUND_CAVIUM_27456,
f58cdf7e 524 ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus),
47c459be 525 },
690a3415
DD		 526#endif
527#ifdef CONFIG_CAVIUM_ERRATUM_30115
528 {
690a3415
DD		 529 .desc = "Cavium erratum 30115",
530 .capability = ARM64_WORKAROUND_CAVIUM_30115,
f58cdf7e 531 ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus),
690a3415 532 },
c0a01b84 533#endif
116c81f4 534 {
880f7cc4 535 .desc = "Mismatched cache type (CTR_EL0)",
314d53d2
SP		 536 .capability = ARM64_MISMATCHED_CACHE_TYPE,
537 .matches = has_mismatched_cache_type,
5b4747c5 538 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
c0cda3b8 539 .cpu_enable = cpu_enable_trap_ctr_access,
116c81f4 540 },
38fd94b0
CC		 541#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
542 {
a3dcea2c 543 .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
bb487118 544 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
d4af3c4b 545 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
1e013d06 546 .matches = cpucap_multi_entry_cap_matches,
a3dcea2c 547 .match_list = qcom_erratum_1003_list,
bb487118 548 },
38fd94b0 549#endif
ce8c80c5 550#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
d9ff80f8 551 {
39fdb65f 552 .desc = "Qualcomm erratum 1009, or ARM erratum 1286807, 2441009",
d9ff80f8 553 .capability = ARM64_WORKAROUND_REPEAT_TLBI,
36c602dc
BA		 554 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
555 .matches = cpucap_multi_entry_cap_matches,
556 .match_list = arm64_repeat_tlbi_list,
d9ff80f8 557 },
eeb1efbc
MZ		 558#endif
559#ifdef CONFIG_ARM64_ERRATUM_858921
560 {
561 /* Cortex-A73 all versions */
562 .desc = "ARM erratum 858921",
563 .capability = ARM64_WORKAROUND_858921,
5e7951ce 564 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
eeb1efbc 565 },
aa6acde6 566#endif
aa6acde6 567 {
d4647f0a 568 .desc = "Spectre-v2",
688f1e4b 569 .capability = ARM64_SPECTRE_V2,
73f38166 570 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
d4647f0a
WD		 571 .matches = has_spectre_v2,
572 .cpu_enable = spectre_v2_enable_mitigation,
f3d795d9 573 },
a59a2edb 574#ifdef CONFIG_RANDOMIZE_BASE
4b472ffd 575 {
b881cdce 576 /* Must come after the Spectre-v2 entry */
c4792b6d
WD		 577 .desc = "Spectre-v3a",
578 .capability = ARM64_SPECTRE_V3A,
cd1f56b9
WD		 579 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
580 .matches = has_spectre_v3a,
c4792b6d 581 .cpu_enable = spectre_v3a_enable_mitigation,
4b472ffd 582 },
a725e3dd 583#endif
a725e3dd 584 {
c2876207 585 .desc = "Spectre-v4",
9b0955ba 586 .capability = ARM64_SPECTRE_V4,
a725e3dd 587 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
c2876207
WD		 588 .matches = has_spectre_v4,
589 .cpu_enable = spectre_v4_enable_mitigation,
a725e3dd 590 },
558c303c
JM		 591 {
592 .desc = "Spectre-BHB",
593 .capability = ARM64_SPECTRE_BHB,
594 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
595 .matches = is_spectre_bhb_affected,
596 .cpu_enable = spectre_bhb_enable_mitigation,
597 },
a5325089 598#ifdef CONFIG_ARM64_ERRATUM_1418040
95b861a4 599 {
a5325089
MZ		 600 .desc = "ARM erratum 1418040",
601 .capability = ARM64_WORKAROUND_1418040,
602 ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
ed888cb0
MZ		 603 /*
604 * We need to allow affected CPUs to come in late, but
605 * also need the non-affected CPUs to be able to come
606 * in at any point in time. Wonderful.
607 */
608 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
95b861a4 609 },
8b2cca9a 610#endif
02ab1f50 611#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
8b2cca9a 612 {
c350717e 613 .desc = "ARM errata 1165522, 1319367, or 1530923",
02ab1f50
AS		 614 .capability = ARM64_WORKAROUND_SPECULATIVE_AT,
615 ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list),
8b2cca9a 616 },
969f5ea6
WD		 617#endif
618#ifdef CONFIG_ARM64_ERRATUM_1463225
619 {
620 .desc = "ARM erratum 1463225",
621 .capability = ARM64_WORKAROUND_1463225,
622 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
623 .matches = has_cortex_a76_erratum_1463225,
a9e821b8 624 .midr_range_list = erratum_1463225,
969f5ea6 625 },
93916beb
MZ		 626#endif
627#ifdef CONFIG_CAVIUM_TX2_ERRATUM_219
628 {
629 .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)",
630 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM,
631 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
632 .matches = needs_tx2_tvm_workaround,
633 },
9405447e
MZ		 634 {
635 .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)",
636 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM,
637 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
638 },
6a036afb 639#endif
05460849
JM		 640#ifdef CONFIG_ARM64_ERRATUM_1542419
641 {
642 /* we depend on the firmware portion for correctness */
643 .desc = "ARM erratum 1542419 (kernel portion)",
644 .capability = ARM64_WORKAROUND_1542419,
645 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
646 .matches = has_neoverse_n1_erratum_1542419,
647 .cpu_enable = cpu_enable_trap_ctr_access,
648 },
96d389ca
RH		 649#endif
650#ifdef CONFIG_ARM64_ERRATUM_1508412
651 {
652 /* we depend on the firmware portion for correctness */
653 .desc = "ARM erratum 1508412 (kernel portion)",
654 .capability = ARM64_WORKAROUND_1508412,
655 ERRATA_MIDR_RANGE(MIDR_CORTEX_A77,
656 0, 0,
657 1, 0),
658 },
20109a85
RW		 659#endif
660#ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM
661 {
662 /* NVIDIA Carmel */
663 .desc = "NVIDIA Carmel CNP erratum",
664 .capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP,
665 ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
666 },
b9d216fc
SP		 667#endif
668#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
669 {
670 /*
671 * The erratum work around is handled within the TRBE
672 * driver and can be applied per-cpu. So, we can allow
673 * a late CPU to come online with this erratum.
674 */
675 .desc = "ARM erratum 2119858 or 2139208",
676 .capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE,
677 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
678 CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus),
679 },
fa82d0b4
SP		 680#endif
681#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
682 {
683 .desc = "ARM erratum 2067961 or 2054223",
684 .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE,
685 ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus),
686 },
8d81b2a3
SP		 687#endif
688#ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
689 {
690 .desc = "ARM erratum 2253138 or 2224489",
691 .capability = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE,
692 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
693 CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus),
694 },
607a9afa 695#endif
5db568e7
AK		 696#ifdef CONFIG_ARM64_ERRATUM_2645198
697 {
698 .desc = "ARM erratum 2645198",
699 .capability = ARM64_WORKAROUND_2645198,
700 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A715)
701 },
702#endif
1dd498e5
JM		 703#ifdef CONFIG_ARM64_ERRATUM_2077057
704 {
705 .desc = "ARM erratum 2077057",
706 .capability = ARM64_WORKAROUND_2077057,
1dd498e5
JM		 707 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2),
708 },
709#endif
607a9afa
AK		 710#ifdef CONFIG_ARM64_ERRATUM_2064142
711 {
712 .desc = "ARM erratum 2064142",
713 .capability = ARM64_WORKAROUND_2064142,
714
715 /* Cortex-A510 r0p0 - r0p2 */
716 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
717 },
d9ff80f8 718#endif
e89d120c
IV		 719#ifdef CONFIG_ARM64_ERRATUM_2457168
720 {
721 .desc = "ARM erratum 2457168",
722 .capability = ARM64_WORKAROUND_2457168,
723 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
724
725 /* Cortex-A510 r0p0-r1p1 */
726 CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1)
727 },
728#endif
3bd94a87
AK		 729#ifdef CONFIG_ARM64_ERRATUM_2038923
730 {
731 .desc = "ARM erratum 2038923",
732 .capability = ARM64_WORKAROUND_2038923,
733
734 /* Cortex-A510 r0p0 - r0p2 */
735 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
736 },
708e8af4
AK		 737#endif
738#ifdef CONFIG_ARM64_ERRATUM_1902691
739 {
740 .desc = "ARM erratum 1902691",
741 .capability = ARM64_WORKAROUND_1902691,
742
743 /* Cortex-A510 r0p0 - r0p1 */
744 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1)
745 },
44b3834b
JM		 746#endif
747#ifdef CONFIG_ARM64_ERRATUM_1742098
748 {
749 .desc = "ARM erratum 1742098",
750 .capability = ARM64_WORKAROUND_1742098,
751 CAP_MIDR_RANGE_LIST(broken_aarch32_aes),
752 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
753 },
1bdb0fbb
JM		 754#endif
755#ifdef CONFIG_ARM64_ERRATUM_2658417
756 {
757 .desc = "ARM erratum 2658417",
758 .capability = ARM64_WORKAROUND_2658417,
759 /* Cortex-A510 r0p0 - r1p1 */
760 ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),
761 MIDR_FIXED(MIDR_CPU_VAR_REV(1,1), BIT(25)),
1bdb0fbb 762 },
6df696cd 763#endif
ec768766 764#ifdef CONFIG_ARM64_ERRATUM_3194386
7187bb7d 765 {
75b3c43e 766 .desc = "SSBS not fully self-synchronizing",
7187bb7d
MR		 767 .capability = ARM64_WORKAROUND_SPECULATIVE_SSBS,
768 ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list),
769 },
770#endif
546b7cde 771#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
471470bc 772 {
f827bcda 773 .desc = "ARM errata 2966298, 3117295",
546b7cde 774 .capability = ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD,
471470bc 775 /* Cortex-A520 r0p0 - r0p1 */
f827bcda 776 ERRATA_MIDR_RANGE_LIST(erratum_spec_unpriv_load_list),
471470bc
RH		 777 },
778#endif
6df696cd
OU		 779#ifdef CONFIG_AMPERE_ERRATUM_AC03_CPU_38
780 {
781 .desc = "AmpereOne erratum AC03_CPU_38",
782 .capability = ARM64_WORKAROUND_AMPERE_AC03_CPU_38,
db0d8a84 783 ERRATA_MIDR_RANGE_LIST(erratum_ac03_cpu_38_list),
6df696cd 784 },
d9ff80f8 785#endif
5afaa1fc 786 {
301bcfac 787 }
e116a375 788};
Linux 6.x block layer and io_uring tree(s)