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e116a375 AP |
1 | /* |
2 | * Contains CPU specific errata definitions | |
3 | * | |
4 | * Copyright (C) 2014 ARM Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
e116a375 AP |
19 | #include <linux/types.h> |
20 | #include <asm/cpu.h> | |
21 | #include <asm/cputype.h> | |
22 | #include <asm/cpufeature.h> | |
23 | ||
301bcfac | 24 | static bool __maybe_unused |
92406f0c | 25 | is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) |
301bcfac | 26 | { |
92406f0c | 27 | WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); |
d5370f75 WD |
28 | return MIDR_IS_CPU_MODEL_RANGE(read_cpuid_id(), entry->midr_model, |
29 | entry->midr_range_min, | |
30 | entry->midr_range_max); | |
301bcfac AP |
31 | } |
32 | ||
116c81f4 SP |
33 | static bool |
34 | has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry, | |
35 | int scope) | |
36 | { | |
37 | WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); | |
38 | return (read_cpuid_cachetype() & arm64_ftr_reg_ctrel0.strict_mask) != | |
39 | (arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask); | |
40 | } | |
41 | ||
2a6dcb2b | 42 | static int cpu_enable_trap_ctr_access(void *__unused) |
116c81f4 SP |
43 | { |
44 | /* Clear SCTLR_EL1.UCT */ | |
45 | config_sctlr_el1(SCTLR_EL1_UCT, 0); | |
2a6dcb2b | 46 | return 0; |
116c81f4 SP |
47 | } |
48 | ||
301bcfac | 49 | #define MIDR_RANGE(model, min, max) \ |
92406f0c | 50 | .def_scope = SCOPE_LOCAL_CPU, \ |
359b7064 | 51 | .matches = is_affected_midr_range, \ |
301bcfac AP |
52 | .midr_model = model, \ |
53 | .midr_range_min = min, \ | |
54 | .midr_range_max = max | |
55 | ||
06f1494f MZ |
56 | #define MIDR_ALL_VERSIONS(model) \ |
57 | .def_scope = SCOPE_LOCAL_CPU, \ | |
58 | .matches = is_affected_midr_range, \ | |
59 | .midr_model = model, \ | |
60 | .midr_range_min = 0, \ | |
61 | .midr_range_max = (MIDR_VARIANT_MASK | MIDR_REVISION_MASK) | |
62 | ||
359b7064 | 63 | const struct arm64_cpu_capabilities arm64_errata[] = { |
c0a01b84 AP |
64 | #if defined(CONFIG_ARM64_ERRATUM_826319) || \ |
65 | defined(CONFIG_ARM64_ERRATUM_827319) || \ | |
66 | defined(CONFIG_ARM64_ERRATUM_824069) | |
301bcfac AP |
67 | { |
68 | /* Cortex-A53 r0p[012] */ | |
69 | .desc = "ARM errata 826319, 827319, 824069", | |
70 | .capability = ARM64_WORKAROUND_CLEAN_CACHE, | |
71 | MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02), | |
7dd01aef | 72 | .enable = cpu_enable_cache_maint_trap, |
301bcfac | 73 | }, |
c0a01b84 AP |
74 | #endif |
75 | #ifdef CONFIG_ARM64_ERRATUM_819472 | |
76 | { | |
77 | /* Cortex-A53 r0p[01] */ | |
78 | .desc = "ARM errata 819472", | |
79 | .capability = ARM64_WORKAROUND_CLEAN_CACHE, | |
80 | MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01), | |
7dd01aef | 81 | .enable = cpu_enable_cache_maint_trap, |
c0a01b84 AP |
82 | }, |
83 | #endif | |
84 | #ifdef CONFIG_ARM64_ERRATUM_832075 | |
301bcfac | 85 | { |
5afaa1fc AP |
86 | /* Cortex-A57 r0p0 - r1p2 */ |
87 | .desc = "ARM erratum 832075", | |
88 | .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, | |
fa5ce3d1 RR |
89 | MIDR_RANGE(MIDR_CORTEX_A57, |
90 | MIDR_CPU_VAR_REV(0, 0), | |
91 | MIDR_CPU_VAR_REV(1, 2)), | |
5afaa1fc | 92 | }, |
905e8c5d | 93 | #endif |
498cd5c3 MZ |
94 | #ifdef CONFIG_ARM64_ERRATUM_834220 |
95 | { | |
96 | /* Cortex-A57 r0p0 - r1p2 */ | |
97 | .desc = "ARM erratum 834220", | |
98 | .capability = ARM64_WORKAROUND_834220, | |
fa5ce3d1 RR |
99 | MIDR_RANGE(MIDR_CORTEX_A57, |
100 | MIDR_CPU_VAR_REV(0, 0), | |
101 | MIDR_CPU_VAR_REV(1, 2)), | |
498cd5c3 MZ |
102 | }, |
103 | #endif | |
905e8c5d WD |
104 | #ifdef CONFIG_ARM64_ERRATUM_845719 |
105 | { | |
106 | /* Cortex-A53 r0p[01234] */ | |
107 | .desc = "ARM erratum 845719", | |
108 | .capability = ARM64_WORKAROUND_845719, | |
109 | MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04), | |
110 | }, | |
6d4e11c5 RR |
111 | #endif |
112 | #ifdef CONFIG_CAVIUM_ERRATUM_23154 | |
113 | { | |
114 | /* Cavium ThunderX, pass 1.x */ | |
115 | .desc = "Cavium erratum 23154", | |
116 | .capability = ARM64_WORKAROUND_CAVIUM_23154, | |
117 | MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01), | |
118 | }, | |
104a0c02 AP |
119 | #endif |
120 | #ifdef CONFIG_CAVIUM_ERRATUM_27456 | |
121 | { | |
122 | /* Cavium ThunderX, T88 pass 1.x - 2.1 */ | |
123 | .desc = "Cavium erratum 27456", | |
124 | .capability = ARM64_WORKAROUND_CAVIUM_27456, | |
fa5ce3d1 RR |
125 | MIDR_RANGE(MIDR_THUNDERX, |
126 | MIDR_CPU_VAR_REV(0, 0), | |
127 | MIDR_CPU_VAR_REV(1, 1)), | |
104a0c02 | 128 | }, |
47c459be GK |
129 | { |
130 | /* Cavium ThunderX, T81 pass 1.0 */ | |
131 | .desc = "Cavium erratum 27456", | |
132 | .capability = ARM64_WORKAROUND_CAVIUM_27456, | |
133 | MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00), | |
134 | }, | |
c0a01b84 | 135 | #endif |
116c81f4 SP |
136 | { |
137 | .desc = "Mismatched cache line size", | |
138 | .capability = ARM64_MISMATCHED_CACHE_LINE_SIZE, | |
139 | .matches = has_mismatched_cache_line_size, | |
140 | .def_scope = SCOPE_LOCAL_CPU, | |
141 | .enable = cpu_enable_trap_ctr_access, | |
142 | }, | |
38fd94b0 CC |
143 | #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 |
144 | { | |
145 | .desc = "Qualcomm Technologies Falkor erratum 1003", | |
146 | .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003, | |
147 | MIDR_RANGE(MIDR_QCOM_FALKOR_V1, | |
148 | MIDR_CPU_VAR_REV(0, 0), | |
149 | MIDR_CPU_VAR_REV(0, 0)), | |
150 | }, | |
151 | #endif | |
d9ff80f8 CC |
152 | #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 |
153 | { | |
154 | .desc = "Qualcomm Technologies Falkor erratum 1009", | |
155 | .capability = ARM64_WORKAROUND_REPEAT_TLBI, | |
156 | MIDR_RANGE(MIDR_QCOM_FALKOR_V1, | |
157 | MIDR_CPU_VAR_REV(0, 0), | |
158 | MIDR_CPU_VAR_REV(0, 0)), | |
159 | }, | |
eeb1efbc MZ |
160 | #endif |
161 | #ifdef CONFIG_ARM64_ERRATUM_858921 | |
162 | { | |
163 | /* Cortex-A73 all versions */ | |
164 | .desc = "ARM erratum 858921", | |
165 | .capability = ARM64_WORKAROUND_858921, | |
166 | MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), | |
167 | }, | |
d9ff80f8 | 168 | #endif |
5afaa1fc | 169 | { |
301bcfac | 170 | } |
e116a375 AP |
171 | }; |
172 | ||
6a6efbb4 SP |
173 | /* |
174 | * The CPU Errata work arounds are detected and applied at boot time | |
175 | * and the related information is freed soon after. If the new CPU requires | |
176 | * an errata not detected at boot, fail this CPU. | |
177 | */ | |
89ba2645 | 178 | void verify_local_cpu_errata_workarounds(void) |
6a6efbb4 SP |
179 | { |
180 | const struct arm64_cpu_capabilities *caps = arm64_errata; | |
181 | ||
182 | for (; caps->matches; caps++) | |
183 | if (!cpus_have_cap(caps->capability) && | |
184 | caps->matches(caps, SCOPE_LOCAL_CPU)) { | |
185 | pr_crit("CPU%d: Requires work around for %s, not detected" | |
186 | " at boot time\n", | |
187 | smp_processor_id(), | |
188 | caps->desc ? : "an erratum"); | |
189 | cpu_die_early(); | |
190 | } | |
191 | } | |
192 | ||
89ba2645 | 193 | void update_cpu_errata_workarounds(void) |
e116a375 | 194 | { |
ce8b602c | 195 | update_cpu_capabilities(arm64_errata, "enabling workaround for"); |
e116a375 | 196 | } |
8e231852 AP |
197 | |
198 | void __init enable_errata_workarounds(void) | |
199 | { | |
200 | enable_cpu_capabilities(arm64_errata); | |
201 | } |