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Merge branches 'pm-cpuidle', 'pm-core' and 'pm-sleep'
[linux-block.git] / arch / arm64 / kernel / cpu_errata.c
CommitLineData
caab277b 1// SPDX-License-Identifier: GPL-2.0-only
e116a375
AP		 2/*
3 * Contains CPU specific errata definitions
4 *
5 * Copyright (C) 2014 ARM Ltd.
e116a375
AP		 6 */
7
94a5d879 8#include <linux/arm-smccc.h>
e116a375 9#include <linux/types.h>
a111b7c0 10#include <linux/cpu.h>
e116a375
AP		 11#include <asm/cpu.h>
12#include <asm/cputype.h>
13#include <asm/cpufeature.h>
4db61fef 14#include <asm/kvm_asm.h>
93916beb 15#include <asm/smp_plat.h>
e116a375 16
301bcfac 17static bool __maybe_unused
92406f0c 18is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
301bcfac 19{
e8002e02
AB		 20 const struct arm64_midr_revidr *fix;
21 u32 midr = read_cpuid_id(), revidr;
22
92406f0c 23 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
1df31050 24 if (!is_midr_in_range(midr, &entry->midr_range))
e8002e02
AB		 25 return false;
26
27 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
28 revidr = read_cpuid(REVIDR_EL1);
29 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
30 if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
31 return false;
32
33 return true;
301bcfac
AP		 34}
35
be5b2998
SP		 36static bool __maybe_unused
37is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
38 int scope)
301bcfac 39{
92406f0c 40 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
be5b2998 41 return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
301bcfac
AP		 42}
43
bb487118
SB		 44static bool __maybe_unused
45is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
46{
47 u32 model;
48
49 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
50
51 model = read_cpuid_id();
52 model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
53 MIDR_ARCHITECTURE_MASK;
54
1df31050 55 return model == entry->midr_range.model;
bb487118
SB		 56}
57
116c81f4 58static bool
314d53d2
SP		 59has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
60 int scope)
116c81f4 61{
1602df02
SP		 62 u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
63 u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask;
64 u64 ctr_raw, ctr_real;
314d53d2 65
116c81f4 66 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
1602df02
SP		 67
68 /*
69 * We want to make sure that all the CPUs in the system expose
70 * a consistent CTR_EL0 to make sure that applications behaves
71 * correctly with migration.
72 *
73 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 :
74 *
75 * 1) It is safe if the system doesn't support IDC, as CPU anyway
76 * reports IDC = 0, consistent with the rest.
77 *
78 * 2) If the system has IDC, it is still safe as we trap CTR_EL0
79 * access on this CPU via the ARM64_HAS_CACHE_IDC capability.
80 *
81 * So, we need to make sure either the raw CTR_EL0 or the effective
82 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot.
83 */
84 ctr_raw = read_cpuid_cachetype() & mask;
85 ctr_real = read_cpuid_effective_cachetype() & mask;
86
87 return (ctr_real != sys) && (ctr_raw != sys);
116c81f4
SP		 88}
89
c0cda3b8 90static void
05460849 91cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap)
116c81f4 92{
4afe8e79 93 u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
05460849 94 bool enable_uct_trap = false;
4afe8e79
SP		 95
96 /* Trap CTR_EL0 access on this CPU, only if it has a mismatch */
97 if ((read_cpuid_cachetype() & mask) !=
98 (arm64_ftr_reg_ctrel0.sys_val & mask))
05460849
JM		 99 enable_uct_trap = true;
100
101 /* ... or if the system is affected by an erratum */
102 if (cap->capability == ARM64_WORKAROUND_1542419)
103 enable_uct_trap = true;
104
105 if (enable_uct_trap)
4afe8e79 106 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
116c81f4
SP		 107}
108
969f5ea6 109#ifdef CONFIG_ARM64_ERRATUM_1463225
969f5ea6
WD		 110static bool
111has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
112 int scope)
113{
a9e821b8 114 return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode();
969f5ea6
WD		 115}
116#endif
117
b8925ee2
WD		 118static void __maybe_unused
119cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
120{
121 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
122}
123
1bdb0fbb
JM		 124static DEFINE_RAW_SPINLOCK(reg_user_mask_modification);
125static void __maybe_unused
126cpu_clear_bf16_from_user_emulation(const struct arm64_cpu_capabilities *__unused)
127{
128 struct arm64_ftr_reg *regp;
129
130 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1);
131 if (!regp)
132 return;
133
134 raw_spin_lock(&reg_user_mask_modification);
135 if (regp->user_mask & ID_AA64ISAR1_EL1_BF16_MASK)
136 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK;
137 raw_spin_unlock(&reg_user_mask_modification);
138}
139
5e7951ce
SP		 140#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
141 .matches = is_affected_midr_range, \
1df31050 142 .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
5e7951ce
SP		 143
144#define CAP_MIDR_ALL_VERSIONS(model) \
145 .matches = is_affected_midr_range, \
1df31050 146 .midr_range = MIDR_ALL_VERSIONS(model)
06f1494f 147
e8002e02
AB		 148#define MIDR_FIXED(rev, revidr_mask) \
149 .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
150
5e7951ce
SP		 151#define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
152 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
153 CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
154
be5b2998
SP		 155#define CAP_MIDR_RANGE_LIST(list) \
156 .matches = is_affected_midr_range_list, \
157 .midr_range_list = list
158
5e7951ce
SP		 159/* Errata affecting a range of revisions of given model variant */
160#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
161 ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
162
163/* Errata affecting a single variant/revision of a model */
164#define ERRATA_MIDR_REV(model, var, rev) \
165 ERRATA_MIDR_RANGE(model, var, rev, var, rev)
166
167/* Errata affecting all variants/revisions of a given a model */
168#define ERRATA_MIDR_ALL_VERSIONS(model) \
169 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
170 CAP_MIDR_ALL_VERSIONS(model)
171
be5b2998
SP		 172/* Errata affecting a list of midr ranges, with same work around */
173#define ERRATA_MIDR_RANGE_LIST(midr_list) \
174 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
175 CAP_MIDR_RANGE_LIST(midr_list)
176
93916beb
MZ		 177static const __maybe_unused struct midr_range tx2_family_cpus[] = {
178 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
179 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
180 {},
181};
182
183static bool __maybe_unused
184needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,
185 int scope)
186{
187 int i;
188
189 if (!is_affected_midr_range_list(entry, scope) ||
190 !is_hyp_mode_available())
191 return false;
192
193 for_each_possible_cpu(i) {
194 if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0)
195 return true;
196 }
197
198 return false;
199}
200
05460849
JM		 201static bool __maybe_unused
202has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
203 int scope)
204{
205 u32 midr = read_cpuid_id();
5b345e39 206 bool has_dic = read_cpuid_cachetype() & BIT(CTR_EL0_DIC_SHIFT);
05460849
JM		 207 const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
208
209 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
210 return is_midr_in_range(midr, &range) && has_dic;
211}
8892b718 212
ce8c80c5 213#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
36c602dc 214static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
ce8c80c5 215#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
36c602dc
BA		 216 {
217 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)
218 },
219 {
220 .midr_range.model = MIDR_QCOM_KRYO,
221 .matches = is_kryo_midr,
222 },
ce8c80c5
CM		 223#endif
224#ifdef CONFIG_ARM64_ERRATUM_1286807
36c602dc
BA		 225 {
226 ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
5e1e0874
ZY		 227 },
228 {
51f559d6
S		 229 /* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */
230 ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),
36c602dc 231 },
39fdb65f 232#endif
171df580
JM		 233#ifdef CONFIG_ARM64_ERRATUM_2441007
234 {
235 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
236 },
237#endif
39fdb65f
JM		 238#ifdef CONFIG_ARM64_ERRATUM_2441009
239 {
240 /* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */
241 ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),
242 },
ce8c80c5
CM		 243#endif
244 {},
245};
ce8c80c5
CM		 246#endif
247
24a147bc 248#ifdef CONFIG_CAVIUM_ERRATUM_23154
710c8d6c 249static const struct midr_range cavium_erratum_23154_cpus[] = {
24a147bc
LC		 250 MIDR_ALL_VERSIONS(MIDR_THUNDERX),
251 MIDR_ALL_VERSIONS(MIDR_THUNDERX_81XX),
252 MIDR_ALL_VERSIONS(MIDR_THUNDERX_83XX),
253 MIDR_ALL_VERSIONS(MIDR_OCTX2_98XX),
254 MIDR_ALL_VERSIONS(MIDR_OCTX2_96XX),
255 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XX),
256 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXN),
257 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXMM),
258 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXO),
f90205b9 259 {},
24a147bc
LC		 260};
261#endif
262
f58cdf7e 263#ifdef CONFIG_CAVIUM_ERRATUM_27456
b89d82ef 264const struct midr_range cavium_erratum_27456_cpus[] = {
f58cdf7e
SP		 265 /* Cavium ThunderX, T88 pass 1.x - 2.1 */
266 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1),
267 /* Cavium ThunderX, T81 pass 1.0 */
268 MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
269 {},
270};
271#endif
272
273#ifdef CONFIG_CAVIUM_ERRATUM_30115
274static const struct midr_range cavium_erratum_30115_cpus[] = {
275 /* Cavium ThunderX, T88 pass 1.x - 2.2 */
276 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2),
277 /* Cavium ThunderX, T81 pass 1.0 - 1.2 */
278 MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
279 /* Cavium ThunderX, T83 pass 1.0 */
280 MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
281 {},
282};
283#endif
284
a3dcea2c
SP		 285#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
286static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {
287 {
288 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
289 },
290 {
291 .midr_range.model = MIDR_QCOM_KRYO,
292 .matches = is_kryo_midr,
293 },
294 {},
295};
296#endif
297
c9460dcb
SP		 298#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
299static const struct midr_range workaround_clean_cache[] = {
c0a01b84
AP		 300#if defined(CONFIG_ARM64_ERRATUM_826319) || \
301 defined(CONFIG_ARM64_ERRATUM_827319) || \
302 defined(CONFIG_ARM64_ERRATUM_824069)
c9460dcb
SP		 303 /* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */
304 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
305#endif
306#ifdef CONFIG_ARM64_ERRATUM_819472
307 /* Cortex-A53 r0p[01] : ARM errata 819472 */
308 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
c0a01b84 309#endif
c9460dcb
SP		 310 {},
311};
312#endif
313
a5325089
MZ		 314#ifdef CONFIG_ARM64_ERRATUM_1418040
315/*
316 * - 1188873 affects r0p0 to r2p0
317 * - 1418040 affects r0p0 to r3p1
318 */
319static const struct midr_range erratum_1418040_list[] = {
320 /* Cortex-A76 r0p0 to r3p1 */
321 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
322 /* Neoverse-N1 r0p0 to r3p1 */
323 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),
a9e821b8
SPR		 324 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
325 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
6989303a
MZ		 326 {},
327};
328#endif
329
bfc97f9f
DB		 330#ifdef CONFIG_ARM64_ERRATUM_845719
331static const struct midr_range erratum_845719_list[] = {
332 /* Cortex-A53 r0p[01234] */
333 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
334 /* Brahma-B53 r0p[0] */
335 MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
23c21641
KD		 336 /* Kryo2XX Silver rAp4 */
337 MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4),
bfc97f9f
DB		 338 {},
339};
340#endif
341
1cf45b8f
FF		 342#ifdef CONFIG_ARM64_ERRATUM_843419
343static const struct arm64_cpu_capabilities erratum_843419_list[] = {
344 {
345 /* Cortex-A53 r0p[01234] */
346 .matches = is_affected_midr_range,
347 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
348 MIDR_FIXED(0x4, BIT(8)),
349 },
350 {
351 /* Brahma-B53 r0p[0] */
352 .matches = is_affected_midr_range,
353 ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
354 },
355 {},
356};
357#endif
358
02ab1f50
AS		 359#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
360static const struct midr_range erratum_speculative_at_list[] = {
e85d68fa
SP		 361#ifdef CONFIG_ARM64_ERRATUM_1165522
362 /* Cortex A76 r0p0 to r2p0 */
363 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
275fa0ea 364#endif
02ab1f50
AS		 365#ifdef CONFIG_ARM64_ERRATUM_1319367
366 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
367 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
368#endif
275fa0ea
SP		 369#ifdef CONFIG_ARM64_ERRATUM_1530923
370 /* Cortex A55 r0p0 to r2p0 */
371 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
9b23d95c
SPR		 372 /* Kryo4xx Silver (rdpe => r1p0) */
373 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
e85d68fa
SP		 374#endif
375 {},
376};
377#endif
378
a9e821b8
SPR		 379#ifdef CONFIG_ARM64_ERRATUM_1463225
380static const struct midr_range erratum_1463225[] = {
381 /* Cortex-A76 r0p0 - r3p1 */
382 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
383 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
384 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
09c717c9 385 {},
a9e821b8
SPR		 386};
387#endif
388
b9d216fc
SP		 389#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
390static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
391#ifdef CONFIG_ARM64_ERRATUM_2139208
392 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
393#endif
394#ifdef CONFIG_ARM64_ERRATUM_2119858
395 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
eb30d838 396 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
b9d216fc
SP		 397#endif
398 {},
399};
400#endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */
401
fa82d0b4
SP		 402#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
403static const struct midr_range tsb_flush_fail_cpus[] = {
404#ifdef CONFIG_ARM64_ERRATUM_2067961
405 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
406#endif
407#ifdef CONFIG_ARM64_ERRATUM_2054223
408 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
409#endif
410 {},
411};
412#endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */
413
8d81b2a3
SP		 414#ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
415static struct midr_range trbe_write_out_of_range_cpus[] = {
416#ifdef CONFIG_ARM64_ERRATUM_2253138
417 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
418#endif
419#ifdef CONFIG_ARM64_ERRATUM_2224489
420 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
eb30d838 421 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
8d81b2a3
SP		 422#endif
423 {},
424};
425#endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */
426
44b3834b
JM		 427#ifdef CONFIG_ARM64_ERRATUM_1742098
428static struct midr_range broken_aarch32_aes[] = {
429 MIDR_RANGE(MIDR_CORTEX_A57, 0, 1, 0xf, 0xf),
430 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
431 {},
432};
433#endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */
434
c9460dcb
SP		 435const struct arm64_cpu_capabilities arm64_errata[] = {
436#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
c0a01b84 437 {
357dd8a2 438 .desc = "ARM errata 826319, 827319, 824069, or 819472",
c0a01b84 439 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
c9460dcb 440 ERRATA_MIDR_RANGE_LIST(workaround_clean_cache),
c0cda3b8 441 .cpu_enable = cpu_enable_cache_maint_trap,
c0a01b84
AP		 442 },
443#endif
444#ifdef CONFIG_ARM64_ERRATUM_832075
301bcfac 445 {
5afaa1fc
AP		 446 /* Cortex-A57 r0p0 - r1p2 */
447 .desc = "ARM erratum 832075",
448 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
5e7951ce
SP		 449 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
450 0, 0,
451 1, 2),
5afaa1fc 452 },
905e8c5d 453#endif
498cd5c3
MZ		 454#ifdef CONFIG_ARM64_ERRATUM_834220
455 {
456 /* Cortex-A57 r0p0 - r1p2 */
457 .desc = "ARM erratum 834220",
458 .capability = ARM64_WORKAROUND_834220,
5e7951ce
SP		 459 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
460 0, 0,
461 1, 2),
498cd5c3
MZ		 462 },
463#endif
ca79acca
AB		 464#ifdef CONFIG_ARM64_ERRATUM_843419
465 {
ca79acca
AB		 466 .desc = "ARM erratum 843419",
467 .capability = ARM64_WORKAROUND_843419,
1cf45b8f
FF		 468 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
469 .matches = cpucap_multi_entry_cap_matches,
470 .match_list = erratum_843419_list,
498cd5c3
MZ		 471 },
472#endif
905e8c5d
WD		 473#ifdef CONFIG_ARM64_ERRATUM_845719
474 {
905e8c5d
WD		 475 .desc = "ARM erratum 845719",
476 .capability = ARM64_WORKAROUND_845719,
bfc97f9f 477 ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
905e8c5d 478 },
6d4e11c5
RR		 479#endif
480#ifdef CONFIG_CAVIUM_ERRATUM_23154
481 {
24a147bc 482 .desc = "Cavium errata 23154 and 38545",
6d4e11c5 483 .capability = ARM64_WORKAROUND_CAVIUM_23154,
24a147bc
LC		 484 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
485 ERRATA_MIDR_RANGE_LIST(cavium_erratum_23154_cpus),
6d4e11c5 486 },
104a0c02
AP		 487#endif
488#ifdef CONFIG_CAVIUM_ERRATUM_27456
489 {
47c459be
GK		 490 .desc = "Cavium erratum 27456",
491 .capability = ARM64_WORKAROUND_CAVIUM_27456,
f58cdf7e 492 ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus),
47c459be 493 },
690a3415
DD		 494#endif
495#ifdef CONFIG_CAVIUM_ERRATUM_30115
496 {
690a3415
DD		 497 .desc = "Cavium erratum 30115",
498 .capability = ARM64_WORKAROUND_CAVIUM_30115,
f58cdf7e 499 ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus),
690a3415 500 },
c0a01b84 501#endif
116c81f4 502 {
880f7cc4 503 .desc = "Mismatched cache type (CTR_EL0)",
314d53d2
SP		 504 .capability = ARM64_MISMATCHED_CACHE_TYPE,
505 .matches = has_mismatched_cache_type,
5b4747c5 506 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
c0cda3b8 507 .cpu_enable = cpu_enable_trap_ctr_access,
116c81f4 508 },
38fd94b0
CC		 509#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
510 {
a3dcea2c 511 .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
bb487118 512 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
d4af3c4b 513 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
1e013d06 514 .matches = cpucap_multi_entry_cap_matches,
a3dcea2c 515 .match_list = qcom_erratum_1003_list,
bb487118 516 },
38fd94b0 517#endif
ce8c80c5 518#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
d9ff80f8 519 {
39fdb65f 520 .desc = "Qualcomm erratum 1009, or ARM erratum 1286807, 2441009",
d9ff80f8 521 .capability = ARM64_WORKAROUND_REPEAT_TLBI,
36c602dc
BA		 522 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
523 .matches = cpucap_multi_entry_cap_matches,
524 .match_list = arm64_repeat_tlbi_list,
d9ff80f8 525 },
eeb1efbc
MZ		 526#endif
527#ifdef CONFIG_ARM64_ERRATUM_858921
528 {
529 /* Cortex-A73 all versions */
530 .desc = "ARM erratum 858921",
531 .capability = ARM64_WORKAROUND_858921,
5e7951ce 532 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
eeb1efbc 533 },
aa6acde6 534#endif
aa6acde6 535 {
d4647f0a 536 .desc = "Spectre-v2",
688f1e4b 537 .capability = ARM64_SPECTRE_V2,
73f38166 538 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
d4647f0a
WD		 539 .matches = has_spectre_v2,
540 .cpu_enable = spectre_v2_enable_mitigation,
f3d795d9 541 },
a59a2edb 542#ifdef CONFIG_RANDOMIZE_BASE
4b472ffd 543 {
b881cdce 544 /* Must come after the Spectre-v2 entry */
c4792b6d
WD		 545 .desc = "Spectre-v3a",
546 .capability = ARM64_SPECTRE_V3A,
cd1f56b9
WD		 547 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
548 .matches = has_spectre_v3a,
c4792b6d 549 .cpu_enable = spectre_v3a_enable_mitigation,
4b472ffd 550 },
a725e3dd 551#endif
a725e3dd 552 {
c2876207 553 .desc = "Spectre-v4",
9b0955ba 554 .capability = ARM64_SPECTRE_V4,
a725e3dd 555 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
c2876207
WD		 556 .matches = has_spectre_v4,
557 .cpu_enable = spectre_v4_enable_mitigation,
a725e3dd 558 },
558c303c
JM		 559 {
560 .desc = "Spectre-BHB",
561 .capability = ARM64_SPECTRE_BHB,
562 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
563 .matches = is_spectre_bhb_affected,
564 .cpu_enable = spectre_bhb_enable_mitigation,
565 },
a5325089 566#ifdef CONFIG_ARM64_ERRATUM_1418040
95b861a4 567 {
a5325089
MZ		 568 .desc = "ARM erratum 1418040",
569 .capability = ARM64_WORKAROUND_1418040,
570 ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
ed888cb0
MZ		 571 /*
572 * We need to allow affected CPUs to come in late, but
573 * also need the non-affected CPUs to be able to come
574 * in at any point in time. Wonderful.
575 */
576 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
95b861a4 577 },
8b2cca9a 578#endif
02ab1f50 579#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
8b2cca9a 580 {
c350717e 581 .desc = "ARM errata 1165522, 1319367, or 1530923",
02ab1f50
AS		 582 .capability = ARM64_WORKAROUND_SPECULATIVE_AT,
583 ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list),
8b2cca9a 584 },
969f5ea6
WD		 585#endif
586#ifdef CONFIG_ARM64_ERRATUM_1463225
587 {
588 .desc = "ARM erratum 1463225",
589 .capability = ARM64_WORKAROUND_1463225,
590 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
591 .matches = has_cortex_a76_erratum_1463225,
a9e821b8 592 .midr_range_list = erratum_1463225,
969f5ea6 593 },
93916beb
MZ		 594#endif
595#ifdef CONFIG_CAVIUM_TX2_ERRATUM_219
596 {
597 .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)",
598 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM,
599 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
600 .matches = needs_tx2_tvm_workaround,
601 },
9405447e
MZ		 602 {
603 .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)",
604 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM,
605 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
606 },
6a036afb 607#endif
05460849
JM		 608#ifdef CONFIG_ARM64_ERRATUM_1542419
609 {
610 /* we depend on the firmware portion for correctness */
611 .desc = "ARM erratum 1542419 (kernel portion)",
612 .capability = ARM64_WORKAROUND_1542419,
613 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
614 .matches = has_neoverse_n1_erratum_1542419,
615 .cpu_enable = cpu_enable_trap_ctr_access,
616 },
96d389ca
RH		 617#endif
618#ifdef CONFIG_ARM64_ERRATUM_1508412
619 {
620 /* we depend on the firmware portion for correctness */
621 .desc = "ARM erratum 1508412 (kernel portion)",
622 .capability = ARM64_WORKAROUND_1508412,
623 ERRATA_MIDR_RANGE(MIDR_CORTEX_A77,
624 0, 0,
625 1, 0),
626 },
20109a85
RW		 627#endif
628#ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM
629 {
630 /* NVIDIA Carmel */
631 .desc = "NVIDIA Carmel CNP erratum",
632 .capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP,
633 ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
634 },
b9d216fc
SP		 635#endif
636#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
637 {
638 /*
639 * The erratum work around is handled within the TRBE
640 * driver and can be applied per-cpu. So, we can allow
641 * a late CPU to come online with this erratum.
642 */
643 .desc = "ARM erratum 2119858 or 2139208",
644 .capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE,
645 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
646 CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus),
647 },
fa82d0b4
SP		 648#endif
649#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
650 {
651 .desc = "ARM erratum 2067961 or 2054223",
652 .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE,
653 ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus),
654 },
8d81b2a3
SP		 655#endif
656#ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
657 {
658 .desc = "ARM erratum 2253138 or 2224489",
659 .capability = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE,
660 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
661 CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus),
662 },
607a9afa 663#endif
5db568e7
AK		 664#ifdef CONFIG_ARM64_ERRATUM_2645198
665 {
666 .desc = "ARM erratum 2645198",
667 .capability = ARM64_WORKAROUND_2645198,
668 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A715)
669 },
670#endif
1dd498e5
JM		 671#ifdef CONFIG_ARM64_ERRATUM_2077057
672 {
673 .desc = "ARM erratum 2077057",
674 .capability = ARM64_WORKAROUND_2077057,
1dd498e5
JM		 675 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2),
676 },
677#endif
607a9afa
AK		 678#ifdef CONFIG_ARM64_ERRATUM_2064142
679 {
680 .desc = "ARM erratum 2064142",
681 .capability = ARM64_WORKAROUND_2064142,
682
683 /* Cortex-A510 r0p0 - r0p2 */
684 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
685 },
d9ff80f8 686#endif
e89d120c
IV		 687#ifdef CONFIG_ARM64_ERRATUM_2457168
688 {
689 .desc = "ARM erratum 2457168",
690 .capability = ARM64_WORKAROUND_2457168,
691 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
692
693 /* Cortex-A510 r0p0-r1p1 */
694 CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1)
695 },
696#endif
3bd94a87
AK		 697#ifdef CONFIG_ARM64_ERRATUM_2038923
698 {
699 .desc = "ARM erratum 2038923",
700 .capability = ARM64_WORKAROUND_2038923,
701
702 /* Cortex-A510 r0p0 - r0p2 */
703 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
704 },
708e8af4
AK		 705#endif
706#ifdef CONFIG_ARM64_ERRATUM_1902691
707 {
708 .desc = "ARM erratum 1902691",
709 .capability = ARM64_WORKAROUND_1902691,
710
711 /* Cortex-A510 r0p0 - r0p1 */
712 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1)
713 },
44b3834b
JM		 714#endif
715#ifdef CONFIG_ARM64_ERRATUM_1742098
716 {
717 .desc = "ARM erratum 1742098",
718 .capability = ARM64_WORKAROUND_1742098,
719 CAP_MIDR_RANGE_LIST(broken_aarch32_aes),
720 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
721 },
1bdb0fbb
JM		 722#endif
723#ifdef CONFIG_ARM64_ERRATUM_2658417
724 {
725 .desc = "ARM erratum 2658417",
726 .capability = ARM64_WORKAROUND_2658417,
727 /* Cortex-A510 r0p0 - r1p1 */
728 ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),
729 MIDR_FIXED(MIDR_CPU_VAR_REV(1,1), BIT(25)),
730 .cpu_enable = cpu_clear_bf16_from_user_emulation,
731 },
d9ff80f8 732#endif
5afaa1fc 733 {
301bcfac 734 }
e116a375 735};
Linux 6.x block layer and io_uring tree(s)