Commit | Line | Data |
---|---|---|
e116a375 AP |
1 | /* |
2 | * Contains CPU specific errata definitions | |
3 | * | |
4 | * Copyright (C) 2014 ARM Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
e116a375 AP |
19 | #include <linux/types.h> |
20 | #include <asm/cpu.h> | |
21 | #include <asm/cputype.h> | |
22 | #include <asm/cpufeature.h> | |
23 | ||
301bcfac | 24 | static bool __maybe_unused |
92406f0c | 25 | is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) |
301bcfac | 26 | { |
e8002e02 AB |
27 | const struct arm64_midr_revidr *fix; |
28 | u32 midr = read_cpuid_id(), revidr; | |
29 | ||
92406f0c | 30 | WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); |
e8002e02 AB |
31 | if (!MIDR_IS_CPU_MODEL_RANGE(midr, entry->midr_model, |
32 | entry->midr_range_min, | |
33 | entry->midr_range_max)) | |
34 | return false; | |
35 | ||
36 | midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK; | |
37 | revidr = read_cpuid(REVIDR_EL1); | |
38 | for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++) | |
39 | if (midr == fix->midr_rv && (revidr & fix->revidr_mask)) | |
40 | return false; | |
41 | ||
42 | return true; | |
301bcfac AP |
43 | } |
44 | ||
bb487118 SB |
45 | static bool __maybe_unused |
46 | is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope) | |
47 | { | |
48 | u32 model; | |
49 | ||
50 | WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); | |
51 | ||
52 | model = read_cpuid_id(); | |
53 | model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) | | |
54 | MIDR_ARCHITECTURE_MASK; | |
55 | ||
56 | return model == entry->midr_model; | |
57 | } | |
58 | ||
116c81f4 SP |
59 | static bool |
60 | has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry, | |
61 | int scope) | |
62 | { | |
63 | WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); | |
64 | return (read_cpuid_cachetype() & arm64_ftr_reg_ctrel0.strict_mask) != | |
65 | (arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask); | |
66 | } | |
67 | ||
2a6dcb2b | 68 | static int cpu_enable_trap_ctr_access(void *__unused) |
116c81f4 SP |
69 | { |
70 | /* Clear SCTLR_EL1.UCT */ | |
71 | config_sctlr_el1(SCTLR_EL1_UCT, 0); | |
2a6dcb2b | 72 | return 0; |
116c81f4 SP |
73 | } |
74 | ||
0f15adbb WD |
75 | #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR |
76 | #include <asm/mmu_context.h> | |
77 | #include <asm/cacheflush.h> | |
78 | ||
79 | DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); | |
80 | ||
81 | #ifdef CONFIG_KVM | |
ec82b567 SD |
82 | extern char __qcom_hyp_sanitize_link_stack_start[]; |
83 | extern char __qcom_hyp_sanitize_link_stack_end[]; | |
b092201e MZ |
84 | extern char __smccc_workaround_1_smc_start[]; |
85 | extern char __smccc_workaround_1_smc_end[]; | |
86 | extern char __smccc_workaround_1_hvc_start[]; | |
87 | extern char __smccc_workaround_1_hvc_end[]; | |
aa6acde6 | 88 | |
0f15adbb WD |
89 | static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start, |
90 | const char *hyp_vecs_end) | |
91 | { | |
92 | void *dst = lm_alias(__bp_harden_hyp_vecs_start + slot * SZ_2K); | |
93 | int i; | |
94 | ||
95 | for (i = 0; i < SZ_2K; i += 0x80) | |
96 | memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start); | |
97 | ||
98 | flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K); | |
99 | } | |
100 | ||
101 | static void __install_bp_hardening_cb(bp_hardening_cb_t fn, | |
102 | const char *hyp_vecs_start, | |
103 | const char *hyp_vecs_end) | |
104 | { | |
105 | static int last_slot = -1; | |
106 | static DEFINE_SPINLOCK(bp_lock); | |
107 | int cpu, slot = -1; | |
108 | ||
109 | spin_lock(&bp_lock); | |
110 | for_each_possible_cpu(cpu) { | |
111 | if (per_cpu(bp_hardening_data.fn, cpu) == fn) { | |
112 | slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu); | |
113 | break; | |
114 | } | |
115 | } | |
116 | ||
117 | if (slot == -1) { | |
118 | last_slot++; | |
119 | BUG_ON(((__bp_harden_hyp_vecs_end - __bp_harden_hyp_vecs_start) | |
120 | / SZ_2K) <= last_slot); | |
121 | slot = last_slot; | |
122 | __copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end); | |
123 | } | |
124 | ||
125 | __this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot); | |
126 | __this_cpu_write(bp_hardening_data.fn, fn); | |
127 | spin_unlock(&bp_lock); | |
128 | } | |
129 | #else | |
ec82b567 SD |
130 | #define __qcom_hyp_sanitize_link_stack_start NULL |
131 | #define __qcom_hyp_sanitize_link_stack_end NULL | |
b092201e MZ |
132 | #define __smccc_workaround_1_smc_start NULL |
133 | #define __smccc_workaround_1_smc_end NULL | |
134 | #define __smccc_workaround_1_hvc_start NULL | |
135 | #define __smccc_workaround_1_hvc_end NULL | |
aa6acde6 | 136 | |
0f15adbb WD |
137 | static void __install_bp_hardening_cb(bp_hardening_cb_t fn, |
138 | const char *hyp_vecs_start, | |
139 | const char *hyp_vecs_end) | |
140 | { | |
141 | __this_cpu_write(bp_hardening_data.fn, fn); | |
142 | } | |
143 | #endif /* CONFIG_KVM */ | |
144 | ||
145 | static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry, | |
146 | bp_hardening_cb_t fn, | |
147 | const char *hyp_vecs_start, | |
148 | const char *hyp_vecs_end) | |
149 | { | |
150 | u64 pfr0; | |
151 | ||
152 | if (!entry->matches(entry, SCOPE_LOCAL_CPU)) | |
153 | return; | |
154 | ||
155 | pfr0 = read_cpuid(ID_AA64PFR0_EL1); | |
156 | if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT)) | |
157 | return; | |
158 | ||
159 | __install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end); | |
160 | } | |
aa6acde6 | 161 | |
b092201e MZ |
162 | #include <uapi/linux/psci.h> |
163 | #include <linux/arm-smccc.h> | |
aa6acde6 WD |
164 | #include <linux/psci.h> |
165 | ||
b092201e MZ |
166 | static void call_smc_arch_workaround_1(void) |
167 | { | |
168 | arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); | |
169 | } | |
170 | ||
171 | static void call_hvc_arch_workaround_1(void) | |
172 | { | |
173 | arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); | |
174 | } | |
175 | ||
3a0a397f | 176 | static int enable_smccc_arch_workaround_1(void *data) |
b092201e | 177 | { |
3a0a397f | 178 | const struct arm64_cpu_capabilities *entry = data; |
b092201e MZ |
179 | bp_hardening_cb_t cb; |
180 | void *smccc_start, *smccc_end; | |
181 | struct arm_smccc_res res; | |
182 | ||
183 | if (!entry->matches(entry, SCOPE_LOCAL_CPU)) | |
3a0a397f | 184 | return 0; |
b092201e MZ |
185 | |
186 | if (psci_ops.smccc_version == SMCCC_VERSION_1_0) | |
3a0a397f | 187 | return 0; |
b092201e MZ |
188 | |
189 | switch (psci_ops.conduit) { | |
190 | case PSCI_CONDUIT_HVC: | |
191 | arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, | |
192 | ARM_SMCCC_ARCH_WORKAROUND_1, &res); | |
193 | if (res.a0) | |
3a0a397f | 194 | return 0; |
b092201e MZ |
195 | cb = call_hvc_arch_workaround_1; |
196 | smccc_start = __smccc_workaround_1_hvc_start; | |
197 | smccc_end = __smccc_workaround_1_hvc_end; | |
198 | break; | |
199 | ||
200 | case PSCI_CONDUIT_SMC: | |
201 | arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, | |
202 | ARM_SMCCC_ARCH_WORKAROUND_1, &res); | |
203 | if (res.a0) | |
3a0a397f | 204 | return 0; |
b092201e MZ |
205 | cb = call_smc_arch_workaround_1; |
206 | smccc_start = __smccc_workaround_1_smc_start; | |
207 | smccc_end = __smccc_workaround_1_smc_end; | |
208 | break; | |
209 | ||
210 | default: | |
3a0a397f | 211 | return 0; |
b092201e MZ |
212 | } |
213 | ||
214 | install_bp_hardening_cb(entry, cb, smccc_start, smccc_end); | |
215 | ||
aa6acde6 WD |
216 | return 0; |
217 | } | |
ec82b567 SD |
218 | |
219 | static void qcom_link_stack_sanitization(void) | |
220 | { | |
221 | u64 tmp; | |
222 | ||
223 | asm volatile("mov %0, x30 \n" | |
224 | ".rept 16 \n" | |
225 | "bl . + 4 \n" | |
226 | ".endr \n" | |
227 | "mov x30, %0 \n" | |
228 | : "=&r" (tmp)); | |
229 | } | |
230 | ||
231 | static int qcom_enable_link_stack_sanitization(void *data) | |
232 | { | |
233 | const struct arm64_cpu_capabilities *entry = data; | |
234 | ||
235 | install_bp_hardening_cb(entry, qcom_link_stack_sanitization, | |
236 | __qcom_hyp_sanitize_link_stack_start, | |
237 | __qcom_hyp_sanitize_link_stack_end); | |
238 | ||
239 | return 0; | |
240 | } | |
0f15adbb WD |
241 | #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ |
242 | ||
301bcfac | 243 | #define MIDR_RANGE(model, min, max) \ |
92406f0c | 244 | .def_scope = SCOPE_LOCAL_CPU, \ |
359b7064 | 245 | .matches = is_affected_midr_range, \ |
301bcfac AP |
246 | .midr_model = model, \ |
247 | .midr_range_min = min, \ | |
248 | .midr_range_max = max | |
249 | ||
06f1494f MZ |
250 | #define MIDR_ALL_VERSIONS(model) \ |
251 | .def_scope = SCOPE_LOCAL_CPU, \ | |
252 | .matches = is_affected_midr_range, \ | |
253 | .midr_model = model, \ | |
254 | .midr_range_min = 0, \ | |
255 | .midr_range_max = (MIDR_VARIANT_MASK | MIDR_REVISION_MASK) | |
256 | ||
e8002e02 AB |
257 | #define MIDR_FIXED(rev, revidr_mask) \ |
258 | .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}} | |
259 | ||
359b7064 | 260 | const struct arm64_cpu_capabilities arm64_errata[] = { |
c0a01b84 AP |
261 | #if defined(CONFIG_ARM64_ERRATUM_826319) || \ |
262 | defined(CONFIG_ARM64_ERRATUM_827319) || \ | |
263 | defined(CONFIG_ARM64_ERRATUM_824069) | |
301bcfac AP |
264 | { |
265 | /* Cortex-A53 r0p[012] */ | |
266 | .desc = "ARM errata 826319, 827319, 824069", | |
267 | .capability = ARM64_WORKAROUND_CLEAN_CACHE, | |
268 | MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02), | |
7dd01aef | 269 | .enable = cpu_enable_cache_maint_trap, |
301bcfac | 270 | }, |
c0a01b84 AP |
271 | #endif |
272 | #ifdef CONFIG_ARM64_ERRATUM_819472 | |
273 | { | |
274 | /* Cortex-A53 r0p[01] */ | |
275 | .desc = "ARM errata 819472", | |
276 | .capability = ARM64_WORKAROUND_CLEAN_CACHE, | |
277 | MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01), | |
7dd01aef | 278 | .enable = cpu_enable_cache_maint_trap, |
c0a01b84 AP |
279 | }, |
280 | #endif | |
281 | #ifdef CONFIG_ARM64_ERRATUM_832075 | |
301bcfac | 282 | { |
5afaa1fc AP |
283 | /* Cortex-A57 r0p0 - r1p2 */ |
284 | .desc = "ARM erratum 832075", | |
285 | .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, | |
fa5ce3d1 RR |
286 | MIDR_RANGE(MIDR_CORTEX_A57, |
287 | MIDR_CPU_VAR_REV(0, 0), | |
288 | MIDR_CPU_VAR_REV(1, 2)), | |
5afaa1fc | 289 | }, |
905e8c5d | 290 | #endif |
498cd5c3 MZ |
291 | #ifdef CONFIG_ARM64_ERRATUM_834220 |
292 | { | |
293 | /* Cortex-A57 r0p0 - r1p2 */ | |
294 | .desc = "ARM erratum 834220", | |
295 | .capability = ARM64_WORKAROUND_834220, | |
fa5ce3d1 RR |
296 | MIDR_RANGE(MIDR_CORTEX_A57, |
297 | MIDR_CPU_VAR_REV(0, 0), | |
298 | MIDR_CPU_VAR_REV(1, 2)), | |
498cd5c3 MZ |
299 | }, |
300 | #endif | |
ca79acca AB |
301 | #ifdef CONFIG_ARM64_ERRATUM_843419 |
302 | { | |
303 | /* Cortex-A53 r0p[01234] */ | |
304 | .desc = "ARM erratum 843419", | |
305 | .capability = ARM64_WORKAROUND_843419, | |
306 | MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04), | |
307 | MIDR_FIXED(0x4, BIT(8)), | |
308 | }, | |
309 | #endif | |
905e8c5d WD |
310 | #ifdef CONFIG_ARM64_ERRATUM_845719 |
311 | { | |
312 | /* Cortex-A53 r0p[01234] */ | |
313 | .desc = "ARM erratum 845719", | |
314 | .capability = ARM64_WORKAROUND_845719, | |
315 | MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04), | |
316 | }, | |
6d4e11c5 RR |
317 | #endif |
318 | #ifdef CONFIG_CAVIUM_ERRATUM_23154 | |
319 | { | |
320 | /* Cavium ThunderX, pass 1.x */ | |
321 | .desc = "Cavium erratum 23154", | |
322 | .capability = ARM64_WORKAROUND_CAVIUM_23154, | |
323 | MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01), | |
324 | }, | |
104a0c02 AP |
325 | #endif |
326 | #ifdef CONFIG_CAVIUM_ERRATUM_27456 | |
327 | { | |
328 | /* Cavium ThunderX, T88 pass 1.x - 2.1 */ | |
329 | .desc = "Cavium erratum 27456", | |
330 | .capability = ARM64_WORKAROUND_CAVIUM_27456, | |
fa5ce3d1 RR |
331 | MIDR_RANGE(MIDR_THUNDERX, |
332 | MIDR_CPU_VAR_REV(0, 0), | |
333 | MIDR_CPU_VAR_REV(1, 1)), | |
104a0c02 | 334 | }, |
47c459be GK |
335 | { |
336 | /* Cavium ThunderX, T81 pass 1.0 */ | |
337 | .desc = "Cavium erratum 27456", | |
338 | .capability = ARM64_WORKAROUND_CAVIUM_27456, | |
339 | MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00), | |
340 | }, | |
690a3415 DD |
341 | #endif |
342 | #ifdef CONFIG_CAVIUM_ERRATUM_30115 | |
343 | { | |
344 | /* Cavium ThunderX, T88 pass 1.x - 2.2 */ | |
345 | .desc = "Cavium erratum 30115", | |
346 | .capability = ARM64_WORKAROUND_CAVIUM_30115, | |
347 | MIDR_RANGE(MIDR_THUNDERX, 0x00, | |
348 | (1 << MIDR_VARIANT_SHIFT) | 2), | |
349 | }, | |
350 | { | |
351 | /* Cavium ThunderX, T81 pass 1.0 - 1.2 */ | |
352 | .desc = "Cavium erratum 30115", | |
353 | .capability = ARM64_WORKAROUND_CAVIUM_30115, | |
354 | MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x02), | |
355 | }, | |
356 | { | |
357 | /* Cavium ThunderX, T83 pass 1.0 */ | |
358 | .desc = "Cavium erratum 30115", | |
359 | .capability = ARM64_WORKAROUND_CAVIUM_30115, | |
360 | MIDR_RANGE(MIDR_THUNDERX_83XX, 0x00, 0x00), | |
361 | }, | |
c0a01b84 | 362 | #endif |
116c81f4 SP |
363 | { |
364 | .desc = "Mismatched cache line size", | |
365 | .capability = ARM64_MISMATCHED_CACHE_LINE_SIZE, | |
366 | .matches = has_mismatched_cache_line_size, | |
367 | .def_scope = SCOPE_LOCAL_CPU, | |
368 | .enable = cpu_enable_trap_ctr_access, | |
369 | }, | |
38fd94b0 CC |
370 | #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 |
371 | { | |
372 | .desc = "Qualcomm Technologies Falkor erratum 1003", | |
373 | .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003, | |
374 | MIDR_RANGE(MIDR_QCOM_FALKOR_V1, | |
375 | MIDR_CPU_VAR_REV(0, 0), | |
376 | MIDR_CPU_VAR_REV(0, 0)), | |
377 | }, | |
bb487118 SB |
378 | { |
379 | .desc = "Qualcomm Technologies Kryo erratum 1003", | |
380 | .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003, | |
381 | .def_scope = SCOPE_LOCAL_CPU, | |
382 | .midr_model = MIDR_QCOM_KRYO, | |
383 | .matches = is_kryo_midr, | |
384 | }, | |
38fd94b0 | 385 | #endif |
d9ff80f8 CC |
386 | #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 |
387 | { | |
388 | .desc = "Qualcomm Technologies Falkor erratum 1009", | |
389 | .capability = ARM64_WORKAROUND_REPEAT_TLBI, | |
390 | MIDR_RANGE(MIDR_QCOM_FALKOR_V1, | |
391 | MIDR_CPU_VAR_REV(0, 0), | |
392 | MIDR_CPU_VAR_REV(0, 0)), | |
393 | }, | |
eeb1efbc MZ |
394 | #endif |
395 | #ifdef CONFIG_ARM64_ERRATUM_858921 | |
396 | { | |
397 | /* Cortex-A73 all versions */ | |
398 | .desc = "ARM erratum 858921", | |
399 | .capability = ARM64_WORKAROUND_858921, | |
400 | MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), | |
401 | }, | |
aa6acde6 WD |
402 | #endif |
403 | #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR | |
404 | { | |
405 | .capability = ARM64_HARDEN_BRANCH_PREDICTOR, | |
406 | MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), | |
3a0a397f | 407 | .enable = enable_smccc_arch_workaround_1, |
aa6acde6 WD |
408 | }, |
409 | { | |
410 | .capability = ARM64_HARDEN_BRANCH_PREDICTOR, | |
411 | MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), | |
3a0a397f | 412 | .enable = enable_smccc_arch_workaround_1, |
aa6acde6 WD |
413 | }, |
414 | { | |
415 | .capability = ARM64_HARDEN_BRANCH_PREDICTOR, | |
416 | MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), | |
3a0a397f | 417 | .enable = enable_smccc_arch_workaround_1, |
aa6acde6 WD |
418 | }, |
419 | { | |
420 | .capability = ARM64_HARDEN_BRANCH_PREDICTOR, | |
421 | MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), | |
3a0a397f | 422 | .enable = enable_smccc_arch_workaround_1, |
aa6acde6 | 423 | }, |
ec82b567 SD |
424 | { |
425 | .capability = ARM64_HARDEN_BRANCH_PREDICTOR, | |
426 | MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1), | |
427 | .enable = qcom_enable_link_stack_sanitization, | |
428 | }, | |
429 | { | |
430 | .capability = ARM64_HARDEN_BP_POST_GUEST_EXIT, | |
431 | MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1), | |
432 | }, | |
16e574d7 SD |
433 | { |
434 | .capability = ARM64_HARDEN_BRANCH_PREDICTOR, | |
435 | MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR), | |
436 | .enable = qcom_enable_link_stack_sanitization, | |
437 | }, | |
438 | { | |
439 | .capability = ARM64_HARDEN_BP_POST_GUEST_EXIT, | |
440 | MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR), | |
441 | }, | |
f3d795d9 J |
442 | { |
443 | .capability = ARM64_HARDEN_BRANCH_PREDICTOR, | |
444 | MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), | |
3a0a397f | 445 | .enable = enable_smccc_arch_workaround_1, |
f3d795d9 J |
446 | }, |
447 | { | |
448 | .capability = ARM64_HARDEN_BRANCH_PREDICTOR, | |
449 | MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), | |
3a0a397f | 450 | .enable = enable_smccc_arch_workaround_1, |
f3d795d9 | 451 | }, |
d9ff80f8 | 452 | #endif |
5afaa1fc | 453 | { |
301bcfac | 454 | } |
e116a375 AP |
455 | }; |
456 | ||
6a6efbb4 SP |
457 | /* |
458 | * The CPU Errata work arounds are detected and applied at boot time | |
459 | * and the related information is freed soon after. If the new CPU requires | |
460 | * an errata not detected at boot, fail this CPU. | |
461 | */ | |
89ba2645 | 462 | void verify_local_cpu_errata_workarounds(void) |
6a6efbb4 SP |
463 | { |
464 | const struct arm64_cpu_capabilities *caps = arm64_errata; | |
465 | ||
55b35d07 SP |
466 | for (; caps->matches; caps++) { |
467 | if (cpus_have_cap(caps->capability)) { | |
468 | if (caps->enable) | |
469 | caps->enable((void *)caps); | |
470 | } else if (caps->matches(caps, SCOPE_LOCAL_CPU)) { | |
6a6efbb4 SP |
471 | pr_crit("CPU%d: Requires work around for %s, not detected" |
472 | " at boot time\n", | |
473 | smp_processor_id(), | |
474 | caps->desc ? : "an erratum"); | |
475 | cpu_die_early(); | |
476 | } | |
55b35d07 | 477 | } |
6a6efbb4 SP |
478 | } |
479 | ||
89ba2645 | 480 | void update_cpu_errata_workarounds(void) |
e116a375 | 481 | { |
ce8b602c | 482 | update_cpu_capabilities(arm64_errata, "enabling workaround for"); |
e116a375 | 483 | } |
8e231852 AP |
484 | |
485 | void __init enable_errata_workarounds(void) | |
486 | { | |
487 | enable_cpu_capabilities(arm64_errata); | |
488 | } |