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efi: vars: Move efivar caching layer into efivarfs
[linux-2.6-block.git] / arch / arm64 / kernel / cpu_errata.c
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caab277b 1// SPDX-License-Identifier: GPL-2.0-only
e116a375
AP		 2/*
3 * Contains CPU specific errata definitions
4 *
5 * Copyright (C) 2014 ARM Ltd.
e116a375
AP		 6 */
7
94a5d879 8#include <linux/arm-smccc.h>
e116a375 9#include <linux/types.h>
a111b7c0 10#include <linux/cpu.h>
e116a375
AP		 11#include <asm/cpu.h>
12#include <asm/cputype.h>
13#include <asm/cpufeature.h>
4db61fef 14#include <asm/kvm_asm.h>
93916beb 15#include <asm/smp_plat.h>
e116a375 16
301bcfac 17static bool __maybe_unused
92406f0c 18is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
301bcfac 19{
e8002e02
AB		 20 const struct arm64_midr_revidr *fix;
21 u32 midr = read_cpuid_id(), revidr;
22
92406f0c 23 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
1df31050 24 if (!is_midr_in_range(midr, &entry->midr_range))
e8002e02
AB		 25 return false;
26
27 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
28 revidr = read_cpuid(REVIDR_EL1);
29 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
30 if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
31 return false;
32
33 return true;
301bcfac
AP		 34}
35
be5b2998
SP		 36static bool __maybe_unused
37is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
38 int scope)
301bcfac 39{
92406f0c 40 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
be5b2998 41 return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
301bcfac
AP		 42}
43
bb487118
SB		 44static bool __maybe_unused
45is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
46{
47 u32 model;
48
49 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
50
51 model = read_cpuid_id();
52 model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
53 MIDR_ARCHITECTURE_MASK;
54
1df31050 55 return model == entry->midr_range.model;
bb487118
SB		 56}
57
116c81f4 58static bool
314d53d2
SP		 59has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
60 int scope)
116c81f4 61{
1602df02
SP		 62 u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
63 u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask;
64 u64 ctr_raw, ctr_real;
314d53d2 65
116c81f4 66 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
1602df02
SP		 67
68 /*
69 * We want to make sure that all the CPUs in the system expose
70 * a consistent CTR_EL0 to make sure that applications behaves
71 * correctly with migration.
72 *
73 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 :
74 *
75 * 1) It is safe if the system doesn't support IDC, as CPU anyway
76 * reports IDC = 0, consistent with the rest.
77 *
78 * 2) If the system has IDC, it is still safe as we trap CTR_EL0
79 * access on this CPU via the ARM64_HAS_CACHE_IDC capability.
80 *
81 * So, we need to make sure either the raw CTR_EL0 or the effective
82 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot.
83 */
84 ctr_raw = read_cpuid_cachetype() & mask;
85 ctr_real = read_cpuid_effective_cachetype() & mask;
86
87 return (ctr_real != sys) && (ctr_raw != sys);
116c81f4
SP		 88}
89
c0cda3b8 90static void
05460849 91cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap)
116c81f4 92{
4afe8e79 93 u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
05460849 94 bool enable_uct_trap = false;
4afe8e79
SP		 95
96 /* Trap CTR_EL0 access on this CPU, only if it has a mismatch */
97 if ((read_cpuid_cachetype() & mask) !=
98 (arm64_ftr_reg_ctrel0.sys_val & mask))
05460849
JM		 99 enable_uct_trap = true;
100
101 /* ... or if the system is affected by an erratum */
102 if (cap->capability == ARM64_WORKAROUND_1542419)
103 enable_uct_trap = true;
104
105 if (enable_uct_trap)
4afe8e79 106 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
116c81f4
SP		 107}
108
969f5ea6 109#ifdef CONFIG_ARM64_ERRATUM_1463225
969f5ea6
WD		 110static bool
111has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
112 int scope)
113{
a9e821b8 114 return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode();
969f5ea6
WD		 115}
116#endif
117
b8925ee2
WD		 118static void __maybe_unused
119cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
120{
121 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
122}
123
5e7951ce
SP		 124#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
125 .matches = is_affected_midr_range, \
1df31050 126 .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
5e7951ce
SP		 127
128#define CAP_MIDR_ALL_VERSIONS(model) \
129 .matches = is_affected_midr_range, \
1df31050 130 .midr_range = MIDR_ALL_VERSIONS(model)
06f1494f 131
e8002e02
AB		 132#define MIDR_FIXED(rev, revidr_mask) \
133 .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
134
5e7951ce
SP		 135#define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
136 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
137 CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
138
be5b2998
SP		 139#define CAP_MIDR_RANGE_LIST(list) \
140 .matches = is_affected_midr_range_list, \
141 .midr_range_list = list
142
5e7951ce
SP		 143/* Errata affecting a range of revisions of given model variant */
144#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
145 ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
146
147/* Errata affecting a single variant/revision of a model */
148#define ERRATA_MIDR_REV(model, var, rev) \
149 ERRATA_MIDR_RANGE(model, var, rev, var, rev)
150
151/* Errata affecting all variants/revisions of a given a model */
152#define ERRATA_MIDR_ALL_VERSIONS(model) \
153 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
154 CAP_MIDR_ALL_VERSIONS(model)
155
be5b2998
SP		 156/* Errata affecting a list of midr ranges, with same work around */
157#define ERRATA_MIDR_RANGE_LIST(midr_list) \
158 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
159 CAP_MIDR_RANGE_LIST(midr_list)
160
93916beb
MZ		 161static const __maybe_unused struct midr_range tx2_family_cpus[] = {
162 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
163 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
164 {},
165};
166
167static bool __maybe_unused
168needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,
169 int scope)
170{
171 int i;
172
173 if (!is_affected_midr_range_list(entry, scope) ||
174 !is_hyp_mode_available())
175 return false;
176
177 for_each_possible_cpu(i) {
178 if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0)
179 return true;
180 }
181
182 return false;
183}
184
05460849
JM		 185static bool __maybe_unused
186has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
187 int scope)
188{
189 u32 midr = read_cpuid_id();
190 bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT);
191 const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
192
193 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
194 return is_midr_in_range(midr, &range) && has_dic;
195}
8892b718 196
ce8c80c5 197#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
36c602dc 198static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
ce8c80c5 199#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
36c602dc
BA		 200 {
201 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)
202 },
203 {
204 .midr_range.model = MIDR_QCOM_KRYO,
205 .matches = is_kryo_midr,
206 },
ce8c80c5
CM		 207#endif
208#ifdef CONFIG_ARM64_ERRATUM_1286807
36c602dc
BA		 209 {
210 ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
51f559d6
S		 211 /* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */
212 ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),
36c602dc 213 },
ce8c80c5
CM		 214#endif
215 {},
216};
ce8c80c5
CM		 217#endif
218
24a147bc 219#ifdef CONFIG_CAVIUM_ERRATUM_23154
710c8d6c 220static const struct midr_range cavium_erratum_23154_cpus[] = {
24a147bc
LC		 221 MIDR_ALL_VERSIONS(MIDR_THUNDERX),
222 MIDR_ALL_VERSIONS(MIDR_THUNDERX_81XX),
223 MIDR_ALL_VERSIONS(MIDR_THUNDERX_83XX),
224 MIDR_ALL_VERSIONS(MIDR_OCTX2_98XX),
225 MIDR_ALL_VERSIONS(MIDR_OCTX2_96XX),
226 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XX),
227 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXN),
228 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXMM),
229 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXO),
f90205b9 230 {},
24a147bc
LC		 231};
232#endif
233
f58cdf7e 234#ifdef CONFIG_CAVIUM_ERRATUM_27456
b89d82ef 235const struct midr_range cavium_erratum_27456_cpus[] = {
f58cdf7e
SP		 236 /* Cavium ThunderX, T88 pass 1.x - 2.1 */
237 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1),
238 /* Cavium ThunderX, T81 pass 1.0 */
239 MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
240 {},
241};
242#endif
243
244#ifdef CONFIG_CAVIUM_ERRATUM_30115
245static const struct midr_range cavium_erratum_30115_cpus[] = {
246 /* Cavium ThunderX, T88 pass 1.x - 2.2 */
247 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2),
248 /* Cavium ThunderX, T81 pass 1.0 - 1.2 */
249 MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
250 /* Cavium ThunderX, T83 pass 1.0 */
251 MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
252 {},
253};
254#endif
255
a3dcea2c
SP		 256#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
257static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {
258 {
259 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
260 },
261 {
262 .midr_range.model = MIDR_QCOM_KRYO,
263 .matches = is_kryo_midr,
264 },
265 {},
266};
267#endif
268
c9460dcb
SP		 269#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
270static const struct midr_range workaround_clean_cache[] = {
c0a01b84
AP		 271#if defined(CONFIG_ARM64_ERRATUM_826319) || \
272 defined(CONFIG_ARM64_ERRATUM_827319) || \
273 defined(CONFIG_ARM64_ERRATUM_824069)
c9460dcb
SP		 274 /* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */
275 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
276#endif
277#ifdef CONFIG_ARM64_ERRATUM_819472
278 /* Cortex-A53 r0p[01] : ARM errata 819472 */
279 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
c0a01b84 280#endif
c9460dcb
SP		 281 {},
282};
283#endif
284
a5325089
MZ		 285#ifdef CONFIG_ARM64_ERRATUM_1418040
286/*
287 * - 1188873 affects r0p0 to r2p0
288 * - 1418040 affects r0p0 to r3p1
289 */
290static const struct midr_range erratum_1418040_list[] = {
291 /* Cortex-A76 r0p0 to r3p1 */
292 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
293 /* Neoverse-N1 r0p0 to r3p1 */
294 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),
a9e821b8
SPR		 295 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
296 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
6989303a
MZ		 297 {},
298};
299#endif
300
bfc97f9f
DB		 301#ifdef CONFIG_ARM64_ERRATUM_845719
302static const struct midr_range erratum_845719_list[] = {
303 /* Cortex-A53 r0p[01234] */
304 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
305 /* Brahma-B53 r0p[0] */
306 MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
23c21641
KD		 307 /* Kryo2XX Silver rAp4 */
308 MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4),
bfc97f9f
DB		 309 {},
310};
311#endif
312
1cf45b8f
FF		 313#ifdef CONFIG_ARM64_ERRATUM_843419
314static const struct arm64_cpu_capabilities erratum_843419_list[] = {
315 {
316 /* Cortex-A53 r0p[01234] */
317 .matches = is_affected_midr_range,
318 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
319 MIDR_FIXED(0x4, BIT(8)),
320 },
321 {
322 /* Brahma-B53 r0p[0] */
323 .matches = is_affected_midr_range,
324 ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
325 },
326 {},
327};
328#endif
329
02ab1f50
AS		 330#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
331static const struct midr_range erratum_speculative_at_list[] = {
e85d68fa
SP		 332#ifdef CONFIG_ARM64_ERRATUM_1165522
333 /* Cortex A76 r0p0 to r2p0 */
334 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
275fa0ea 335#endif
02ab1f50
AS		 336#ifdef CONFIG_ARM64_ERRATUM_1319367
337 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
338 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
339#endif
275fa0ea
SP		 340#ifdef CONFIG_ARM64_ERRATUM_1530923
341 /* Cortex A55 r0p0 to r2p0 */
342 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
9b23d95c
SPR		 343 /* Kryo4xx Silver (rdpe => r1p0) */
344 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
e85d68fa
SP		 345#endif
346 {},
347};
348#endif
349
a9e821b8
SPR		 350#ifdef CONFIG_ARM64_ERRATUM_1463225
351static const struct midr_range erratum_1463225[] = {
352 /* Cortex-A76 r0p0 - r3p1 */
353 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
354 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
355 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
09c717c9 356 {},
a9e821b8
SPR		 357};
358#endif
359
b9d216fc
SP		 360#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
361static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
362#ifdef CONFIG_ARM64_ERRATUM_2139208
363 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
364#endif
365#ifdef CONFIG_ARM64_ERRATUM_2119858
366 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
eb30d838 367 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
b9d216fc
SP		 368#endif
369 {},
370};
371#endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */
372
fa82d0b4
SP		 373#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
374static const struct midr_range tsb_flush_fail_cpus[] = {
375#ifdef CONFIG_ARM64_ERRATUM_2067961
376 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
377#endif
378#ifdef CONFIG_ARM64_ERRATUM_2054223
379 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
380#endif
381 {},
382};
383#endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */
384
8d81b2a3
SP		 385#ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
386static struct midr_range trbe_write_out_of_range_cpus[] = {
387#ifdef CONFIG_ARM64_ERRATUM_2253138
388 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
389#endif
390#ifdef CONFIG_ARM64_ERRATUM_2224489
391 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
eb30d838 392 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
8d81b2a3
SP		 393#endif
394 {},
395};
396#endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */
397
c9460dcb
SP		 398const struct arm64_cpu_capabilities arm64_errata[] = {
399#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
c0a01b84 400 {
357dd8a2 401 .desc = "ARM errata 826319, 827319, 824069, or 819472",
c0a01b84 402 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
c9460dcb 403 ERRATA_MIDR_RANGE_LIST(workaround_clean_cache),
c0cda3b8 404 .cpu_enable = cpu_enable_cache_maint_trap,
c0a01b84
AP		 405 },
406#endif
407#ifdef CONFIG_ARM64_ERRATUM_832075
301bcfac 408 {
5afaa1fc
AP		 409 /* Cortex-A57 r0p0 - r1p2 */
410 .desc = "ARM erratum 832075",
411 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
5e7951ce
SP		 412 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
413 0, 0,
414 1, 2),
5afaa1fc 415 },
905e8c5d 416#endif
498cd5c3
MZ		 417#ifdef CONFIG_ARM64_ERRATUM_834220
418 {
419 /* Cortex-A57 r0p0 - r1p2 */
420 .desc = "ARM erratum 834220",
421 .capability = ARM64_WORKAROUND_834220,
5e7951ce
SP		 422 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
423 0, 0,
424 1, 2),
498cd5c3
MZ		 425 },
426#endif
ca79acca
AB		 427#ifdef CONFIG_ARM64_ERRATUM_843419
428 {
ca79acca
AB		 429 .desc = "ARM erratum 843419",
430 .capability = ARM64_WORKAROUND_843419,
1cf45b8f
FF		 431 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
432 .matches = cpucap_multi_entry_cap_matches,
433 .match_list = erratum_843419_list,
498cd5c3
MZ		 434 },
435#endif
905e8c5d
WD		 436#ifdef CONFIG_ARM64_ERRATUM_845719
437 {
905e8c5d
WD		 438 .desc = "ARM erratum 845719",
439 .capability = ARM64_WORKAROUND_845719,
bfc97f9f 440 ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
905e8c5d 441 },
6d4e11c5
RR		 442#endif
443#ifdef CONFIG_CAVIUM_ERRATUM_23154
444 {
24a147bc 445 .desc = "Cavium errata 23154 and 38545",
6d4e11c5 446 .capability = ARM64_WORKAROUND_CAVIUM_23154,
24a147bc
LC		 447 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
448 ERRATA_MIDR_RANGE_LIST(cavium_erratum_23154_cpus),
6d4e11c5 449 },
104a0c02
AP		 450#endif
451#ifdef CONFIG_CAVIUM_ERRATUM_27456
452 {
47c459be
GK		 453 .desc = "Cavium erratum 27456",
454 .capability = ARM64_WORKAROUND_CAVIUM_27456,
f58cdf7e 455 ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus),
47c459be 456 },
690a3415
DD		 457#endif
458#ifdef CONFIG_CAVIUM_ERRATUM_30115
459 {
690a3415
DD		 460 .desc = "Cavium erratum 30115",
461 .capability = ARM64_WORKAROUND_CAVIUM_30115,
f58cdf7e 462 ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus),
690a3415 463 },
c0a01b84 464#endif
116c81f4 465 {
880f7cc4 466 .desc = "Mismatched cache type (CTR_EL0)",
314d53d2
SP		 467 .capability = ARM64_MISMATCHED_CACHE_TYPE,
468 .matches = has_mismatched_cache_type,
5b4747c5 469 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
c0cda3b8 470 .cpu_enable = cpu_enable_trap_ctr_access,
116c81f4 471 },
38fd94b0
CC		 472#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
473 {
a3dcea2c 474 .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
bb487118 475 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
d4af3c4b 476 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
1e013d06 477 .matches = cpucap_multi_entry_cap_matches,
a3dcea2c 478 .match_list = qcom_erratum_1003_list,
bb487118 479 },
38fd94b0 480#endif
ce8c80c5 481#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
d9ff80f8 482 {
357dd8a2 483 .desc = "Qualcomm erratum 1009, or ARM erratum 1286807",
d9ff80f8 484 .capability = ARM64_WORKAROUND_REPEAT_TLBI,
36c602dc
BA		 485 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
486 .matches = cpucap_multi_entry_cap_matches,
487 .match_list = arm64_repeat_tlbi_list,
d9ff80f8 488 },
eeb1efbc
MZ		 489#endif
490#ifdef CONFIG_ARM64_ERRATUM_858921
491 {
492 /* Cortex-A73 all versions */
493 .desc = "ARM erratum 858921",
494 .capability = ARM64_WORKAROUND_858921,
5e7951ce 495 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
eeb1efbc 496 },
aa6acde6 497#endif
aa6acde6 498 {
d4647f0a 499 .desc = "Spectre-v2",
688f1e4b 500 .capability = ARM64_SPECTRE_V2,
73f38166 501 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
d4647f0a
WD		 502 .matches = has_spectre_v2,
503 .cpu_enable = spectre_v2_enable_mitigation,
f3d795d9 504 },
a59a2edb 505#ifdef CONFIG_RANDOMIZE_BASE
4b472ffd 506 {
b881cdce 507 /* Must come after the Spectre-v2 entry */
c4792b6d
WD		 508 .desc = "Spectre-v3a",
509 .capability = ARM64_SPECTRE_V3A,
cd1f56b9
WD		 510 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
511 .matches = has_spectre_v3a,
c4792b6d 512 .cpu_enable = spectre_v3a_enable_mitigation,
4b472ffd 513 },
a725e3dd 514#endif
a725e3dd 515 {
c2876207 516 .desc = "Spectre-v4",
9b0955ba 517 .capability = ARM64_SPECTRE_V4,
a725e3dd 518 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
c2876207
WD		 519 .matches = has_spectre_v4,
520 .cpu_enable = spectre_v4_enable_mitigation,
a725e3dd 521 },
558c303c
JM		 522 {
523 .desc = "Spectre-BHB",
524 .capability = ARM64_SPECTRE_BHB,
525 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
526 .matches = is_spectre_bhb_affected,
527 .cpu_enable = spectre_bhb_enable_mitigation,
528 },
a5325089 529#ifdef CONFIG_ARM64_ERRATUM_1418040
95b861a4 530 {
a5325089
MZ		 531 .desc = "ARM erratum 1418040",
532 .capability = ARM64_WORKAROUND_1418040,
533 ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
ed888cb0
MZ		 534 /*
535 * We need to allow affected CPUs to come in late, but
536 * also need the non-affected CPUs to be able to come
537 * in at any point in time. Wonderful.
538 */
539 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
95b861a4 540 },
8b2cca9a 541#endif
02ab1f50 542#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
8b2cca9a 543 {
c350717e 544 .desc = "ARM errata 1165522, 1319367, or 1530923",
02ab1f50
AS		 545 .capability = ARM64_WORKAROUND_SPECULATIVE_AT,
546 ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list),
8b2cca9a 547 },
969f5ea6
WD		 548#endif
549#ifdef CONFIG_ARM64_ERRATUM_1463225
550 {
551 .desc = "ARM erratum 1463225",
552 .capability = ARM64_WORKAROUND_1463225,
553 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
554 .matches = has_cortex_a76_erratum_1463225,
a9e821b8 555 .midr_range_list = erratum_1463225,
969f5ea6 556 },
93916beb
MZ		 557#endif
558#ifdef CONFIG_CAVIUM_TX2_ERRATUM_219
559 {
560 .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)",
561 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM,
562 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
563 .matches = needs_tx2_tvm_workaround,
564 },
9405447e
MZ		 565 {
566 .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)",
567 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM,
568 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
569 },
6a036afb 570#endif
05460849
JM		 571#ifdef CONFIG_ARM64_ERRATUM_1542419
572 {
573 /* we depend on the firmware portion for correctness */
574 .desc = "ARM erratum 1542419 (kernel portion)",
575 .capability = ARM64_WORKAROUND_1542419,
576 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
577 .matches = has_neoverse_n1_erratum_1542419,
578 .cpu_enable = cpu_enable_trap_ctr_access,
579 },
96d389ca
RH		 580#endif
581#ifdef CONFIG_ARM64_ERRATUM_1508412
582 {
583 /* we depend on the firmware portion for correctness */
584 .desc = "ARM erratum 1508412 (kernel portion)",
585 .capability = ARM64_WORKAROUND_1508412,
586 ERRATA_MIDR_RANGE(MIDR_CORTEX_A77,
587 0, 0,
588 1, 0),
589 },
20109a85
RW		 590#endif
591#ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM
592 {
593 /* NVIDIA Carmel */
594 .desc = "NVIDIA Carmel CNP erratum",
595 .capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP,
596 ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
597 },
b9d216fc
SP		 598#endif
599#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
600 {
601 /*
602 * The erratum work around is handled within the TRBE
603 * driver and can be applied per-cpu. So, we can allow
604 * a late CPU to come online with this erratum.
605 */
606 .desc = "ARM erratum 2119858 or 2139208",
607 .capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE,
608 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
609 CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus),
610 },
fa82d0b4
SP		 611#endif
612#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
613 {
614 .desc = "ARM erratum 2067961 or 2054223",
615 .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE,
616 ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus),
617 },
8d81b2a3
SP		 618#endif
619#ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
620 {
621 .desc = "ARM erratum 2253138 or 2224489",
622 .capability = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE,
623 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
624 CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus),
625 },
607a9afa 626#endif
1dd498e5
JM		 627#ifdef CONFIG_ARM64_ERRATUM_2077057
628 {
629 .desc = "ARM erratum 2077057",
630 .capability = ARM64_WORKAROUND_2077057,
1dd498e5
JM		 631 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2),
632 },
633#endif
607a9afa
AK		 634#ifdef CONFIG_ARM64_ERRATUM_2064142
635 {
636 .desc = "ARM erratum 2064142",
637 .capability = ARM64_WORKAROUND_2064142,
638
639 /* Cortex-A510 r0p0 - r0p2 */
640 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
641 },
d9ff80f8 642#endif
3bd94a87
AK		 643#ifdef CONFIG_ARM64_ERRATUM_2038923
644 {
645 .desc = "ARM erratum 2038923",
646 .capability = ARM64_WORKAROUND_2038923,
647
648 /* Cortex-A510 r0p0 - r0p2 */
649 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
650 },
708e8af4
AK		 651#endif
652#ifdef CONFIG_ARM64_ERRATUM_1902691
653 {
654 .desc = "ARM erratum 1902691",
655 .capability = ARM64_WORKAROUND_1902691,
656
657 /* Cortex-A510 r0p0 - r0p1 */
658 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1)
659 },
d9ff80f8 660#endif
5afaa1fc 661 {
301bcfac 662 }
e116a375 663};
Linux 6.x block layer and io_uring tree(s)