Commit | Line | Data |
---|---|---|
0be7320a CM |
1 | /* |
2 | * Based on arch/arm/kernel/asm-offsets.c | |
3 | * | |
4 | * Copyright (C) 1995-2003 Russell King | |
5 | * 2001-2002 Keith Owens | |
6 | * Copyright (C) 2012 ARM Ltd. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
f5df2696 | 21 | #include <linux/arm_sdei.h> |
0be7320a CM |
22 | #include <linux/sched.h> |
23 | #include <linux/mm.h> | |
24 | #include <linux/dma-mapping.h> | |
c3eb5b14 | 25 | #include <linux/kvm_host.h> |
24534b35 | 26 | #include <linux/preempt.h> |
82869ac5 | 27 | #include <linux/suspend.h> |
116c81f4 | 28 | #include <asm/cpufeature.h> |
51a0048b | 29 | #include <asm/fixmap.h> |
0be7320a CM |
30 | #include <asm/thread_info.h> |
31 | #include <asm/memory.h> | |
95322526 LP |
32 | #include <asm/smp_plat.h> |
33 | #include <asm/suspend.h> | |
0be7320a CM |
34 | #include <asm/vdso_datapage.h> |
35 | #include <linux/kbuild.h> | |
14457459 | 36 | #include <linux/arm-smccc.h> |
0be7320a CM |
37 | |
38 | int main(void) | |
39 | { | |
40 | DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm)); | |
41 | BLANK(); | |
c02433dd MR |
42 | DEFINE(TSK_TI_FLAGS, offsetof(struct task_struct, thread_info.flags)); |
43 | DEFINE(TSK_TI_PREEMPT, offsetof(struct task_struct, thread_info.preempt_count)); | |
44 | DEFINE(TSK_TI_ADDR_LIMIT, offsetof(struct task_struct, thread_info.addr_limit)); | |
4b65a5db CM |
45 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
46 | DEFINE(TSK_TI_TTBR0, offsetof(struct task_struct, thread_info.ttbr0)); | |
47 | #endif | |
c02433dd | 48 | DEFINE(TSK_STACK, offsetof(struct task_struct, stack)); |
0a1213fa AB |
49 | #ifdef CONFIG_STACKPROTECTOR |
50 | DEFINE(TSK_STACK_CANARY, offsetof(struct task_struct, stack_canary)); | |
51 | #endif | |
0be7320a CM |
52 | BLANK(); |
53 | DEFINE(THREAD_CPU_CONTEXT, offsetof(struct task_struct, thread.cpu_context)); | |
54 | BLANK(); | |
55 | DEFINE(S_X0, offsetof(struct pt_regs, regs[0])); | |
56 | DEFINE(S_X1, offsetof(struct pt_regs, regs[1])); | |
57 | DEFINE(S_X2, offsetof(struct pt_regs, regs[2])); | |
58 | DEFINE(S_X3, offsetof(struct pt_regs, regs[3])); | |
59 | DEFINE(S_X4, offsetof(struct pt_regs, regs[4])); | |
60 | DEFINE(S_X5, offsetof(struct pt_regs, regs[5])); | |
61 | DEFINE(S_X6, offsetof(struct pt_regs, regs[6])); | |
62 | DEFINE(S_X7, offsetof(struct pt_regs, regs[7])); | |
da6a9125 WC |
63 | DEFINE(S_X8, offsetof(struct pt_regs, regs[8])); |
64 | DEFINE(S_X10, offsetof(struct pt_regs, regs[10])); | |
65 | DEFINE(S_X12, offsetof(struct pt_regs, regs[12])); | |
66 | DEFINE(S_X14, offsetof(struct pt_regs, regs[14])); | |
67 | DEFINE(S_X16, offsetof(struct pt_regs, regs[16])); | |
68 | DEFINE(S_X18, offsetof(struct pt_regs, regs[18])); | |
69 | DEFINE(S_X20, offsetof(struct pt_regs, regs[20])); | |
70 | DEFINE(S_X22, offsetof(struct pt_regs, regs[22])); | |
71 | DEFINE(S_X24, offsetof(struct pt_regs, regs[24])); | |
72 | DEFINE(S_X26, offsetof(struct pt_regs, regs[26])); | |
73 | DEFINE(S_X28, offsetof(struct pt_regs, regs[28])); | |
0be7320a CM |
74 | DEFINE(S_LR, offsetof(struct pt_regs, regs[30])); |
75 | DEFINE(S_SP, offsetof(struct pt_regs, sp)); | |
76 | #ifdef CONFIG_COMPAT | |
77 | DEFINE(S_COMPAT_SP, offsetof(struct pt_regs, compat_sp)); | |
78 | #endif | |
79 | DEFINE(S_PSTATE, offsetof(struct pt_regs, pstate)); | |
80 | DEFINE(S_PC, offsetof(struct pt_regs, pc)); | |
81 | DEFINE(S_ORIG_X0, offsetof(struct pt_regs, orig_x0)); | |
82 | DEFINE(S_SYSCALLNO, offsetof(struct pt_regs, syscallno)); | |
e19a6ee2 | 83 | DEFINE(S_ORIG_ADDR_LIMIT, offsetof(struct pt_regs, orig_addr_limit)); |
73267498 | 84 | DEFINE(S_STACKFRAME, offsetof(struct pt_regs, stackframe)); |
0be7320a CM |
85 | DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs)); |
86 | BLANK(); | |
5aec715d | 87 | DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id.counter)); |
0be7320a CM |
88 | BLANK(); |
89 | DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm)); | |
90 | DEFINE(VMA_VM_FLAGS, offsetof(struct vm_area_struct, vm_flags)); | |
91 | BLANK(); | |
92 | DEFINE(VM_EXEC, VM_EXEC); | |
93 | BLANK(); | |
94 | DEFINE(PAGE_SZ, PAGE_SIZE); | |
95 | BLANK(); | |
0be7320a CM |
96 | DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL); |
97 | DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE); | |
98 | DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE); | |
99 | BLANK(); | |
24534b35 AB |
100 | DEFINE(PREEMPT_DISABLE_OFFSET, PREEMPT_DISABLE_OFFSET); |
101 | BLANK(); | |
0be7320a CM |
102 | DEFINE(CLOCK_REALTIME, CLOCK_REALTIME); |
103 | DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC); | |
49eea433 | 104 | DEFINE(CLOCK_MONOTONIC_RAW, CLOCK_MONOTONIC_RAW); |
0be7320a CM |
105 | DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC); |
106 | DEFINE(CLOCK_REALTIME_COARSE, CLOCK_REALTIME_COARSE); | |
107 | DEFINE(CLOCK_MONOTONIC_COARSE,CLOCK_MONOTONIC_COARSE); | |
108 | DEFINE(CLOCK_COARSE_RES, LOW_RES_NSEC); | |
109 | DEFINE(NSEC_PER_SEC, NSEC_PER_SEC); | |
110 | BLANK(); | |
111 | DEFINE(VDSO_CS_CYCLE_LAST, offsetof(struct vdso_data, cs_cycle_last)); | |
49eea433 KB |
112 | DEFINE(VDSO_RAW_TIME_SEC, offsetof(struct vdso_data, raw_time_sec)); |
113 | DEFINE(VDSO_RAW_TIME_NSEC, offsetof(struct vdso_data, raw_time_nsec)); | |
0be7320a CM |
114 | DEFINE(VDSO_XTIME_CLK_SEC, offsetof(struct vdso_data, xtime_clock_sec)); |
115 | DEFINE(VDSO_XTIME_CLK_NSEC, offsetof(struct vdso_data, xtime_clock_nsec)); | |
116 | DEFINE(VDSO_XTIME_CRS_SEC, offsetof(struct vdso_data, xtime_coarse_sec)); | |
117 | DEFINE(VDSO_XTIME_CRS_NSEC, offsetof(struct vdso_data, xtime_coarse_nsec)); | |
118 | DEFINE(VDSO_WTM_CLK_SEC, offsetof(struct vdso_data, wtm_clock_sec)); | |
119 | DEFINE(VDSO_WTM_CLK_NSEC, offsetof(struct vdso_data, wtm_clock_nsec)); | |
120 | DEFINE(VDSO_TB_SEQ_COUNT, offsetof(struct vdso_data, tb_seq_count)); | |
49eea433 KB |
121 | DEFINE(VDSO_CS_MONO_MULT, offsetof(struct vdso_data, cs_mono_mult)); |
122 | DEFINE(VDSO_CS_RAW_MULT, offsetof(struct vdso_data, cs_raw_mult)); | |
0be7320a CM |
123 | DEFINE(VDSO_CS_SHIFT, offsetof(struct vdso_data, cs_shift)); |
124 | DEFINE(VDSO_TZ_MINWEST, offsetof(struct vdso_data, tz_minuteswest)); | |
125 | DEFINE(VDSO_TZ_DSTTIME, offsetof(struct vdso_data, tz_dsttime)); | |
126 | DEFINE(VDSO_USE_SYSCALL, offsetof(struct vdso_data, use_syscall)); | |
127 | BLANK(); | |
128 | DEFINE(TVAL_TV_SEC, offsetof(struct timeval, tv_sec)); | |
129 | DEFINE(TVAL_TV_USEC, offsetof(struct timeval, tv_usec)); | |
130 | DEFINE(TSPEC_TV_SEC, offsetof(struct timespec, tv_sec)); | |
131 | DEFINE(TSPEC_TV_NSEC, offsetof(struct timespec, tv_nsec)); | |
132 | BLANK(); | |
133 | DEFINE(TZ_MINWEST, offsetof(struct timezone, tz_minuteswest)); | |
134 | DEFINE(TZ_DSTTIME, offsetof(struct timezone, tz_dsttime)); | |
55c7401d | 135 | BLANK(); |
bb905274 | 136 | DEFINE(CPU_BOOT_STACK, offsetof(struct secondary_data, stack)); |
c02433dd | 137 | DEFINE(CPU_BOOT_TASK, offsetof(struct secondary_data, task)); |
bb905274 | 138 | BLANK(); |
55c7401d MZ |
139 | #ifdef CONFIG_KVM_ARM_HOST |
140 | DEFINE(VCPU_CONTEXT, offsetof(struct kvm_vcpu, arch.ctxt)); | |
0067df41 | 141 | DEFINE(VCPU_FAULT_DISR, offsetof(struct kvm_vcpu, arch.fault.disr_el1)); |
b4f18c06 | 142 | DEFINE(VCPU_WORKAROUND_FLAGS, offsetof(struct kvm_vcpu, arch.workaround_flags)); |
55c7401d MZ |
143 | DEFINE(CPU_GP_REGS, offsetof(struct kvm_cpu_context, gp_regs)); |
144 | DEFINE(CPU_USER_PT_REGS, offsetof(struct kvm_regs, regs)); | |
145 | DEFINE(CPU_FP_REGS, offsetof(struct kvm_regs, fp_regs)); | |
9d8415d6 | 146 | DEFINE(VCPU_FPEXC32_EL2, offsetof(struct kvm_vcpu, arch.ctxt.sys_regs[FPEXC32_EL2])); |
55c7401d | 147 | DEFINE(VCPU_HOST_CONTEXT, offsetof(struct kvm_vcpu, arch.host_cpu_context)); |
4464e210 | 148 | DEFINE(HOST_CONTEXT_VCPU, offsetof(struct kvm_cpu_context, __hyp_running_vcpu)); |
95322526 | 149 | #endif |
af3cfdbf | 150 | #ifdef CONFIG_CPU_PM |
95322526 LP |
151 | DEFINE(CPU_SUSPEND_SZ, sizeof(struct cpu_suspend_ctx)); |
152 | DEFINE(CPU_CTX_SP, offsetof(struct cpu_suspend_ctx, sp)); | |
153 | DEFINE(MPIDR_HASH_MASK, offsetof(struct mpidr_hash, mask)); | |
154 | DEFINE(MPIDR_HASH_SHIFTS, offsetof(struct mpidr_hash, shift_aff)); | |
adc9b2df JM |
155 | DEFINE(SLEEP_STACK_DATA_SYSTEM_REGS, offsetof(struct sleep_stack_data, system_regs)); |
156 | DEFINE(SLEEP_STACK_DATA_CALLEE_REGS, offsetof(struct sleep_stack_data, callee_saved_regs)); | |
55c7401d | 157 | #endif |
680a0873 AG |
158 | DEFINE(ARM_SMCCC_RES_X0_OFFS, offsetof(struct arm_smccc_res, a0)); |
159 | DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2)); | |
160 | DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id)); | |
161 | DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state)); | |
82869ac5 JM |
162 | BLANK(); |
163 | DEFINE(HIBERN_PBE_ORIG, offsetof(struct pbe, orig_address)); | |
164 | DEFINE(HIBERN_PBE_ADDR, offsetof(struct pbe, address)); | |
165 | DEFINE(HIBERN_PBE_NEXT, offsetof(struct pbe, next)); | |
116c81f4 | 166 | DEFINE(ARM64_FTR_SYSVAL, offsetof(struct arm64_ftr_reg, sys_val)); |
51a0048b WD |
167 | BLANK(); |
168 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 | |
169 | DEFINE(TRAMP_VALIAS, TRAMP_VALIAS); | |
f5df2696 JM |
170 | #endif |
171 | #ifdef CONFIG_ARM_SDE_INTERFACE | |
172 | DEFINE(SDEI_EVENT_INTREGS, offsetof(struct sdei_registered_event, interrupted_regs)); | |
173 | DEFINE(SDEI_EVENT_PRIORITY, offsetof(struct sdei_registered_event, priority)); | |
51a0048b | 174 | #endif |
0be7320a CM |
175 | return 0; |
176 | } |