Commit | Line | Data |
---|---|---|
37655163 AS |
1 | /* |
2 | * ARM64 Specific Low-Level ACPI Boot Support | |
3 | * | |
4 | * Copyright (C) 2013-2014, Linaro Ltd. | |
5 | * Author: Al Stone <al.stone@linaro.org> | |
6 | * Author: Graeme Gregory <graeme.gregory@linaro.org> | |
7 | * Author: Hanjun Guo <hanjun.guo@linaro.org> | |
8 | * Author: Tomasz Nowicki <tomasz.nowicki@linaro.org> | |
9 | * Author: Naresh Bhat <naresh.bhat@linaro.org> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #define pr_fmt(fmt) "ACPI: " fmt | |
17 | ||
18 | #include <linux/acpi.h> | |
19 | #include <linux/bootmem.h> | |
20 | #include <linux/cpumask.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/irq.h> | |
23 | #include <linux/irqdomain.h> | |
24 | #include <linux/memblock.h> | |
b10d79f7 | 25 | #include <linux/of_fdt.h> |
37655163 AS |
26 | #include <linux/smp.h> |
27 | ||
fccb9a81 HG |
28 | #include <asm/cputype.h> |
29 | #include <asm/cpu_ops.h> | |
30 | #include <asm/smp_plat.h> | |
31 | ||
b10d79f7 AS |
32 | int acpi_noirq = 1; /* skip ACPI IRQ initialization */ |
33 | int acpi_disabled = 1; | |
37655163 AS |
34 | EXPORT_SYMBOL(acpi_disabled); |
35 | ||
b10d79f7 | 36 | int acpi_pci_disabled = 1; /* skip ACPI PCI scan and IRQ initialization */ |
37655163 AS |
37 | EXPORT_SYMBOL(acpi_pci_disabled); |
38 | ||
fccb9a81 HG |
39 | /* Processors with enabled flag and sane MPIDR */ |
40 | static int enabled_cpus; | |
41 | ||
42 | /* Boot CPU is valid or not in MADT */ | |
43 | static bool bootcpu_valid __initdata; | |
44 | ||
b10d79f7 AS |
45 | static bool param_acpi_off __initdata; |
46 | static bool param_acpi_force __initdata; | |
47 | ||
48 | static int __init parse_acpi(char *arg) | |
49 | { | |
50 | if (!arg) | |
51 | return -EINVAL; | |
52 | ||
53 | /* "acpi=off" disables both ACPI table parsing and interpreter */ | |
54 | if (strcmp(arg, "off") == 0) | |
55 | param_acpi_off = true; | |
56 | else if (strcmp(arg, "force") == 0) /* force ACPI to be enabled */ | |
57 | param_acpi_force = true; | |
58 | else | |
59 | return -EINVAL; /* Core will print when we return error */ | |
60 | ||
61 | return 0; | |
62 | } | |
63 | early_param("acpi", parse_acpi); | |
64 | ||
65 | static int __init dt_scan_depth1_nodes(unsigned long node, | |
66 | const char *uname, int depth, | |
67 | void *data) | |
68 | { | |
69 | /* | |
70 | * Return 1 as soon as we encounter a node at depth 1 that is | |
71 | * not the /chosen node. | |
72 | */ | |
73 | if (depth == 1 && (strcmp(uname, "chosen") != 0)) | |
74 | return 1; | |
75 | return 0; | |
76 | } | |
77 | ||
fbe61ec7 HG |
78 | /* |
79 | * Since we're on ARM, the default interrupt routing model | |
80 | * clearly has to be GIC. | |
81 | */ | |
82 | enum acpi_irq_model_id acpi_irq_model = ACPI_IRQ_MODEL_GIC; | |
83 | ||
37655163 AS |
84 | /* |
85 | * __acpi_map_table() will be called before page_init(), so early_ioremap() | |
86 | * or early_memremap() should be called here to for ACPI table mapping. | |
87 | */ | |
88 | char *__init __acpi_map_table(unsigned long phys, unsigned long size) | |
89 | { | |
90 | if (!size) | |
91 | return NULL; | |
92 | ||
93 | return early_memremap(phys, size); | |
94 | } | |
95 | ||
96 | void __init __acpi_unmap_table(char *map, unsigned long size) | |
97 | { | |
98 | if (!map || !size) | |
99 | return; | |
100 | ||
101 | early_memunmap(map, size); | |
102 | } | |
103 | ||
fccb9a81 HG |
104 | /** |
105 | * acpi_map_gic_cpu_interface - generates a logical cpu number | |
106 | * and map to MPIDR represented by GICC structure | |
107 | * @mpidr: CPU's hardware id to register, MPIDR represented in MADT | |
108 | * @enabled: this cpu is enabled or not | |
109 | * | |
110 | * Returns the logical cpu number which maps to MPIDR | |
111 | */ | |
112 | static int __init acpi_map_gic_cpu_interface(u64 mpidr, u8 enabled) | |
113 | { | |
114 | int i; | |
115 | ||
116 | if (mpidr == INVALID_HWID) { | |
117 | pr_info("Skip MADT cpu entry with invalid MPIDR\n"); | |
118 | return -EINVAL; | |
119 | } | |
120 | ||
121 | total_cpus++; | |
122 | if (!enabled) | |
123 | return -EINVAL; | |
124 | ||
125 | if (enabled_cpus >= NR_CPUS) { | |
126 | pr_warn("NR_CPUS limit of %d reached, Processor %d/0x%llx ignored.\n", | |
127 | NR_CPUS, total_cpus, mpidr); | |
128 | return -EINVAL; | |
129 | } | |
130 | ||
131 | /* Check if GICC structure of boot CPU is available in the MADT */ | |
132 | if (cpu_logical_map(0) == mpidr) { | |
133 | if (bootcpu_valid) { | |
134 | pr_err("Firmware bug, duplicate CPU MPIDR: 0x%llx in MADT\n", | |
135 | mpidr); | |
136 | return -EINVAL; | |
137 | } | |
138 | ||
139 | bootcpu_valid = true; | |
140 | } | |
141 | ||
142 | /* | |
143 | * Duplicate MPIDRs are a recipe for disaster. Scan | |
144 | * all initialized entries and check for | |
145 | * duplicates. If any is found just ignore the CPU. | |
146 | */ | |
147 | for (i = 1; i < enabled_cpus; i++) { | |
148 | if (cpu_logical_map(i) == mpidr) { | |
149 | pr_err("Firmware bug, duplicate CPU MPIDR: 0x%llx in MADT\n", | |
150 | mpidr); | |
151 | return -EINVAL; | |
152 | } | |
153 | } | |
154 | ||
155 | if (!acpi_psci_present()) | |
156 | return -EOPNOTSUPP; | |
157 | ||
158 | cpu_ops[enabled_cpus] = cpu_get_ops("psci"); | |
159 | /* CPU 0 was already initialized */ | |
160 | if (enabled_cpus) { | |
161 | if (!cpu_ops[enabled_cpus]) | |
162 | return -EINVAL; | |
163 | ||
164 | if (cpu_ops[enabled_cpus]->cpu_init(NULL, enabled_cpus)) | |
165 | return -EOPNOTSUPP; | |
166 | ||
167 | /* map the logical cpu id to cpu MPIDR */ | |
168 | cpu_logical_map(enabled_cpus) = mpidr; | |
169 | } | |
170 | ||
171 | enabled_cpus++; | |
172 | return enabled_cpus; | |
173 | } | |
174 | ||
175 | static int __init | |
176 | acpi_parse_gic_cpu_interface(struct acpi_subtable_header *header, | |
177 | const unsigned long end) | |
178 | { | |
179 | struct acpi_madt_generic_interrupt *processor; | |
180 | ||
181 | processor = (struct acpi_madt_generic_interrupt *)header; | |
182 | ||
183 | if (BAD_MADT_ENTRY(processor, end)) | |
184 | return -EINVAL; | |
185 | ||
186 | acpi_table_print_madt_entry(header); | |
187 | ||
188 | acpi_map_gic_cpu_interface(processor->arm_mpidr & MPIDR_HWID_BITMASK, | |
189 | processor->flags & ACPI_MADT_ENABLED); | |
190 | ||
191 | return 0; | |
192 | } | |
193 | ||
194 | /* Parse GIC cpu interface entries in MADT for SMP init */ | |
195 | void __init acpi_init_cpus(void) | |
196 | { | |
197 | int count, i; | |
198 | ||
199 | /* | |
200 | * do a partial walk of MADT to determine how many CPUs | |
201 | * we have including disabled CPUs, and get information | |
202 | * we need for SMP init | |
203 | */ | |
204 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
205 | acpi_parse_gic_cpu_interface, 0); | |
206 | ||
207 | if (!count) { | |
208 | pr_err("No GIC CPU interface entries present\n"); | |
209 | return; | |
210 | } else if (count < 0) { | |
211 | pr_err("Error parsing GIC CPU interface entry\n"); | |
212 | return; | |
213 | } | |
214 | ||
215 | if (!bootcpu_valid) { | |
216 | pr_err("MADT missing boot CPU MPIDR, not enabling secondaries\n"); | |
217 | return; | |
218 | } | |
219 | ||
220 | for (i = 0; i < enabled_cpus; i++) | |
221 | set_cpu_possible(i, true); | |
222 | ||
223 | /* Make boot-up look pretty */ | |
224 | pr_info("%d CPUs enabled, %d CPUs total\n", enabled_cpus, total_cpus); | |
225 | } | |
226 | ||
fbe61ec7 HG |
227 | int acpi_gsi_to_irq(u32 gsi, unsigned int *irq) |
228 | { | |
229 | *irq = irq_find_mapping(NULL, gsi); | |
230 | ||
231 | return 0; | |
232 | } | |
233 | EXPORT_SYMBOL_GPL(acpi_gsi_to_irq); | |
234 | ||
235 | /* | |
236 | * success: return IRQ number (>0) | |
237 | * failure: return =< 0 | |
238 | */ | |
239 | int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity) | |
240 | { | |
241 | unsigned int irq; | |
242 | unsigned int irq_type; | |
243 | ||
244 | /* | |
245 | * ACPI have no bindings to indicate SPI or PPI, so we | |
246 | * use different mappings from DT in ACPI. | |
247 | * | |
248 | * For FDT | |
249 | * PPI interrupt: in the range [0, 15]; | |
250 | * SPI interrupt: in the range [0, 987]; | |
251 | * | |
252 | * For ACPI, GSI should be unique so using | |
253 | * the hwirq directly for the mapping: | |
254 | * PPI interrupt: in the range [16, 31]; | |
255 | * SPI interrupt: in the range [32, 1019]; | |
256 | */ | |
257 | ||
258 | if (trigger == ACPI_EDGE_SENSITIVE && | |
259 | polarity == ACPI_ACTIVE_LOW) | |
260 | irq_type = IRQ_TYPE_EDGE_FALLING; | |
261 | else if (trigger == ACPI_EDGE_SENSITIVE && | |
262 | polarity == ACPI_ACTIVE_HIGH) | |
263 | irq_type = IRQ_TYPE_EDGE_RISING; | |
264 | else if (trigger == ACPI_LEVEL_SENSITIVE && | |
265 | polarity == ACPI_ACTIVE_LOW) | |
266 | irq_type = IRQ_TYPE_LEVEL_LOW; | |
267 | else if (trigger == ACPI_LEVEL_SENSITIVE && | |
268 | polarity == ACPI_ACTIVE_HIGH) | |
269 | irq_type = IRQ_TYPE_LEVEL_HIGH; | |
270 | else | |
271 | irq_type = IRQ_TYPE_NONE; | |
272 | ||
273 | /* | |
274 | * Since only one GIC is supported in ACPI 5.0, we can | |
275 | * create mapping refer to the default domain | |
276 | */ | |
277 | irq = irq_create_mapping(NULL, gsi); | |
278 | if (!irq) | |
279 | return irq; | |
280 | ||
281 | /* Set irq type if specified and different than the current one */ | |
282 | if (irq_type != IRQ_TYPE_NONE && | |
283 | irq_type != irq_get_trigger_type(irq)) | |
284 | irq_set_irq_type(irq, irq_type); | |
285 | return irq; | |
286 | } | |
287 | EXPORT_SYMBOL_GPL(acpi_register_gsi); | |
288 | ||
289 | void acpi_unregister_gsi(u32 gsi) | |
290 | { | |
291 | } | |
292 | EXPORT_SYMBOL_GPL(acpi_unregister_gsi); | |
293 | ||
37655163 AS |
294 | static int __init acpi_parse_fadt(struct acpi_table_header *table) |
295 | { | |
296 | struct acpi_table_fadt *fadt = (struct acpi_table_fadt *)table; | |
297 | ||
298 | /* | |
299 | * Revision in table header is the FADT Major revision, and there | |
300 | * is a minor revision of FADT which was introduced by ACPI 5.1, | |
301 | * we only deal with ACPI 5.1 or newer revision to get GIC and SMP | |
302 | * boot protocol configuration data, or we will disable ACPI. | |
303 | */ | |
304 | if (table->revision > 5 || | |
fccb9a81 | 305 | (table->revision == 5 && fadt->minor_revision >= 1)) { |
6933de0c AS |
306 | if (!acpi_gbl_reduced_hardware) { |
307 | pr_err("Not hardware reduced ACPI mode, will not be supported\n"); | |
308 | goto disable_acpi; | |
309 | } | |
310 | ||
fccb9a81 HG |
311 | /* |
312 | * ACPI 5.1 only has two explicit methods to boot up SMP, | |
313 | * PSCI and Parking protocol, but the Parking protocol is | |
314 | * only specified for ARMv7 now, so make PSCI as the only | |
315 | * way for the SMP boot protocol before some updates for | |
316 | * the Parking protocol spec. | |
317 | */ | |
318 | if (acpi_psci_present()) | |
319 | return 0; | |
320 | ||
321 | pr_warn("No PSCI support, will not bring up secondary CPUs\n"); | |
322 | return -EOPNOTSUPP; | |
323 | } | |
37655163 AS |
324 | |
325 | pr_warn("Unsupported FADT revision %d.%d, should be 5.1+, will disable ACPI\n", | |
326 | table->revision, fadt->minor_revision); | |
37655163 | 327 | |
6933de0c AS |
328 | disable_acpi: |
329 | disable_acpi(); | |
37655163 AS |
330 | return -EINVAL; |
331 | } | |
332 | ||
333 | /* | |
334 | * acpi_boot_table_init() called from setup_arch(), always. | |
335 | * 1. find RSDP and get its address, and then find XSDT | |
336 | * 2. extract all tables and checksums them all | |
337 | * 3. check ACPI FADT revision | |
338 | * | |
339 | * We can parse ACPI boot-time tables such as MADT after | |
340 | * this function is called. | |
341 | */ | |
342 | void __init acpi_boot_table_init(void) | |
343 | { | |
b10d79f7 AS |
344 | /* |
345 | * Enable ACPI instead of device tree unless | |
346 | * - ACPI has been disabled explicitly (acpi=off), or | |
347 | * - the device tree is not empty (it has more than just a /chosen node) | |
348 | * and ACPI has not been force enabled (acpi=force) | |
349 | */ | |
350 | if (param_acpi_off || | |
351 | (!param_acpi_force && of_scan_flat_dt(dt_scan_depth1_nodes, NULL))) | |
37655163 AS |
352 | return; |
353 | ||
b10d79f7 AS |
354 | enable_acpi(); |
355 | ||
37655163 AS |
356 | /* Initialize the ACPI boot-time table parser. */ |
357 | if (acpi_table_init()) { | |
358 | disable_acpi(); | |
359 | return; | |
360 | } | |
361 | ||
362 | if (acpi_table_parse(ACPI_SIG_FADT, acpi_parse_fadt)) { | |
363 | /* disable ACPI if no FADT is found */ | |
364 | disable_acpi(); | |
365 | pr_err("Can't find FADT\n"); | |
366 | } | |
367 | } | |
d60fc389 TN |
368 | |
369 | void __init acpi_gic_init(void) | |
370 | { | |
371 | struct acpi_table_header *table; | |
372 | acpi_status status; | |
373 | acpi_size tbl_size; | |
374 | int err; | |
375 | ||
376 | if (acpi_disabled) | |
377 | return; | |
378 | ||
379 | status = acpi_get_table_with_size(ACPI_SIG_MADT, 0, &table, &tbl_size); | |
380 | if (ACPI_FAILURE(status)) { | |
381 | const char *msg = acpi_format_exception(status); | |
382 | ||
383 | pr_err("Failed to get MADT table, %s\n", msg); | |
384 | return; | |
385 | } | |
386 | ||
387 | err = gic_v2_acpi_init(table); | |
388 | if (err) | |
389 | pr_err("Failed to initialize GIC IRQ controller"); | |
390 | ||
391 | early_acpi_os_unmap_memory((char *)table, tbl_size); | |
392 | } |