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caab277b | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
f35a9205 MZ |
2 | /* |
3 | * Copyright (C) 2012 ARM Ltd. | |
4 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
f35a9205 MZ |
5 | */ |
6 | ||
7 | #ifndef __ASM__VIRT_H | |
8 | #define __ASM__VIRT_H | |
9 | ||
ad72e59f | 10 | /* |
810c86ee MZ |
11 | * The arm64 hcall implementation uses x0 to specify the hcall |
12 | * number. A value less than HVC_STUB_HCALL_NR indicates a special | |
13 | * hcall, such as set vector. Any other value is handled in a | |
14 | * hypervisor specific way. | |
15 | * | |
16 | * The hypercall is allowed to clobber any of the caller-saved | |
17 | * registers (x0-x18), so it is advisable to use it through the | |
18 | * indirection of a function call (as implemented in hyp-stub.S). | |
ad72e59f GL |
19 | */ |
20 | ||
ad72e59f GL |
21 | /* |
22 | * HVC_SET_VECTORS - Set the value of the vbar_el2 register. | |
23 | * | |
24 | * @x1: Physical address of the new vector table. | |
25 | */ | |
0b51c547 | 26 | #define HVC_SET_VECTORS 0 |
ad72e59f | 27 | |
f9076ecf GL |
28 | /* |
29 | * HVC_SOFT_RESTART - CPU soft reset, used by the cpu_soft_restart routine. | |
30 | */ | |
0b51c547 | 31 | #define HVC_SOFT_RESTART 1 |
f9076ecf | 32 | |
fd0e0c61 MZ |
33 | /* |
34 | * HVC_RESET_VECTORS - Restore the vectors to the original HYP stubs | |
35 | */ | |
0b51c547 | 36 | #define HVC_RESET_VECTORS 2 |
fd0e0c61 MZ |
37 | |
38 | /* Max number of HYP stub hypercalls */ | |
0b51c547 | 39 | #define HVC_STUB_HCALL_NR 3 |
fd0e0c61 | 40 | |
4993fdcf MZ |
41 | /* Error returned when an invalid stub number is passed into x0 */ |
42 | #define HVC_STUB_ERR 0xbadca11 | |
43 | ||
828e9834 ML |
44 | #define BOOT_CPU_MODE_EL1 (0xe11) |
45 | #define BOOT_CPU_MODE_EL2 (0xe12) | |
f35a9205 MZ |
46 | |
47 | #ifndef __ASSEMBLY__ | |
48 | ||
82deae0f | 49 | #include <asm/ptrace.h> |
ee78fdc7 | 50 | #include <asm/sections.h> |
1f3d8699 | 51 | #include <asm/sysreg.h> |
488f94d7 | 52 | #include <asm/cpufeature.h> |
82deae0f | 53 | |
f35a9205 MZ |
54 | /* |
55 | * __boot_cpu_mode records what mode CPUs were booted in. | |
56 | * A correctly-implemented bootloader must start all CPUs in the same mode: | |
57 | * In this case, both 32bit halves of __boot_cpu_mode will contain the | |
58 | * same value (either 0 if booted in EL1, BOOT_CPU_MODE_EL2 if booted in EL2). | |
59 | * | |
60 | * Should the bootloader fail to do this, the two values will be different. | |
61 | * This allows the kernel to flag an error when the secondaries have come up. | |
62 | */ | |
63 | extern u32 __boot_cpu_mode[2]; | |
64 | ||
712c6ff4 | 65 | void __hyp_set_vectors(phys_addr_t phys_vector_base); |
fd0e0c61 | 66 | void __hyp_reset_vectors(void); |
712c6ff4 | 67 | |
f35a9205 MZ |
68 | /* Reports the availability of HYP mode */ |
69 | static inline bool is_hyp_mode_available(void) | |
70 | { | |
71 | return (__boot_cpu_mode[0] == BOOT_CPU_MODE_EL2 && | |
72 | __boot_cpu_mode[1] == BOOT_CPU_MODE_EL2); | |
73 | } | |
74 | ||
75 | /* Check if the bootloader has booted CPUs in different modes */ | |
76 | static inline bool is_hyp_mode_mismatched(void) | |
77 | { | |
78 | return __boot_cpu_mode[0] != __boot_cpu_mode[1]; | |
79 | } | |
80 | ||
82deae0f MZ |
81 | static inline bool is_kernel_in_hyp_mode(void) |
82 | { | |
1f3d8699 | 83 | return read_sysreg(CurrentEL) == CurrentEL_EL2; |
82deae0f MZ |
84 | } |
85 | ||
5c37f1ae | 86 | static __always_inline bool has_vhe(void) |
488f94d7 JL |
87 | { |
88 | if (cpus_have_const_cap(ARM64_HAS_VIRT_HOST_EXTN)) | |
89 | return true; | |
90 | ||
91 | return false; | |
92 | } | |
93 | ||
f35a9205 MZ |
94 | #endif /* __ASSEMBLY__ */ |
95 | ||
96 | #endif /* ! __ASM__VIRT_H */ |