projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| caab277b | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 72c58395 CM |
2 | /* |
| 3 | * Macros for accessing system registers with older binutils. | |
| 4 | * | |
| 5 | * Copyright (C) 2014 ARM Ltd. | |
| 6 | * Author: Catalin Marinas <catalin.marinas@arm.com> | |
| 72c58395 CM |
7 | */ |
| 8 | ||
| 9 | #ifndef __ASM_SYSREG_H | |
| 10 | #define __ASM_SYSREG_H | |
| 11 | ||
| fe6ba88b | 12 | #include <linux/bits.h> |
| 3600c2fd | 13 | #include <linux/stringify.h> |
| 82868247 | 14 | #include <linux/kasan-tags.h> |
| 3600c2fd | 15 | |
| 8ed1b498 MR |
16 | #include <asm/gpr-num.h> |
| 17 | ||
| 9ded63aa SP |
18 | /* |
| 19 | * ARMv8 ARM reserves the following encoding for system registers: | |
| 20 | * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", | |
| 21 | * C5.2, version:ARM DDI 0487A.f) | |
| 22 | * [20-19] : Op0 | |
| 23 | * [18-16] : Op1 | |
| 24 | * [15-12] : CRn | |
| 25 | * [11-8] : CRm | |
| 26 | * [7-5] : Op2 | |
| 27 | */ | |
| c9ee0f98 SP |
28 | #define Op0_shift 19 |
| 29 | #define Op0_mask 0x3 | |
| 30 | #define Op1_shift 16 | |
| 31 | #define Op1_mask 0x7 | |
| 32 | #define CRn_shift 12 | |
| 33 | #define CRn_mask 0xf | |
| 34 | #define CRm_shift 8 | |
| 35 | #define CRm_mask 0xf | |
| 36 | #define Op2_shift 5 | |
| 37 | #define Op2_mask 0x7 | |
| 38 | ||
| 72c58395 | 39 | #define sys_reg(op0, op1, crn, crm, op2) \ |
| c9ee0f98 SP |
40 | (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ |
| 41 | ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ | |
| 42 | ((op2) << Op2_shift)) | |
| 43 | ||
| 4dc52925 MR |
44 | #define sys_insn sys_reg |
| 45 | ||
| c9ee0f98 SP |
46 | #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) |
| 47 | #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) | |
| 48 | #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) | |
| 49 | #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) | |
| 50 | #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) | |
| 72c58395 | 51 | |
| cd9e1927 MZ |
52 | #ifndef CONFIG_BROKEN_GAS_INST |
| 53 | ||
| bca8f17f | 54 | #ifdef __ASSEMBLY__ |
| c9a4ef66 FS |
55 | // The space separator is omitted so that __emit_inst(x) can be parsed as |
| 56 | // either an assembler directive or an assembler macro argument. | |
| 57 | #define __emit_inst(x) .inst(x) | |
| bca8f17f MZ |
58 | #else |
| 59 | #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" | |
| 60 | #endif | |
| 61 | ||
| cd9e1927 MZ |
62 | #else /* CONFIG_BROKEN_GAS_INST */ |
| 63 | ||
| 64 | #ifndef CONFIG_CPU_BIG_ENDIAN | |
| 65 | #define __INSTR_BSWAP(x) (x) | |
| 66 | #else /* CONFIG_CPU_BIG_ENDIAN */ | |
| 67 | #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ | |
| 68 | (((x) << 8) & 0x00ff0000) | \ | |
| 69 | (((x) >> 8) & 0x0000ff00) | \ | |
| 70 | (((x) >> 24) & 0x000000ff)) | |
| 71 | #endif /* CONFIG_CPU_BIG_ENDIAN */ | |
| 72 | ||
| 73 | #ifdef __ASSEMBLY__ | |
| 74 | #define __emit_inst(x) .long __INSTR_BSWAP(x) | |
| 75 | #else /* __ASSEMBLY__ */ | |
| 76 | #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" | |
| 77 | #endif /* __ASSEMBLY__ */ | |
| 78 | ||
| 79 | #endif /* CONFIG_BROKEN_GAS_INST */ | |
| 80 | ||
| 74e24828 SP |
81 | /* |
| 82 | * Instructions for modifying PSTATE fields. | |
| 83 | * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints, | |
| 84 | * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions | |
| 85 | * for accessing PSTATE fields have the following encoding: | |
| 86 | * Op0 = 0, CRn = 4 | |
| 87 | * Op1, Op2 encodes the PSTATE field modified and defines the constraints. | |
| 88 | * CRm = Imm4 for the instruction. | |
| 89 | * Rt = 0x1f | |
| 90 | */ | |
| 91 | #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) | |
| 92 | #define PSTATE_Imm_shift CRm_shift | |
| 01ab991f | 93 | #define SET_PSTATE(x, r) __emit_inst(0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift)) |
| 74e24828 SP |
94 | |
| 95 | #define PSTATE_PAN pstate_field(0, 4) | |
| 96 | #define PSTATE_UAO pstate_field(0, 3) | |
| 97 | #define PSTATE_SSBS pstate_field(3, 1) | |
| 01ab991f | 98 | #define PSTATE_DIT pstate_field(3, 2) |
| c058b1c4 | 99 | #define PSTATE_TCO pstate_field(3, 4) |
| 74e24828 | 100 | |
| 01ab991f AB |
101 | #define SET_PSTATE_PAN(x) SET_PSTATE((x), PAN) |
| 102 | #define SET_PSTATE_UAO(x) SET_PSTATE((x), UAO) | |
| 103 | #define SET_PSTATE_SSBS(x) SET_PSTATE((x), SSBS) | |
| 104 | #define SET_PSTATE_DIT(x) SET_PSTATE((x), DIT) | |
| 105 | #define SET_PSTATE_TCO(x) SET_PSTATE((x), TCO) | |
| 47863d41 | 106 | |
| 515d5c8a MR |
107 | #define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x)) |
| 108 | #define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x)) | |
| 109 | #define set_pstate_ssbs(x) asm volatile(SET_PSTATE_SSBS(x)) | |
| 01ab991f | 110 | #define set_pstate_dit(x) asm volatile(SET_PSTATE_DIT(x)) |
| 515d5c8a | 111 | |
| bd4fb6d2 WD |
112 | #define __SYS_BARRIER_INSN(CRm, op2, Rt) \ |
| 113 | __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f)) | |
| 114 | ||
| 115 | #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31) | |
| 116 | ||
| 4dc52925 | 117 | #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) |
| 8d0f019e MZ |
118 | #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4) |
| 119 | #define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6) | |
| 4dc52925 | 120 | #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) |
| 8d0f019e MZ |
121 | #define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4) |
| 122 | #define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6) | |
| 4dc52925 | 123 | #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) |
| 8d0f019e MZ |
124 | #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4) |
| 125 | #define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6) | |
| 4dc52925 | 126 | |
| 21f74a51 MZ |
127 | #define SYS_IC_IALLUIS sys_insn(1, 0, 7, 1, 0) |
| 128 | #define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0) | |
| 129 | #define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1) | |
| 130 | ||
| 131 | #define SYS_DC_IVAC sys_insn(1, 0, 7, 6, 1) | |
| 132 | #define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3) | |
| 133 | #define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5) | |
| 134 | ||
| 135 | #define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1) | |
| 136 | #define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3) | |
| 137 | #define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5) | |
| 138 | ||
| 139 | #define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1) | |
| 140 | ||
| 141 | #define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1) | |
| 142 | #define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3) | |
| 143 | #define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5) | |
| 144 | ||
| 145 | #define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1) | |
| 146 | #define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3) | |
| 147 | #define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5) | |
| 148 | ||
| 149 | #define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1) | |
| 150 | #define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3) | |
| 151 | #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5) | |
| 152 | ||
| 6ddea24d MZ |
153 | /* Data cache zero operations */ |
| 154 | #define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1) | |
| 155 | #define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3) | |
| 156 | #define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4) | |
| 157 | ||
| c07d8017 MB |
158 | /* |
| 159 | * Automatically generated definitions for system registers, the | |
| 160 | * manual encodings below are in the process of being converted to | |
| 161 | * come from here. The header relies on the definition of sys_reg() | |
| 162 | * earlier in this file. | |
| 163 | */ | |
| 164 | #include "asm/sysreg-defs.h" | |
| 165 | ||
| eeb2d87e WD |
166 | /* |
| 167 | * System registers, organised loosely by encoding but grouped together | |
| 168 | * where the architected name contains an index. e.g. ID_MMFR<n>_EL1. | |
| 169 | */ | |
| b4adc83b MB |
170 | #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3) |
| 171 | #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3) | |
| 172 | #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3) | |
| 173 | ||
| d9801207 MR |
174 | #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) |
| 175 | #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) | |
| 176 | #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) | |
| 177 | #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) | |
| 178 | #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) | |
| f24adc65 | 179 | |
| d9801207 | 180 | #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) |
| 187de7c2 MB |
181 | #define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0)) |
| 182 | #define OSLSR_EL1_OSLM_NI 0 | |
| 183 | #define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3) | |
| 184 | #define OSLSR_EL1_OSLK BIT(1) | |
| d42e2671 | 185 | |
| d9801207 MR |
186 | #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) |
| 187 | #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) | |
| 188 | #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) | |
| 189 | #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6) | |
| 190 | #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6) | |
| 191 | #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0) | |
| 192 | #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0) | |
| 193 | #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0) | |
| 194 | #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) | |
| 195 | #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) | |
| 196 | ||
| 57596c8f MZ |
197 | #define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0)) |
| 198 | #define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0) | |
| 199 | #define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1)) | |
| 200 | #define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1) | |
| 201 | #define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2)) | |
| 202 | #define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2) | |
| 203 | #define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2) | |
| 204 | ||
| 205 | #define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0) | |
| 206 | #define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1) | |
| 207 | #define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0) | |
| 208 | ||
| 209 | #define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3) | |
| 210 | #define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3))) | |
| 211 | #define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3))) | |
| 212 | #define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6) | |
| 213 | #define SYS_TRCAUXCTLR sys_reg(2, 1, 0, 6, 0) | |
| 214 | #define SYS_TRCBBCTLR sys_reg(2, 1, 0, 15, 0) | |
| 215 | #define SYS_TRCCCCTLR sys_reg(2, 1, 0, 14, 0) | |
| 216 | #define SYS_TRCCIDCCTLR0 sys_reg(2, 1, 3, 0, 2) | |
| 217 | #define SYS_TRCCIDCCTLR1 sys_reg(2, 1, 3, 1, 2) | |
| 218 | #define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0) | |
| 219 | #define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6) | |
| 220 | #define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6) | |
| 221 | #define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5) | |
| 222 | #define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5) | |
| 223 | #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5) | |
| 224 | #define SYS_TRCCONFIGR sys_reg(2, 1, 0, 4, 0) | |
| 225 | #define SYS_TRCDEVARCH sys_reg(2, 1, 7, 15, 6) | |
| 226 | #define SYS_TRCDEVID sys_reg(2, 1, 7, 2, 7) | |
| 227 | #define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0) | |
| 228 | #define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0) | |
| 229 | #define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4) | |
| 230 | #define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7) | |
| 231 | #define SYS_TRCIDR10 sys_reg(2, 1, 0, 2, 6) | |
| 232 | #define SYS_TRCIDR11 sys_reg(2, 1, 0, 3, 6) | |
| 233 | #define SYS_TRCIDR12 sys_reg(2, 1, 0, 4, 6) | |
| 234 | #define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6) | |
| 235 | #define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7) | |
| 236 | #define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7) | |
| 237 | #define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7) | |
| 238 | #define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7) | |
| 239 | #define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7) | |
| 240 | #define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7) | |
| 241 | #define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7) | |
| 242 | #define SYS_TRCIDR8 sys_reg(2, 1, 0, 0, 6) | |
| 243 | #define SYS_TRCIDR9 sys_reg(2, 1, 0, 1, 6) | |
| 244 | #define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7) | |
| 245 | #define SYS_TRCITEEDCR sys_reg(2, 1, 0, 2, 1) | |
| 246 | #define SYS_TRCOSLSR sys_reg(2, 1, 1, 1, 4) | |
| 247 | #define SYS_TRCPRGCTLR sys_reg(2, 1, 0, 1, 0) | |
| 248 | #define SYS_TRCQCTLR sys_reg(2, 1, 0, 1, 1) | |
| 249 | #define SYS_TRCRSCTLR(m) sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4))) | |
| 250 | #define SYS_TRCRSR sys_reg(2, 1, 0, 10, 0) | |
| 251 | #define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4) | |
| 252 | #define SYS_TRCSEQRSTEVR sys_reg(2, 1, 0, 6, 4) | |
| 253 | #define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4) | |
| 254 | #define SYS_TRCSSCCR(m) sys_reg(2, 1, 1, (m & 7), 2) | |
| 255 | #define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2) | |
| 256 | #define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3) | |
| 257 | #define SYS_TRCSTALLCTLR sys_reg(2, 1, 0, 11, 0) | |
| 258 | #define SYS_TRCSTATR sys_reg(2, 1, 0, 3, 0) | |
| 259 | #define SYS_TRCSYNCPR sys_reg(2, 1, 0, 13, 0) | |
| 260 | #define SYS_TRCTRACEIDR sys_reg(2, 1, 0, 0, 1) | |
| 261 | #define SYS_TRCTSCTLR sys_reg(2, 1, 0, 12, 0) | |
| 262 | #define SYS_TRCVICTLR sys_reg(2, 1, 0, 0, 2) | |
| 263 | #define SYS_TRCVIIECTLR sys_reg(2, 1, 0, 1, 2) | |
| 264 | #define SYS_TRCVIPCSSCTLR sys_reg(2, 1, 0, 3, 2) | |
| 265 | #define SYS_TRCVISSCTLR sys_reg(2, 1, 0, 2, 2) | |
| 266 | #define SYS_TRCVMIDCCTLR0 sys_reg(2, 1, 3, 2, 2) | |
| 267 | #define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2) | |
| 268 | #define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1) | |
| 269 | ||
| 270 | /* ETM */ | |
| 271 | #define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4) | |
| 272 | ||
| 41f6c934 ML |
273 | #define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0) |
| 274 | ||
| 3c739b57 SP |
275 | #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) |
| 276 | #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) | |
| 277 | #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) | |
| 278 | ||
| 14ae7518 | 279 | #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) |
| c058b1c4 VF |
280 | #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) |
| 281 | #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) | |
| 14ae7518 | 282 | |
| 4b6929f5 | 283 | #define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) |
| 67236564 | 284 | |
| 14ae7518 MR |
285 | #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) |
| 286 | ||
| aa6eece8 MR |
287 | #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) |
| 288 | #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1) | |
| 289 | #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2) | |
| 290 | #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3) | |
| 291 | ||
| 292 | #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0) | |
| 293 | #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1) | |
| 294 | #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2) | |
| 295 | #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3) | |
| 296 | ||
| 297 | #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0) | |
| 298 | #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1) | |
| 299 | ||
| fdec2a9e DM |
300 | #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0) |
| 301 | #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1) | |
| 302 | ||
| 0e9884fe MR |
303 | #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) |
| 304 | ||
| 14ae7518 MR |
305 | #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) |
| 306 | #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) | |
| 307 | #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) | |
| 558daf69 DG |
308 | |
| 309 | #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0) | |
| 310 | #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1) | |
| 311 | #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0) | |
| 312 | #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1) | |
| 313 | #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2) | |
| 314 | #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3) | |
| 464f2164 MZ |
315 | #define SYS_ERXPFGF_EL1 sys_reg(3, 0, 5, 4, 4) |
| 316 | #define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5) | |
| 317 | #define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6) | |
| 558daf69 DG |
318 | #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0) |
| 319 | #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1) | |
| 464f2164 MZ |
320 | #define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2) |
| 321 | #define SYS_ERXMISC3_EL1 sys_reg(3, 0, 5, 5, 3) | |
| c058b1c4 VF |
322 | #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0) |
| 323 | #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1) | |
| 558daf69 | 324 | |
| 14ae7518 MR |
325 | #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) |
| 326 | ||
| 29a0f5ad | 327 | #define SYS_PAR_EL1_F BIT(0) |
| e8620cff WD |
328 | #define SYS_PAR_EL1_FST GENMASK(6, 1) |
| 329 | ||
| a173c390 | 330 | /*** Statistical Profiling Extension ***/ |
| e080477a | 331 | #define PMSEVFR_EL1_RES0_IMP \ |
| 4a669e24 WL |
332 | (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\ |
| 333 | BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) | |
| e080477a RH |
334 | #define PMSEVFR_EL1_RES0_V1P1 \ |
| 335 | (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) | |
| 4998897b RH |
336 | #define PMSEVFR_EL1_RES0_V1P2 \ |
| 337 | (PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6)) | |
| a173c390 | 338 | |
| a173c390 | 339 | /* Buffer error reporting */ |
| 95693604 RH |
340 | #define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT |
| 341 | #define PMBSR_EL1_FAULT_FSC_MASK PMBSR_EL1_MSS_MASK | |
| 342 | ||
| 343 | #define PMBSR_EL1_BUF_BSC_SHIFT PMBSR_EL1_MSS_SHIFT | |
| 344 | #define PMBSR_EL1_BUF_BSC_MASK PMBSR_EL1_MSS_MASK | |
| a173c390 | 345 | |
| c759ec85 | 346 | #define PMBSR_EL1_BUF_BSC_FULL 0x1UL |
| a173c390 WD |
347 | |
| 348 | /*** End of Statistical Profiling Extension ***/ | |
| 349 | ||
| 7bb94882 AK |
350 | #define TRBSR_EL1_BSC_MASK GENMASK(5, 0) |
| 351 | #define TRBSR_EL1_BSC_SHIFT 0 | |
| 3f9b72f6 | 352 | |
| c7a3c61f MR |
353 | #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) |
| 354 | #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) | |
| 355 | ||
| f5be3a61 SZ |
356 | #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6) |
| 357 | ||
| 14ae7518 MR |
358 | #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) |
| 359 | #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) | |
| 360 | ||
| 361 | #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) | |
| 68ddbf09 | 362 | #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) |
| 14ae7518 | 363 | |
| eab0b2dc MZ |
364 | #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) |
| 365 | #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1) | |
| 366 | #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) | |
| 423de85a | 367 | #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) |
| eab0b2dc | 368 | #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) |
| 0959db6c MR |
369 | #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) |
| 370 | #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) | |
| 371 | #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) | |
| 372 | #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) | |
| f9e7449c | 373 | #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) |
| 0959db6c MR |
374 | #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) |
| 375 | #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) | |
| 376 | #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) | |
| 377 | #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) | |
| 0e9884fe | 378 | #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) |
| 43515894 | 379 | #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) |
| 0e9884fe | 380 | #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) |
| 03bd646d MZ |
381 | #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6) |
| 382 | #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7) | |
| 0e9884fe MR |
383 | #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) |
| 384 | #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) | |
| 2724c11a | 385 | #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2) |
| 0e9884fe MR |
386 | #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) |
| 387 | #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) | |
| 388 | #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) | |
| 21bc5281 MR |
389 | #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) |
| 390 | #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) | |
| 0e9884fe | 391 | |
| 484f8682 MZ |
392 | #define SYS_ACCDATA_EL1 sys_reg(3, 0, 13, 0, 5) |
| 393 | ||
| 14ae7518 MR |
394 | #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) |
| 395 | ||
| 14ae7518 MR |
396 | #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) |
| 397 | ||
| 1a50ec0b RH |
398 | #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) |
| 399 | #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1) | |
| 400 | ||
| c7a3c61f MR |
401 | #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0) |
| 402 | #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) | |
| 403 | #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) | |
| 404 | #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) | |
| 405 | #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) | |
| 406 | #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5) | |
| 407 | #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) | |
| 408 | #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) | |
| 409 | #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) | |
| 410 | #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1) | |
| 411 | #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2) | |
| 412 | #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0) | |
| 413 | #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3) | |
| 338d4f49 | 414 | |
| 14ae7518 MR |
415 | #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) |
| 416 | #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) | |
| b4adc83b | 417 | #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5) |
| 14ae7518 | 418 | |
| ed4ffaf4 MZ |
419 | #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7) |
| 420 | ||
| 2c9d45b4 IV |
421 | /* Definitions for system register interface to AMU for ARMv8.4 onwards */ |
| 422 | #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2)) | |
| 423 | #define SYS_AMCR_EL0 SYS_AM_EL0(2, 0) | |
| 424 | #define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1) | |
| 425 | #define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2) | |
| 426 | #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3) | |
| 427 | #define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4) | |
| 428 | #define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5) | |
| 429 | #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0) | |
| 430 | #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1) | |
| 431 | ||
| 432 | /* | |
| 433 | * Group 0 of activity monitors (architected): | |
| 434 | * op0 op1 CRn CRm op2 | |
| 435 | * Counter: 11 011 1101 010:n<3> n<2:0> | |
| 436 | * Type: 11 011 1101 011:n<3> n<2:0> | |
| 437 | * n: 0-15 | |
| 438 | * | |
| 439 | * Group 1 of activity monitors (auxiliary): | |
| 440 | * op0 op1 CRn CRm op2 | |
| 441 | * Counter: 11 011 1101 110:n<3> n<2:0> | |
| 442 | * Type: 11 011 1101 111:n<3> n<2:0> | |
| 443 | * n: 0-15 | |
| 444 | */ | |
| 445 | ||
| 446 | #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7) | |
| 493cf9b7 | 447 | #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7) |
| 2c9d45b4 | 448 | #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7) |
| 493cf9b7 | 449 | #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7) |
| 2c9d45b4 IV |
450 | |
| 451 | /* AMU v1: Fixed (architecturally defined) activity monitors */ | |
| 452 | #define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0) | |
| 453 | #define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1) | |
| 454 | #define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2) | |
| 455 | #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3) | |
| 456 | ||
| 47863d41 | 457 | #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) |
| 338d4f49 | 458 | |
| c605ee24 | 459 | #define SYS_CNTPCT_EL0 sys_reg(3, 3, 14, 0, 1) |
| 9ee840a9 MZ |
460 | #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5) |
| 461 | #define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6) | |
| 462 | ||
| 147a70ce MR |
463 | #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) |
| 464 | #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) | |
| 465 | #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) | |
| 466 | ||
| fdec2a9e DM |
467 | #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1) |
| 468 | #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2) | |
| 469 | ||
| 84135d3d AP |
470 | #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0) |
| 471 | #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1) | |
| c605ee24 | 472 | #define SYS_AARCH32_CNTPCT sys_reg(0, 0, 0, 14, 0) |
| 84135d3d | 473 | #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0) |
| a6610435 | 474 | #define SYS_AARCH32_CNTPCTSS sys_reg(0, 8, 0, 14, 0) |
| 84135d3d | 475 | |
| c7a3c61f MR |
476 | #define __PMEV_op2(n) ((n) & 0x7) |
| 477 | #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) | |
| 478 | #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) | |
| 479 | #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) | |
| 480 | #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) | |
| 481 | ||
| fdec2a9e | 482 | #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7) |
| c7a3c61f | 483 | |
| 6ff9dc23 JL |
484 | #define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0) |
| 485 | #define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5) | |
| 486 | ||
| 29052f1b | 487 | #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) |
| 6ff9dc23 | 488 | #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1) |
| 41f6c934 | 489 | #define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3) |
| 6ff9dc23 JL |
490 | #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0) |
| 491 | #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1) | |
| 492 | #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2) | |
| 493 | #define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3) | |
| 6ff9dc23 JL |
494 | #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7) |
| 495 | ||
| 496 | #define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0) | |
| 497 | #define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1) | |
| 498 | #define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2) | |
| 499 | #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) | |
| 500 | #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) | |
| 501 | ||
| 4b6929f5 | 502 | #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) |
| 41f6c934 | 503 | #define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0) |
| 31c00d2a | 504 | #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) |
| fdec2a9e DM |
505 | #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) |
| 506 | #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) | |
| 6ff9dc23 | 507 | #define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0) |
| 3f7915cc MZ |
508 | #define SYS_SPSR_irq sys_reg(3, 4, 4, 3, 0) |
| 509 | #define SYS_SPSR_abt sys_reg(3, 4, 4, 3, 1) | |
| 510 | #define SYS_SPSR_und sys_reg(3, 4, 4, 3, 2) | |
| 511 | #define SYS_SPSR_fiq sys_reg(3, 4, 4, 3, 3) | |
| 14ae7518 | 512 | #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) |
| 6ff9dc23 JL |
513 | #define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0) |
| 514 | #define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1) | |
| fdec2a9e | 515 | #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0) |
| 4715c14b | 516 | #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) |
| 14ae7518 | 517 | #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) |
| c058b1c4 | 518 | #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0) |
| 14ae7518 | 519 | |
| 6ff9dc23 JL |
520 | #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0) |
| 521 | #define SYS_HPFAR_EL2 sys_reg(3, 4, 6, 0, 4) | |
| 522 | ||
| 523 | #define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0) | |
| 524 | #define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0) | |
| 41f6c934 ML |
525 | #define SYS_MPAMHCR_EL2 sys_reg(3, 4, 10, 4, 0) |
| 526 | #define SYS_MPAMVPMV_EL2 sys_reg(3, 4, 10, 4, 1) | |
| 527 | #define SYS_MPAM2_EL2 sys_reg(3, 4, 10, 5, 0) | |
| 528 | #define __SYS__MPAMVPMx_EL2(x) sys_reg(3, 4, 10, 6, x) | |
| 529 | #define SYS_MPAMVPM0_EL2 __SYS__MPAMVPMx_EL2(0) | |
| 530 | #define SYS_MPAMVPM1_EL2 __SYS__MPAMVPMx_EL2(1) | |
| 531 | #define SYS_MPAMVPM2_EL2 __SYS__MPAMVPMx_EL2(2) | |
| 532 | #define SYS_MPAMVPM3_EL2 __SYS__MPAMVPMx_EL2(3) | |
| 533 | #define SYS_MPAMVPM4_EL2 __SYS__MPAMVPMx_EL2(4) | |
| 534 | #define SYS_MPAMVPM5_EL2 __SYS__MPAMVPMx_EL2(5) | |
| 535 | #define SYS_MPAMVPM6_EL2 __SYS__MPAMVPMx_EL2(6) | |
| 536 | #define SYS_MPAMVPM7_EL2 __SYS__MPAMVPMx_EL2(7) | |
| 6ff9dc23 JL |
537 | |
| 538 | #define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0) | |
| 539 | #define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1) | |
| 540 | #define SYS_RMR_EL2 sys_reg(3, 4, 12, 0, 2) | |
| 541 | #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) | |
| 0e9884fe MR |
542 | #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) |
| 543 | #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) | |
| 544 | #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) | |
| 545 | #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) | |
| 546 | #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) | |
| 547 | ||
| 548 | #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) | |
| 549 | #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0) | |
| 550 | #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1) | |
| 551 | #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2) | |
| 552 | #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3) | |
| 553 | ||
| 554 | #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) | |
| 555 | #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) | |
| 556 | #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) | |
| 557 | #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) | |
| 558 | #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) | |
| 559 | #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) | |
| b98c079b | 560 | #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5) |
| 0e9884fe MR |
561 | #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) |
| 562 | ||
| 563 | #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) | |
| 564 | #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) | |
| 565 | #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1) | |
| 566 | #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2) | |
| 567 | #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3) | |
| 568 | #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4) | |
| 569 | #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5) | |
| 570 | #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6) | |
| 571 | #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7) | |
| 572 | ||
| 573 | #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) | |
| 574 | #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0) | |
| 575 | #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1) | |
| 576 | #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) | |
| 577 | #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) | |
| 578 | #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) | |
| 579 | #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) | |
| 580 | #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) | |
| 581 | #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) | |
| 338d4f49 | 582 | |
| 6ff9dc23 JL |
583 | #define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1) |
| 584 | #define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2) | |
| 41f6c934 ML |
585 | #define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7) |
| 586 | ||
| 587 | #define __AMEV_op2(m) (m & 0x7) | |
| 588 | #define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3)) | |
| 589 | #define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m)) | |
| 590 | #define SYS_AMEVCNTVOFF0n_EL2(m) __SYS__AMEVCNTVOFF0n_EL2(m) | |
| 591 | #define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m)) | |
| 592 | #define SYS_AMEVCNTVOFF1n_EL2(m) __SYS__AMEVCNTVOFF1n_EL2(m) | |
| 6ff9dc23 JL |
593 | |
| 594 | #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3) | |
| 595 | #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0) | |
| 41f6c934 ML |
596 | #define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0) |
| 597 | #define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1) | |
| 598 | #define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2) | |
| 599 | #define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0) | |
| 600 | #define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1) | |
| 601 | #define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2) | |
| 6ff9dc23 | 602 | |
| 73433762 | 603 | /* VHE encodings for architectural EL0/1 system registers */ |
| d5cb781b | 604 | #define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0) |
| fdec2a9e | 605 | #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0) |
| d5cb781b ML |
606 | #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2) |
| 607 | #define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3) | |
| 608 | #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0) | |
| 609 | #define SYS_TRFCR_EL12 sys_reg(3, 5, 1, 2, 1) | |
| 610 | #define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6) | |
| fdec2a9e DM |
611 | #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0) |
| 612 | #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1) | |
| 613 | #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2) | |
| d5cb781b | 614 | #define SYS_TCR2_EL12 sys_reg(3, 5, 2, 0, 3) |
| fdec2a9e DM |
615 | #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0) |
| 616 | #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1) | |
| 617 | #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0) | |
| 618 | #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) | |
| 619 | #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0) | |
| c058b1c4 | 620 | #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0) |
| d5cb781b ML |
621 | #define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0) |
| 622 | #define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0) | |
| fdec2a9e DM |
623 | #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0) |
| 624 | #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0) | |
| 625 | #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0) | |
| d5cb781b ML |
626 | #define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1) |
| 627 | #define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7) | |
| fdec2a9e DM |
628 | #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0) |
| 629 | #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0) | |
| 630 | #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1) | |
| 631 | #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2) | |
| 632 | #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0) | |
| 633 | #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1) | |
| 634 | #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2) | |
| 73433762 | 635 | |
| 6ff9dc23 JL |
636 | #define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0) |
| 637 | ||
| 2b97411f MZ |
638 | /* AT instructions */ |
| 639 | #define AT_Op0 1 | |
| 640 | #define AT_CRn 7 | |
| 641 | ||
| 642 | #define OP_AT_S1E1R sys_insn(AT_Op0, 0, AT_CRn, 8, 0) | |
| 643 | #define OP_AT_S1E1W sys_insn(AT_Op0, 0, AT_CRn, 8, 1) | |
| 644 | #define OP_AT_S1E0R sys_insn(AT_Op0, 0, AT_CRn, 8, 2) | |
| 645 | #define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3) | |
| 646 | #define OP_AT_S1E1RP sys_insn(AT_Op0, 0, AT_CRn, 9, 0) | |
| 647 | #define OP_AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1) | |
| 4ebee8ce | 648 | #define OP_AT_S1E1A sys_insn(AT_Op0, 0, AT_CRn, 9, 2) |
| 2b97411f MZ |
649 | #define OP_AT_S1E2R sys_insn(AT_Op0, 4, AT_CRn, 8, 0) |
| 650 | #define OP_AT_S1E2W sys_insn(AT_Op0, 4, AT_CRn, 8, 1) | |
| 651 | #define OP_AT_S12E1R sys_insn(AT_Op0, 4, AT_CRn, 8, 4) | |
| 652 | #define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5) | |
| 653 | #define OP_AT_S12E0R sys_insn(AT_Op0, 4, AT_CRn, 8, 6) | |
| 654 | #define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7) | |
| 655 | ||
| fb1926cc MZ |
656 | /* TLBI instructions */ |
| 657 | #define OP_TLBI_VMALLE1OS sys_insn(1, 0, 8, 1, 0) | |
| 658 | #define OP_TLBI_VAE1OS sys_insn(1, 0, 8, 1, 1) | |
| 659 | #define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2) | |
| 660 | #define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3) | |
| 661 | #define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5) | |
| 662 | #define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7) | |
| 663 | #define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1) | |
| 664 | #define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3) | |
| 665 | #define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5) | |
| 666 | #define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7) | |
| 667 | #define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0) | |
| 668 | #define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1) | |
| 669 | #define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2) | |
| 670 | #define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3) | |
| 671 | #define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5) | |
| 672 | #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7) | |
| 673 | #define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1) | |
| 674 | #define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3) | |
| 675 | #define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5) | |
| 676 | #define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7) | |
| 677 | #define OP_TLBI_RVAE1 sys_insn(1, 0, 8, 6, 1) | |
| 678 | #define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3) | |
| 679 | #define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5) | |
| 680 | #define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7) | |
| 681 | #define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0) | |
| 682 | #define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1) | |
| 683 | #define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2) | |
| 684 | #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3) | |
| 685 | #define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5) | |
| 686 | #define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7) | |
| 687 | #define OP_TLBI_VMALLE1OSNXS sys_insn(1, 0, 9, 1, 0) | |
| 688 | #define OP_TLBI_VAE1OSNXS sys_insn(1, 0, 9, 1, 1) | |
| 689 | #define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2) | |
| 690 | #define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3) | |
| 691 | #define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5) | |
| 692 | #define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7) | |
| 693 | #define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1) | |
| 694 | #define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3) | |
| 695 | #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5) | |
| 696 | #define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7) | |
| 697 | #define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0) | |
| 698 | #define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1) | |
| 699 | #define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2) | |
| 700 | #define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3) | |
| 701 | #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5) | |
| 702 | #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7) | |
| 703 | #define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1) | |
| 704 | #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3) | |
| 705 | #define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5) | |
| 706 | #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7) | |
| 707 | #define OP_TLBI_RVAE1NXS sys_insn(1, 0, 9, 6, 1) | |
| 708 | #define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3) | |
| 709 | #define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5) | |
| 710 | #define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7) | |
| 711 | #define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0) | |
| 712 | #define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1) | |
| 713 | #define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2) | |
| 714 | #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3) | |
| 715 | #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5) | |
| 716 | #define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7) | |
| 717 | #define OP_TLBI_IPAS2E1IS sys_insn(1, 4, 8, 0, 1) | |
| 718 | #define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2) | |
| 719 | #define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5) | |
| 720 | #define OP_TLBI_RIPAS2LE1IS sys_insn(1, 4, 8, 0, 6) | |
| 721 | #define OP_TLBI_ALLE2OS sys_insn(1, 4, 8, 1, 0) | |
| 722 | #define OP_TLBI_VAE2OS sys_insn(1, 4, 8, 1, 1) | |
| 723 | #define OP_TLBI_ALLE1OS sys_insn(1, 4, 8, 1, 4) | |
| 724 | #define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5) | |
| 725 | #define OP_TLBI_VMALLS12E1OS sys_insn(1, 4, 8, 1, 6) | |
| 726 | #define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1) | |
| 727 | #define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5) | |
| 728 | #define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0) | |
| 729 | #define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1) | |
| 730 | #define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4) | |
| 731 | #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5) | |
| 732 | #define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6) | |
| 733 | #define OP_TLBI_IPAS2E1OS sys_insn(1, 4, 8, 4, 0) | |
| 734 | #define OP_TLBI_IPAS2E1 sys_insn(1, 4, 8, 4, 1) | |
| 735 | #define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2) | |
| 736 | #define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3) | |
| 737 | #define OP_TLBI_IPAS2LE1OS sys_insn(1, 4, 8, 4, 4) | |
| 738 | #define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5) | |
| 739 | #define OP_TLBI_RIPAS2LE1 sys_insn(1, 4, 8, 4, 6) | |
| 740 | #define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7) | |
| 741 | #define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1) | |
| 742 | #define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5) | |
| 743 | #define OP_TLBI_RVAE2 sys_insn(1, 4, 8, 6, 1) | |
| 744 | #define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5) | |
| 745 | #define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0) | |
| 746 | #define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1) | |
| 747 | #define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4) | |
| 748 | #define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5) | |
| 749 | #define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6) | |
| 750 | #define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1) | |
| 751 | #define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2) | |
| 752 | #define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5) | |
| 753 | #define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6) | |
| 754 | #define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0) | |
| 755 | #define OP_TLBI_VAE2OSNXS sys_insn(1, 4, 9, 1, 1) | |
| 756 | #define OP_TLBI_ALLE1OSNXS sys_insn(1, 4, 9, 1, 4) | |
| 757 | #define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5) | |
| 758 | #define OP_TLBI_VMALLS12E1OSNXS sys_insn(1, 4, 9, 1, 6) | |
| 759 | #define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1) | |
| 760 | #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5) | |
| 761 | #define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0) | |
| 762 | #define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1) | |
| 763 | #define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4) | |
| 764 | #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5) | |
| 765 | #define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6) | |
| 766 | #define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0) | |
| 767 | #define OP_TLBI_IPAS2E1NXS sys_insn(1, 4, 9, 4, 1) | |
| 768 | #define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2) | |
| 769 | #define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3) | |
| 770 | #define OP_TLBI_IPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 4) | |
| 771 | #define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5) | |
| 772 | #define OP_TLBI_RIPAS2LE1NXS sys_insn(1, 4, 9, 4, 6) | |
| 773 | #define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7) | |
| 774 | #define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1) | |
| 775 | #define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5) | |
| 776 | #define OP_TLBI_RVAE2NXS sys_insn(1, 4, 9, 6, 1) | |
| 777 | #define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5) | |
| 778 | #define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0) | |
| 779 | #define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1) | |
| 780 | #define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4) | |
| 781 | #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5) | |
| 782 | #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6) | |
| 783 | ||
| 2b062ed4 | 784 | /* Misc instructions */ |
| 4ebee8ce FT |
785 | #define OP_GCSPUSHX sys_insn(1, 0, 7, 7, 4) |
| 786 | #define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5) | |
| 787 | #define OP_GCSPOPX sys_insn(1, 0, 7, 7, 6) | |
| 788 | #define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0) | |
| 789 | ||
| 2b062ed4 MZ |
790 | #define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4) |
| 791 | #define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5) | |
| 792 | #define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4) | |
| 793 | #define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5) | |
| 4ebee8ce | 794 | #define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6) |
| 2b062ed4 MZ |
795 | #define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7) |
| 796 | ||
| e7227d0e | 797 | /* Common SCTLR_ELx flags. */ |
| b4adc83b | 798 | #define SCTLR_ELx_ENTP2 (BIT(60)) |
| fe6ba88b | 799 | #define SCTLR_ELx_DSSBS (BIT(44)) |
| c058b1c4 VF |
800 | #define SCTLR_ELx_ATA (BIT(43)) |
| 801 | ||
| 2ced0f30 | 802 | #define SCTLR_ELx_EE_SHIFT 25 |
| 20169862 PC |
803 | #define SCTLR_ELx_ENIA_SHIFT 31 |
| 804 | ||
| 56eb621b MB |
805 | #define SCTLR_ELx_ITFSB (BIT(37)) |
| 806 | #define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT)) | |
| 807 | #define SCTLR_ELx_ENIB (BIT(30)) | |
| 808 | #define SCTLR_ELx_LSMAOE (BIT(29)) | |
| 809 | #define SCTLR_ELx_nTLSMD (BIT(28)) | |
| 810 | #define SCTLR_ELx_ENDA (BIT(27)) | |
| 2ced0f30 | 811 | #define SCTLR_ELx_EE (BIT(SCTLR_ELx_EE_SHIFT)) |
| 56eb621b MB |
812 | #define SCTLR_ELx_EIS (BIT(22)) |
| 813 | #define SCTLR_ELx_IESB (BIT(21)) | |
| 814 | #define SCTLR_ELx_TSCXT (BIT(20)) | |
| 815 | #define SCTLR_ELx_WXN (BIT(19)) | |
| 816 | #define SCTLR_ELx_ENDB (BIT(13)) | |
| 817 | #define SCTLR_ELx_I (BIT(12)) | |
| 818 | #define SCTLR_ELx_EOS (BIT(11)) | |
| 819 | #define SCTLR_ELx_SA (BIT(3)) | |
| 820 | #define SCTLR_ELx_C (BIT(2)) | |
| 821 | #define SCTLR_ELx_A (BIT(1)) | |
| 822 | #define SCTLR_ELx_M (BIT(0)) | |
| e7227d0e | 823 | |
| 7a00d68e | 824 | /* SCTLR_EL2 specific flags. */ |
| fe6ba88b MY |
825 | #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \ |
| 826 | (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \ | |
| 827 | (BIT(29))) | |
| 7a00d68e | 828 | |
| b53d4a27 | 829 | #define SCTLR_EL2_BT (BIT(36)) |
| 7a00d68e JM |
830 | #ifdef CONFIG_CPU_BIG_ENDIAN |
| 831 | #define ENDIAN_SET_EL2 SCTLR_ELx_EE | |
| 7a00d68e JM |
832 | #else |
| 833 | #define ENDIAN_SET_EL2 0 | |
| 1c312e84 | 834 | #endif |
| e7227d0e | 835 | |
| fe2c8d19 MZ |
836 | #define INIT_SCTLR_EL2_MMU_ON \ |
| 837 | (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I | \ | |
| e1f358b5 SP |
838 | SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 | \ |
| 839 | SCTLR_ELx_ITFSB | SCTLR_EL2_RES1) | |
| fe2c8d19 | 840 | |
| 2ffac9e3 MR |
841 | #define INIT_SCTLR_EL2_MMU_OFF \ |
| 842 | (SCTLR_EL2_RES1 | ENDIAN_SET_EL2) | |
| 843 | ||
| e7227d0e | 844 | /* SCTLR_EL1 specific flags. */ |
| 7a00d68e JM |
845 | #ifdef CONFIG_CPU_BIG_ENDIAN |
| 846 | #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) | |
| 7a00d68e JM |
847 | #else |
| 848 | #define ENDIAN_SET_EL1 0 | |
| 7a00d68e JM |
849 | #endif |
| 850 | ||
| 2ffac9e3 | 851 | #define INIT_SCTLR_EL1_MMU_OFF \ |
| 56eb621b MB |
852 | (ENDIAN_SET_EL1 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | \ |
| 853 | SCTLR_EL1_EIS | SCTLR_EL1_TSCXT | SCTLR_EL1_EOS) | |
| 2ffac9e3 MR |
854 | |
| 855 | #define INIT_SCTLR_EL1_MMU_ON \ | |
| 56eb621b MB |
856 | (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | \ |
| 857 | SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I | \ | |
| 858 | SCTLR_EL1_DZE | SCTLR_EL1_UCT | SCTLR_EL1_nTWE | \ | |
| 859 | SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \ | |
| 860 | ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_EPAN | \ | |
| 861 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS | \ | |
| 862 | SCTLR_EL1_TSCXT | SCTLR_EL1_EOS) | |
| 3c739b57 | 863 | |
| 95b3f74b CM |
864 | /* MAIR_ELx memory attributes (used by Linux) */ |
| 865 | #define MAIR_ATTR_DEVICE_nGnRnE UL(0x00) | |
| 866 | #define MAIR_ATTR_DEVICE_nGnRE UL(0x04) | |
| 95b3f74b | 867 | #define MAIR_ATTR_NORMAL_NC UL(0x44) |
| c058b1c4 | 868 | #define MAIR_ATTR_NORMAL_TAGGED UL(0xf0) |
| 95b3f74b CM |
869 | #define MAIR_ATTR_NORMAL UL(0xff) |
| 870 | #define MAIR_ATTR_MASK UL(0xff) | |
| 871 | ||
| 872 | /* Position the attr at the correct index */ | |
| 873 | #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) | |
| 874 | ||
| 3c739b57 | 875 | /* id_aa64pfr0 */ |
| 55adc08d MB |
876 | #define ID_AA64PFR0_EL1_ELx_64BIT_ONLY 0x1 |
| 877 | #define ID_AA64PFR0_EL1_ELx_32BIT_64BIT 0x2 | |
| 3c739b57 SP |
878 | |
| 879 | /* id_aa64mmfr0 */ | |
| 2d987e64 | 880 | #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0 |
| e477c8c4 | 881 | #define ID_AA64MMFR0_EL1_TGRAN4_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT |
| 2d987e64 | 882 | #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 0x7 |
| 2d987e64 MB |
883 | #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 0x0 |
| 884 | #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 0x7 | |
| 2d987e64 | 885 | #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 0x1 |
| e477c8c4 | 886 | #define ID_AA64MMFR0_EL1_TGRAN16_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT |
| 2d987e64 MB |
887 | #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 0xf |
| 888 | ||
| 504c6295 AK |
889 | #define ARM64_MIN_PARANGE_BITS 32 |
| 890 | ||
| 2d987e64 MB |
891 | #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT 0x0 |
| 892 | #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE 0x1 | |
| 893 | #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN 0x2 | |
| e477c8c4 | 894 | #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2 0x3 |
| 2d987e64 | 895 | #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7 |
| 26f55386 | 896 | |
| 787fd1d0 | 897 | #ifdef CONFIG_ARM64_PA_BITS_52 |
| 2d987e64 | 898 | #define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_52 |
| 787fd1d0 | 899 | #else |
| 2d987e64 | 900 | #define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48 |
| 787fd1d0 | 901 | #endif |
| 3c739b57 | 902 | |
| 4bf8b96e | 903 | #if defined(CONFIG_ARM64_4K_PAGES) |
| 2d987e64 | 904 | #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT |
| e477c8c4 | 905 | #define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT |
| 2d987e64 MB |
906 | #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN |
| 907 | #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX | |
| 908 | #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT | |
| 44eaacf1 | 909 | #elif defined(CONFIG_ARM64_16K_PAGES) |
| 2d987e64 | 910 | #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN16_SHIFT |
| e477c8c4 | 911 | #define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT |
| 2d987e64 MB |
912 | #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN |
| 913 | #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX | |
| 914 | #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT | |
| 4bf8b96e | 915 | #elif defined(CONFIG_ARM64_64K_PAGES) |
| 2d987e64 MB |
916 | #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN64_SHIFT |
| 917 | #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN | |
| 918 | #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX | |
| 919 | #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT | |
| 4bf8b96e SP |
920 | #endif |
| 921 | ||
| 879358fc MB |
922 | #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */ |
| 923 | #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */ | |
| 879358fc | 924 | |
| b4adc83b MB |
925 | #define CPACR_EL1_SMEN_EL1EN (BIT(24)) /* enable EL1 access */ |
| 926 | #define CPACR_EL1_SMEN_EL0EN (BIT(25)) /* enable EL0 access, if EL1EN set */ | |
| 927 | ||
| fe6ba88b MY |
928 | #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */ |
| 929 | #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */ | |
| 67236564 | 930 | |
| c058b1c4 VF |
931 | /* GCR_EL1 Definitions */ |
| 932 | #define SYS_GCR_EL1_RRND (BIT(16)) | |
| 933 | #define SYS_GCR_EL1_EXCL_MASK 0xffffUL | |
| 934 | ||
| 82868247 MR |
935 | #ifdef CONFIG_KASAN_HW_TAGS |
| 936 | /* | |
| 937 | * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it | |
| 938 | * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF. | |
| 939 | */ | |
| 940 | #define __MTE_TAG_MIN (KASAN_TAG_MIN & 0xf) | |
| 941 | #define __MTE_TAG_MAX (KASAN_TAG_MAX & 0xf) | |
| 942 | #define __MTE_TAG_INCL GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN) | |
| 943 | #define KERNEL_GCR_EL1_EXCL (SYS_GCR_EL1_EXCL_MASK & ~__MTE_TAG_INCL) | |
| 944 | #else | |
| 945 | #define KERNEL_GCR_EL1_EXCL SYS_GCR_EL1_EXCL_MASK | |
| 946 | #endif | |
| 947 | ||
| 948 | #define KERNEL_GCR_EL1 (SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL) | |
| 949 | ||
| c058b1c4 VF |
950 | /* RGSR_EL1 Definitions */ |
| 951 | #define SYS_RGSR_EL1_TAG_MASK 0xfUL | |
| 952 | #define SYS_RGSR_EL1_SEED_SHIFT 8 | |
| 953 | #define SYS_RGSR_EL1_SEED_MASK 0xffffUL | |
| 954 | ||
| c058b1c4 VF |
955 | /* TFSR{,E0}_EL1 bit definitions */ |
| 956 | #define SYS_TFSR_EL1_TF0_SHIFT 0 | |
| 957 | #define SYS_TFSR_EL1_TF1_SHIFT 1 | |
| 958 | #define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT) | |
| 9e5344e0 | 959 | #define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT) |
| 67236564 | 960 | |
| 77c97b4e | 961 | /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ |
| fe6ba88b | 962 | #define SYS_MPIDR_SAFE_VAL (BIT(31)) |
| 77c97b4e | 963 | |
| 4b6929f5 | 964 | #define TRFCR_ELx_TS_SHIFT 5 |
| 0f00b223 | 965 | #define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT) |
| 4b6929f5 JZ |
966 | #define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) |
| 967 | #define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) | |
| 968 | #define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) | |
| 969 | #define TRFCR_EL2_CX BIT(3) | |
| 970 | #define TRFCR_ELx_ExTRE BIT(1) | |
| 971 | #define TRFCR_ELx_E0TRE BIT(0) | |
| 972 | ||
| 8a657f71 HM |
973 | /* GIC Hypervisor interface registers */ |
| 974 | /* ICH_MISR_EL2 bit definitions */ | |
| 975 | #define ICH_MISR_EOI (1 << 0) | |
| 976 | #define ICH_MISR_U (1 << 1) | |
| 977 | ||
| 978 | /* ICH_LR*_EL2 bit definitions */ | |
| 979 | #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1) | |
| 980 | ||
| 981 | #define ICH_LR_EOI (1ULL << 41) | |
| 982 | #define ICH_LR_GROUP (1ULL << 60) | |
| 983 | #define ICH_LR_HW (1ULL << 61) | |
| 984 | #define ICH_LR_STATE (3ULL << 62) | |
| 985 | #define ICH_LR_PENDING_BIT (1ULL << 62) | |
| 986 | #define ICH_LR_ACTIVE_BIT (1ULL << 63) | |
| 987 | #define ICH_LR_PHYS_ID_SHIFT 32 | |
| 988 | #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT) | |
| 989 | #define ICH_LR_PRIORITY_SHIFT 48 | |
| 990 | #define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT) | |
| 991 | ||
| 992 | /* ICH_HCR_EL2 bit definitions */ | |
| 993 | #define ICH_HCR_EN (1 << 0) | |
| 994 | #define ICH_HCR_UIE (1 << 1) | |
| 995 | #define ICH_HCR_NPIE (1 << 3) | |
| 996 | #define ICH_HCR_TC (1 << 10) | |
| 997 | #define ICH_HCR_TALL0 (1 << 11) | |
| 998 | #define ICH_HCR_TALL1 (1 << 12) | |
| 0924729b | 999 | #define ICH_HCR_TDIR (1 << 14) |
| 8a657f71 HM |
1000 | #define ICH_HCR_EOIcount_SHIFT 27 |
| 1001 | #define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT) | |
| 1002 | ||
| 1003 | /* ICH_VMCR_EL2 bit definitions */ | |
| 1004 | #define ICH_VMCR_ACK_CTL_SHIFT 2 | |
| 1005 | #define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT) | |
| 1006 | #define ICH_VMCR_FIQ_EN_SHIFT 3 | |
| 1007 | #define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT) | |
| 1008 | #define ICH_VMCR_CBPR_SHIFT 4 | |
| 1009 | #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT) | |
| 1010 | #define ICH_VMCR_EOIM_SHIFT 9 | |
| 1011 | #define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT) | |
| 1012 | #define ICH_VMCR_BPR1_SHIFT 18 | |
| 1013 | #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT) | |
| 1014 | #define ICH_VMCR_BPR0_SHIFT 21 | |
| 1015 | #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT) | |
| 1016 | #define ICH_VMCR_PMR_SHIFT 24 | |
| 1017 | #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT) | |
| 1018 | #define ICH_VMCR_ENG0_SHIFT 0 | |
| 1019 | #define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT) | |
| 1020 | #define ICH_VMCR_ENG1_SHIFT 1 | |
| 1021 | #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT) | |
| 1022 | ||
| 1023 | /* ICH_VTR_EL2 bit definitions */ | |
| 1024 | #define ICH_VTR_PRI_BITS_SHIFT 29 | |
| 1025 | #define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT) | |
| 1026 | #define ICH_VTR_ID_BITS_SHIFT 23 | |
| 1027 | #define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT) | |
| 1028 | #define ICH_VTR_SEIS_SHIFT 22 | |
| 1029 | #define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT) | |
| 1030 | #define ICH_VTR_A3V_SHIFT 21 | |
| 1031 | #define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT) | |
| 0924729b MZ |
1032 | #define ICH_VTR_TDS_SHIFT 19 |
| 1033 | #define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT) | |
| 8a657f71 | 1034 | |
| c36ad194 JG |
1035 | /* |
| 1036 | * Permission Indirection Extension (PIE) permission encodings. | |
| 1037 | * Encodings with the _O suffix, have overlays applied (Permission Overlay Extension). | |
| 1038 | */ | |
| 1039 | #define PIE_NONE_O 0x0 | |
| 1040 | #define PIE_R_O 0x1 | |
| 1041 | #define PIE_X_O 0x2 | |
| 1042 | #define PIE_RX_O 0x3 | |
| 1043 | #define PIE_RW_O 0x5 | |
| 1044 | #define PIE_RWnX_O 0x6 | |
| 1045 | #define PIE_RWX_O 0x7 | |
| 1046 | #define PIE_R 0x8 | |
| 1047 | #define PIE_GCS 0x9 | |
| 1048 | #define PIE_RX 0xa | |
| 1049 | #define PIE_RW 0xc | |
| 1050 | #define PIE_RWX 0xe | |
| 1051 | ||
| 1052 | #define PIRx_ELx_PERM(idx, perm) ((perm) << ((idx) * 4)) | |
| 1053 | ||
| c0c5a8ea JG |
1054 | /* |
| 1055 | * Permission Overlay Extension (POE) permission encodings. | |
| 1056 | */ | |
| 1057 | #define POE_NONE UL(0x0) | |
| 1058 | #define POE_R UL(0x1) | |
| 1059 | #define POE_X UL(0x2) | |
| 1060 | #define POE_RX UL(0x3) | |
| 1061 | #define POE_W UL(0x4) | |
| 1062 | #define POE_RW UL(0x5) | |
| 1063 | #define POE_XW UL(0x6) | |
| 1064 | #define POE_RXW UL(0x7) | |
| 1065 | #define POE_MASK UL(0xf) | |
| 1066 | ||
| f76f89e2 FT |
1067 | #define ARM64_FEATURE_FIELD_BITS 4 |
| 1068 | ||
| e978eaca MB |
1069 | /* Defined for compatibility only, do not add new users. */ |
| 1070 | #define ARM64_FEATURE_MASK(x) (x##_MASK) | |
| f76f89e2 | 1071 | |
| 72c58395 CM |
1072 | #ifdef __ASSEMBLY__ |
| 1073 | ||
| 72c58395 | 1074 | .macro mrs_s, rt, sreg |
| 8ed1b498 | 1075 | __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt)) |
| 72c58395 CM |
1076 | .endm |
| 1077 | ||
| 1078 | .macro msr_s, sreg, rt | |
| 8ed1b498 | 1079 | __emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt)) |
| 72c58395 CM |
1080 | .endm |
| 1081 | ||
| 1082 | #else | |
| 1083 | ||
| 02e483f8 | 1084 | #include <linux/bitfield.h> |
| 7a00d68e | 1085 | #include <linux/build_bug.h> |
| 3600c2fd | 1086 | #include <linux/types.h> |
| 96d389ca | 1087 | #include <asm/alternative.h> |
| 3600c2fd | 1088 | |
| be604c61 | 1089 | #define DEFINE_MRS_S \ |
| 8ed1b498 | 1090 | __DEFINE_ASM_GPR_NUMS \ |
| be604c61 | 1091 | " .macro mrs_s, rt, sreg\n" \ |
| 8ed1b498 | 1092 | __emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt)) \ |
| 72c58395 | 1093 | " .endm\n" |
| be604c61 KC |
1094 | |
| 1095 | #define DEFINE_MSR_S \ | |
| 8ed1b498 | 1096 | __DEFINE_ASM_GPR_NUMS \ |
| be604c61 | 1097 | " .macro msr_s, sreg, rt\n" \ |
| 8ed1b498 | 1098 | __emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt)) \ |
| 72c58395 | 1099 | " .endm\n" |
| be604c61 KC |
1100 | |
| 1101 | #define UNDEFINE_MRS_S \ | |
| 1102 | " .purgem mrs_s\n" | |
| 1103 | ||
| 1104 | #define UNDEFINE_MSR_S \ | |
| 1105 | " .purgem msr_s\n" | |
| 1106 | ||
| 1107 | #define __mrs_s(v, r) \ | |
| 1108 | DEFINE_MRS_S \ | |
| 1109 | " mrs_s " v ", " __stringify(r) "\n" \ | |
| 1110 | UNDEFINE_MRS_S | |
| 1111 | ||
| 1112 | #define __msr_s(r, v) \ | |
| 1113 | DEFINE_MSR_S \ | |
| 1114 | " msr_s " __stringify(r) ", " v "\n" \ | |
| 1115 | UNDEFINE_MSR_S | |
| 72c58395 | 1116 | |
| 3600c2fd MR |
1117 | /* |
| 1118 | * Unlike read_cpuid, calls to read_sysreg are never expected to be | |
| 1119 | * optimized away or replaced with synthetic values. | |
| 1120 | */ | |
| 1121 | #define read_sysreg(r) ({ \ | |
| 1122 | u64 __val; \ | |
| 1123 | asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ | |
| 1124 | __val; \ | |
| 1125 | }) | |
| 1126 | ||
| 7aff4a2d MR |
1127 | /* |
| 1128 | * The "Z" constraint normally means a zero immediate, but when combined with | |
| 1129 | * the "%x0" template means XZR. | |
| 1130 | */ | |
| 3600c2fd | 1131 | #define write_sysreg(v, r) do { \ |
| d0153c7f | 1132 | u64 __val = (u64)(v); \ |
| 7aff4a2d MR |
1133 | asm volatile("msr " __stringify(r) ", %x0" \ |
| 1134 | : : "rZ" (__val)); \ | |
| 3600c2fd MR |
1135 | } while (0) |
| 1136 | ||
| 8a71f0c6 WD |
1137 | /* |
| 1138 | * For registers without architectural names, or simply unsupported by | |
| 1139 | * GAS. | |
| 18b8f57a JC |
1140 | * |
| 1141 | * __check_r forces warnings to be generated by the compiler when | |
| 1142 | * evaluating r which wouldn't normally happen due to being passed to | |
| 1143 | * the assembler via __stringify(r). | |
| 8a71f0c6 WD |
1144 | */ |
| 1145 | #define read_sysreg_s(r) ({ \ | |
| 1146 | u64 __val; \ | |
| 18b8f57a | 1147 | u32 __maybe_unused __check_r = (u32)(r); \ |
| be604c61 | 1148 | asm volatile(__mrs_s("%0", r) : "=r" (__val)); \ |
| 8a71f0c6 WD |
1149 | __val; \ |
| 1150 | }) | |
| 1151 | ||
| 1152 | #define write_sysreg_s(v, r) do { \ | |
| d0153c7f | 1153 | u64 __val = (u64)(v); \ |
| 18b8f57a | 1154 | u32 __maybe_unused __check_r = (u32)(r); \ |
| be604c61 | 1155 | asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \ |
| 8a71f0c6 WD |
1156 | } while (0) |
| 1157 | ||
| 6ebdf4db MR |
1158 | /* |
| 1159 | * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the | |
| 1160 | * set mask are set. Other bits are left as-is. | |
| 1161 | */ | |
| 1162 | #define sysreg_clear_set(sysreg, clear, set) do { \ | |
| 1163 | u64 __scs_val = read_sysreg(sysreg); \ | |
| 1164 | u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ | |
| 1165 | if (__scs_new != __scs_val) \ | |
| 1166 | write_sysreg(__scs_new, sysreg); \ | |
| 1167 | } while (0) | |
| 1168 | ||
| af5ce952 CM |
1169 | #define sysreg_clear_set_s(sysreg, clear, set) do { \ |
| 1170 | u64 __scs_val = read_sysreg_s(sysreg); \ | |
| 1171 | u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ | |
| 1172 | if (__scs_new != __scs_val) \ | |
| 1173 | write_sysreg_s(__scs_new, sysreg); \ | |
| 1174 | } while (0) | |
| 1175 | ||
| 96d389ca RH |
1176 | #define read_sysreg_par() ({ \ |
| 1177 | u64 par; \ | |
| 1178 | asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ | |
| 1179 | par = read_sysreg(par_el1); \ | |
| 1180 | asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ | |
| 1181 | par; \ | |
| 1182 | }) | |
| 1183 | ||
| 53eaeb7f MZ |
1184 | #define SYS_FIELD_VALUE(reg, field, val) reg##_##field##_##val |
| 1185 | ||
| 3a87d538 MB |
1186 | #define SYS_FIELD_GET(reg, field, val) \ |
| 1187 | FIELD_GET(reg##_##field##_MASK, val) | |
| 1188 | ||
| e6a6b34f MB |
1189 | #define SYS_FIELD_PREP(reg, field, val) \ |
| 1190 | FIELD_PREP(reg##_##field##_MASK, val) | |
| 1191 | ||
| 1192 | #define SYS_FIELD_PREP_ENUM(reg, field, val) \ | |
| 53eaeb7f MZ |
1193 | FIELD_PREP(reg##_##field##_MASK, \ |
| 1194 | SYS_FIELD_VALUE(reg, field, val)) | |
| e6a6b34f | 1195 | |
| a10edea4 MB |
1196 | #endif |
| 1197 | ||
| 72c58395 | 1198 | #endif /* __ASM_SYSREG_H */ |