Commit | Line | Data |
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caab277b | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
08e875c1 CM |
2 | /* |
3 | * Copyright (C) 2012 ARM Ltd. | |
08e875c1 CM |
4 | */ |
5 | #ifndef __ASM_SMP_H | |
6 | #define __ASM_SMP_H | |
7 | ||
1236cd2b SZ |
8 | #include <linux/const.h> |
9 | ||
bb905274 | 10 | /* Values for secondary_data.status */ |
66f16a24 | 11 | #define CPU_STUCK_REASON_SHIFT (8) |
1236cd2b | 12 | #define CPU_BOOT_STATUS_MASK ((UL(1) << CPU_STUCK_REASON_SHIFT) - 1) |
bb905274 | 13 | |
66f16a24 WD |
14 | #define CPU_MMU_OFF (-1) |
15 | #define CPU_BOOT_SUCCESS (0) | |
bb905274 | 16 | /* The cpu invoked ops->cpu_die, synchronise it with cpu_kill */ |
66f16a24 | 17 | #define CPU_KILL_ME (1) |
bb905274 | 18 | /* The cpu couldn't die gracefully and is looping in the kernel */ |
66f16a24 | 19 | #define CPU_STUCK_IN_KERNEL (2) |
bb905274 | 20 | /* Fatal system error detected by secondary CPU, crash the system */ |
66f16a24 WD |
21 | #define CPU_PANIC_KERNEL (3) |
22 | ||
1236cd2b SZ |
23 | #define CPU_STUCK_REASON_52_BIT_VA (UL(1) << CPU_STUCK_REASON_SHIFT) |
24 | #define CPU_STUCK_REASON_NO_GRAN (UL(2) << CPU_STUCK_REASON_SHIFT) | |
bb905274 SP |
25 | |
26 | #ifndef __ASSEMBLY__ | |
27 | ||
08e875c1 CM |
28 | #include <linux/threads.h> |
29 | #include <linux/cpumask.h> | |
30 | #include <linux/thread_info.h> | |
31 | ||
bf0baa5b | 32 | #define raw_smp_processor_id() (current_thread_info()->cpu) |
08e875c1 | 33 | |
262afe92 FF |
34 | /* |
35 | * Logical CPU mapping. | |
36 | */ | |
37 | extern u64 __cpu_logical_map[NR_CPUS]; | |
c1f45f4e | 38 | extern u64 cpu_logical_map(unsigned int cpu); |
eaecca9e | 39 | |
c1f45f4e | 40 | static inline void set_cpu_logical_map(unsigned int cpu, u64 hwid) |
eaecca9e KW |
41 | { |
42 | __cpu_logical_map[cpu] = hwid; | |
43 | } | |
262afe92 | 44 | |
08e875c1 CM |
45 | struct seq_file; |
46 | ||
08e875c1 | 47 | /* |
fccb9a81 HG |
48 | * Discover the set of possible CPUs and determine their |
49 | * SMP operations. | |
08e875c1 | 50 | */ |
0f078336 | 51 | extern void smp_init_cpus(void); |
08e875c1 | 52 | |
d3afc7f1 MZ |
53 | /* |
54 | * Register IPI interrupts with the arch SMP code | |
55 | */ | |
56 | extern void set_smp_ipi_range(int ipi_base, int nr_ipi); | |
57 | ||
08e875c1 CM |
58 | /* |
59 | * Called from the secondary holding pen, this is the secondary CPU entry point. | |
60 | */ | |
61 | asmlinkage void secondary_start_kernel(void); | |
62 | ||
63 | /* | |
64 | * Initial data for bringing up a secondary CPU. | |
bb905274 SP |
65 | * @status - Result passed back from the secondary CPU to |
66 | * indicate failure. | |
08e875c1 CM |
67 | */ |
68 | struct secondary_data { | |
c02433dd | 69 | struct task_struct *task; |
bb905274 | 70 | long status; |
08e875c1 | 71 | }; |
bb905274 | 72 | |
08e875c1 | 73 | extern struct secondary_data secondary_data; |
bb905274 | 74 | extern long __early_cpu_boot_status; |
652af899 | 75 | extern void secondary_entry(void); |
08e875c1 CM |
76 | |
77 | extern void arch_send_call_function_single_ipi(int cpu); | |
78 | extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); | |
79 | ||
5e89c55e | 80 | #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL |
2b2d0a7a | 81 | extern void arch_send_wakeup_ipi(unsigned int cpu); |
5e89c55e | 82 | #else |
2b2d0a7a | 83 | static inline void arch_send_wakeup_ipi(unsigned int cpu) |
5e89c55e LP |
84 | { |
85 | BUILD_BUG(); | |
86 | } | |
87 | #endif | |
88 | ||
9327e2c6 MR |
89 | extern int __cpu_disable(void); |
90 | ||
b3091f17 | 91 | static inline void __cpu_die(unsigned int cpu) { } |
9bdc61ef | 92 | extern void __noreturn cpu_die(void); |
5ab6876c | 93 | extern void __noreturn cpu_die_early(void); |
9327e2c6 | 94 | |
5ab6876c | 95 | static inline void __noreturn cpu_park_loop(void) |
c4bc34d2 SP |
96 | { |
97 | for (;;) { | |
98 | wfe(); | |
99 | wfi(); | |
100 | } | |
101 | } | |
102 | ||
bb905274 SP |
103 | static inline void update_cpu_boot_status(int val) |
104 | { | |
105 | WRITE_ONCE(secondary_data.status, val); | |
106 | /* Ensure the visibility of the status update */ | |
107 | dsb(ishst); | |
108 | } | |
109 | ||
17eebd1a SP |
110 | /* |
111 | * The calling secondary CPU has detected serious configuration mismatch, | |
112 | * which calls for a kernel panic. Update the boot status and park the calling | |
113 | * CPU. | |
114 | */ | |
5ab6876c | 115 | static inline void __noreturn cpu_panic_kernel(void) |
17eebd1a SP |
116 | { |
117 | update_cpu_boot_status(CPU_PANIC_KERNEL); | |
118 | cpu_park_loop(); | |
119 | } | |
120 | ||
5c492c3f JM |
121 | /* |
122 | * If a secondary CPU enters the kernel but fails to come online, | |
123 | * (e.g. due to mismatched features), and cannot exit the kernel, | |
124 | * we increment cpus_stuck_in_kernel and leave the CPU in a | |
125 | * quiesecent loop within the kernel text. The memory containing | |
126 | * this loop must not be re-used for anything else as the 'stuck' | |
127 | * core is executing it. | |
128 | * | |
129 | * This function is used to inhibit features like kexec and hibernate. | |
130 | */ | |
131 | bool cpus_are_stuck_in_kernel(void); | |
132 | ||
a88ce63b | 133 | extern void crash_smp_send_stop(void); |
78fd584c AT |
134 | extern bool smp_crash_stop_failed(void); |
135 | ||
bb905274 SP |
136 | #endif /* ifndef __ASSEMBLY__ */ |
137 | ||
08e875c1 | 138 | #endif /* ifndef __ASM_SMP_H */ |