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60ffc30d CM |
1 | /* |
2 | * Based on arch/arm/include/asm/ptrace.h | |
3 | * | |
4 | * Copyright (C) 1996-2003 Russell King | |
5 | * Copyright (C) 2012 ARM Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #ifndef __ASM_PTRACE_H | |
20 | #define __ASM_PTRACE_H | |
21 | ||
4262a727 | 22 | #include <uapi/asm/ptrace.h> |
60ffc30d | 23 | |
974c8e45 MZ |
24 | /* Current Exception Level values, as contained in CurrentEL */ |
25 | #define CurrentEL_EL1 (1 << 2) | |
26 | #define CurrentEL_EL2 (2 << 2) | |
27 | ||
60ffc30d | 28 | /* AArch32-specific ptrace requests */ |
27aa55c5 WD |
29 | #define COMPAT_PTRACE_GETREGS 12 |
30 | #define COMPAT_PTRACE_SETREGS 13 | |
31 | #define COMPAT_PTRACE_GET_THREAD_AREA 22 | |
32 | #define COMPAT_PTRACE_SET_SYSCALL 23 | |
60ffc30d CM |
33 | #define COMPAT_PTRACE_GETVFPREGS 27 |
34 | #define COMPAT_PTRACE_SETVFPREGS 28 | |
27aa55c5 WD |
35 | #define COMPAT_PTRACE_GETHBPREGS 29 |
36 | #define COMPAT_PTRACE_SETHBPREGS 30 | |
9ec218b8 MZ |
37 | |
38 | /* AArch32 CPSR bits */ | |
39 | #define COMPAT_PSR_MODE_MASK 0x0000001f | |
60ffc30d | 40 | #define COMPAT_PSR_MODE_USR 0x00000010 |
9ec218b8 MZ |
41 | #define COMPAT_PSR_MODE_FIQ 0x00000011 |
42 | #define COMPAT_PSR_MODE_IRQ 0x00000012 | |
43 | #define COMPAT_PSR_MODE_SVC 0x00000013 | |
44 | #define COMPAT_PSR_MODE_ABT 0x00000017 | |
45 | #define COMPAT_PSR_MODE_HYP 0x0000001a | |
46 | #define COMPAT_PSR_MODE_UND 0x0000001b | |
47 | #define COMPAT_PSR_MODE_SYS 0x0000001f | |
60ffc30d | 48 | #define COMPAT_PSR_T_BIT 0x00000020 |
a795a38e | 49 | #define COMPAT_PSR_E_BIT 0x00000200 |
10a3cc2f MZ |
50 | #define COMPAT_PSR_F_BIT 0x00000040 |
51 | #define COMPAT_PSR_I_BIT 0x00000080 | |
52 | #define COMPAT_PSR_A_BIT 0x00000100 | |
53 | #define COMPAT_PSR_E_BIT 0x00000200 | |
54 | #define COMPAT_PSR_J_BIT 0x01000000 | |
55 | #define COMPAT_PSR_Q_BIT 0x08000000 | |
56 | #define COMPAT_PSR_V_BIT 0x10000000 | |
57 | #define COMPAT_PSR_C_BIT 0x20000000 | |
58 | #define COMPAT_PSR_Z_BIT 0x40000000 | |
59 | #define COMPAT_PSR_N_BIT 0x80000000 | |
60ffc30d | 60 | #define COMPAT_PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */ |
60ffc30d CM |
61 | /* |
62 | * These are 'magic' values for PTRACE_PEEKUSR that return info about where a | |
63 | * process is located in memory. | |
64 | */ | |
7606c37d CM |
65 | #define COMPAT_PT_TEXT_ADDR 0x10000 |
66 | #define COMPAT_PT_DATA_ADDR 0x10004 | |
67 | #define COMPAT_PT_TEXT_END_ADDR 0x10008 | |
60ffc30d CM |
68 | #ifndef __ASSEMBLY__ |
69 | ||
60ffc30d CM |
70 | /* sizeof(struct user) for AArch32 */ |
71 | #define COMPAT_USER_SZ 296 | |
88483ec6 MZ |
72 | |
73 | /* Architecturally defined mapping between AArch32 and AArch64 registers */ | |
74 | #define compat_usr(x) regs[(x)] | |
2ee0d7fd | 75 | #define compat_fp regs[11] |
60ffc30d | 76 | #define compat_sp regs[13] |
60ffc30d | 77 | #define compat_lr regs[14] |
88483ec6 MZ |
78 | #define compat_sp_hyp regs[15] |
79 | #define compat_sp_irq regs[16] | |
80 | #define compat_lr_irq regs[17] | |
81 | #define compat_sp_svc regs[18] | |
82 | #define compat_lr_svc regs[19] | |
83 | #define compat_sp_abt regs[20] | |
84 | #define compat_lr_abt regs[21] | |
85 | #define compat_sp_und regs[22] | |
86 | #define compat_lr_und regs[23] | |
87 | #define compat_r8_fiq regs[24] | |
88 | #define compat_r9_fiq regs[25] | |
89 | #define compat_r10_fiq regs[26] | |
90 | #define compat_r11_fiq regs[27] | |
91 | #define compat_r12_fiq regs[28] | |
92 | #define compat_sp_fiq regs[29] | |
93 | #define compat_lr_fiq regs[30] | |
60ffc30d CM |
94 | |
95 | /* | |
96 | * This struct defines the way the registers are stored on the stack during an | |
97 | * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for | |
98 | * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs. | |
99 | */ | |
100 | struct pt_regs { | |
101 | union { | |
102 | struct user_pt_regs user_regs; | |
103 | struct { | |
104 | u64 regs[31]; | |
105 | u64 sp; | |
106 | u64 pc; | |
107 | u64 pstate; | |
108 | }; | |
109 | }; | |
110 | u64 orig_x0; | |
111 | u64 syscallno; | |
112 | }; | |
113 | ||
114 | #define arch_has_single_step() (1) | |
115 | ||
116 | #ifdef CONFIG_COMPAT | |
117 | #define compat_thumb_mode(regs) \ | |
118 | (((regs)->pstate & COMPAT_PSR_T_BIT)) | |
119 | #else | |
120 | #define compat_thumb_mode(regs) (0) | |
121 | #endif | |
122 | ||
123 | #define user_mode(regs) \ | |
124 | (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t) | |
125 | ||
126 | #define compat_user_mode(regs) \ | |
127 | (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \ | |
128 | (PSR_MODE32_BIT | PSR_MODE_EL0t)) | |
129 | ||
130 | #define processor_mode(regs) \ | |
131 | ((regs)->pstate & PSR_MODE_MASK) | |
132 | ||
133 | #define interrupts_enabled(regs) \ | |
134 | (!((regs)->pstate & PSR_I_BIT)) | |
135 | ||
136 | #define fast_interrupts_enabled(regs) \ | |
137 | (!((regs)->pstate & PSR_F_BIT)) | |
138 | ||
139 | #define user_stack_pointer(regs) \ | |
5f888a1d | 140 | (!compat_user_mode(regs)) ? ((regs)->sp) : ((regs)->compat_sp) |
60ffc30d | 141 | |
d34a3ebd AT |
142 | static inline unsigned long regs_return_value(struct pt_regs *regs) |
143 | { | |
144 | return regs->regs[0]; | |
145 | } | |
146 | ||
60ffc30d CM |
147 | /* |
148 | * Are the current registers suitable for user mode? (used to maintain | |
149 | * security in signal handlers) | |
150 | */ | |
151 | static inline int valid_user_regs(struct user_pt_regs *regs) | |
152 | { | |
153 | if (user_mode(regs) && (regs->pstate & PSR_I_BIT) == 0) { | |
154 | regs->pstate &= ~(PSR_F_BIT | PSR_A_BIT); | |
155 | ||
156 | /* The T bit is reserved for AArch64 */ | |
157 | if (!(regs->pstate & PSR_MODE32_BIT)) | |
158 | regs->pstate &= ~COMPAT_PSR_T_BIT; | |
159 | ||
160 | return 1; | |
161 | } | |
162 | ||
163 | /* | |
164 | * Force PSR to something logical... | |
165 | */ | |
166 | regs->pstate &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | \ | |
167 | COMPAT_PSR_T_BIT | PSR_MODE32_BIT; | |
168 | ||
169 | if (!(regs->pstate & PSR_MODE32_BIT)) { | |
170 | regs->pstate &= ~COMPAT_PSR_T_BIT; | |
171 | regs->pstate |= PSR_MODE_EL0t; | |
172 | } | |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
58dcc204 | 177 | #define instruction_pointer(regs) ((unsigned long)(regs)->pc) |
60ffc30d CM |
178 | |
179 | #ifdef CONFIG_SMP | |
180 | extern unsigned long profile_pc(struct pt_regs *regs); | |
181 | #else | |
182 | #define profile_pc(regs) instruction_pointer(regs) | |
183 | #endif | |
184 | ||
60ffc30d | 185 | #endif /* __ASSEMBLY__ */ |
60ffc30d | 186 | #endif |