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60ffc30d CM |
1 | /* |
2 | * Based on arch/arm/include/asm/ptrace.h | |
3 | * | |
4 | * Copyright (C) 1996-2003 Russell King | |
5 | * Copyright (C) 2012 ARM Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #ifndef __ASM_PTRACE_H | |
20 | #define __ASM_PTRACE_H | |
21 | ||
4262a727 | 22 | #include <uapi/asm/ptrace.h> |
60ffc30d | 23 | |
60ffc30d | 24 | /* AArch32-specific ptrace requests */ |
27aa55c5 WD |
25 | #define COMPAT_PTRACE_GETREGS 12 |
26 | #define COMPAT_PTRACE_SETREGS 13 | |
27 | #define COMPAT_PTRACE_GET_THREAD_AREA 22 | |
28 | #define COMPAT_PTRACE_SET_SYSCALL 23 | |
60ffc30d CM |
29 | #define COMPAT_PTRACE_GETVFPREGS 27 |
30 | #define COMPAT_PTRACE_SETVFPREGS 28 | |
27aa55c5 WD |
31 | #define COMPAT_PTRACE_GETHBPREGS 29 |
32 | #define COMPAT_PTRACE_SETHBPREGS 30 | |
60ffc30d CM |
33 | #define COMPAT_PSR_MODE_USR 0x00000010 |
34 | #define COMPAT_PSR_T_BIT 0x00000020 | |
35 | #define COMPAT_PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */ | |
60ffc30d CM |
36 | /* |
37 | * These are 'magic' values for PTRACE_PEEKUSR that return info about where a | |
38 | * process is located in memory. | |
39 | */ | |
7606c37d CM |
40 | #define COMPAT_PT_TEXT_ADDR 0x10000 |
41 | #define COMPAT_PT_DATA_ADDR 0x10004 | |
42 | #define COMPAT_PT_TEXT_END_ADDR 0x10008 | |
60ffc30d CM |
43 | #ifndef __ASSEMBLY__ |
44 | ||
60ffc30d CM |
45 | /* sizeof(struct user) for AArch32 */ |
46 | #define COMPAT_USER_SZ 296 | |
47 | /* AArch32 uses x13 as the stack pointer... */ | |
48 | #define compat_sp regs[13] | |
49 | /* ... and x14 as the link register. */ | |
50 | #define compat_lr regs[14] | |
51 | ||
52 | /* | |
53 | * This struct defines the way the registers are stored on the stack during an | |
54 | * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for | |
55 | * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs. | |
56 | */ | |
57 | struct pt_regs { | |
58 | union { | |
59 | struct user_pt_regs user_regs; | |
60 | struct { | |
61 | u64 regs[31]; | |
62 | u64 sp; | |
63 | u64 pc; | |
64 | u64 pstate; | |
65 | }; | |
66 | }; | |
67 | u64 orig_x0; | |
68 | u64 syscallno; | |
69 | }; | |
70 | ||
71 | #define arch_has_single_step() (1) | |
72 | ||
73 | #ifdef CONFIG_COMPAT | |
74 | #define compat_thumb_mode(regs) \ | |
75 | (((regs)->pstate & COMPAT_PSR_T_BIT)) | |
76 | #else | |
77 | #define compat_thumb_mode(regs) (0) | |
78 | #endif | |
79 | ||
80 | #define user_mode(regs) \ | |
81 | (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t) | |
82 | ||
83 | #define compat_user_mode(regs) \ | |
84 | (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \ | |
85 | (PSR_MODE32_BIT | PSR_MODE_EL0t)) | |
86 | ||
87 | #define processor_mode(regs) \ | |
88 | ((regs)->pstate & PSR_MODE_MASK) | |
89 | ||
90 | #define interrupts_enabled(regs) \ | |
91 | (!((regs)->pstate & PSR_I_BIT)) | |
92 | ||
93 | #define fast_interrupts_enabled(regs) \ | |
94 | (!((regs)->pstate & PSR_F_BIT)) | |
95 | ||
96 | #define user_stack_pointer(regs) \ | |
97 | ((regs)->sp) | |
98 | ||
99 | /* | |
100 | * Are the current registers suitable for user mode? (used to maintain | |
101 | * security in signal handlers) | |
102 | */ | |
103 | static inline int valid_user_regs(struct user_pt_regs *regs) | |
104 | { | |
105 | if (user_mode(regs) && (regs->pstate & PSR_I_BIT) == 0) { | |
106 | regs->pstate &= ~(PSR_F_BIT | PSR_A_BIT); | |
107 | ||
108 | /* The T bit is reserved for AArch64 */ | |
109 | if (!(regs->pstate & PSR_MODE32_BIT)) | |
110 | regs->pstate &= ~COMPAT_PSR_T_BIT; | |
111 | ||
112 | return 1; | |
113 | } | |
114 | ||
115 | /* | |
116 | * Force PSR to something logical... | |
117 | */ | |
118 | regs->pstate &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | \ | |
119 | COMPAT_PSR_T_BIT | PSR_MODE32_BIT; | |
120 | ||
121 | if (!(regs->pstate & PSR_MODE32_BIT)) { | |
122 | regs->pstate &= ~COMPAT_PSR_T_BIT; | |
123 | regs->pstate |= PSR_MODE_EL0t; | |
124 | } | |
125 | ||
126 | return 0; | |
127 | } | |
128 | ||
129 | #define instruction_pointer(regs) (regs)->pc | |
130 | ||
131 | #ifdef CONFIG_SMP | |
132 | extern unsigned long profile_pc(struct pt_regs *regs); | |
133 | #else | |
134 | #define profile_pc(regs) instruction_pointer(regs) | |
135 | #endif | |
136 | ||
137 | extern int aarch32_break_trap(struct pt_regs *regs); | |
138 | ||
60ffc30d | 139 | #endif /* __ASSEMBLY__ */ |
60ffc30d | 140 | #endif |