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60ffc30d CM |
1 | /* |
2 | * Based on arch/arm/include/asm/ptrace.h | |
3 | * | |
4 | * Copyright (C) 1996-2003 Russell King | |
5 | * Copyright (C) 2012 ARM Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #ifndef __ASM_PTRACE_H | |
20 | #define __ASM_PTRACE_H | |
21 | ||
4262a727 | 22 | #include <uapi/asm/ptrace.h> |
60ffc30d | 23 | |
974c8e45 MZ |
24 | /* Current Exception Level values, as contained in CurrentEL */ |
25 | #define CurrentEL_EL1 (1 << 2) | |
26 | #define CurrentEL_EL2 (2 << 2) | |
27 | ||
e4e11cc0 CD |
28 | /* Additional SPSR bits not exposed in the UABI */ |
29 | #define PSR_IL_BIT (1 << 20) | |
30 | ||
60ffc30d | 31 | /* AArch32-specific ptrace requests */ |
27aa55c5 WD |
32 | #define COMPAT_PTRACE_GETREGS 12 |
33 | #define COMPAT_PTRACE_SETREGS 13 | |
34 | #define COMPAT_PTRACE_GET_THREAD_AREA 22 | |
35 | #define COMPAT_PTRACE_SET_SYSCALL 23 | |
60ffc30d CM |
36 | #define COMPAT_PTRACE_GETVFPREGS 27 |
37 | #define COMPAT_PTRACE_SETVFPREGS 28 | |
27aa55c5 WD |
38 | #define COMPAT_PTRACE_GETHBPREGS 29 |
39 | #define COMPAT_PTRACE_SETHBPREGS 30 | |
9ec218b8 | 40 | |
25086263 MR |
41 | /* SPSR_ELx bits for exceptions taken from AArch32 */ |
42 | #define PSR_AA32_MODE_MASK 0x0000001f | |
43 | #define PSR_AA32_MODE_USR 0x00000010 | |
44 | #define PSR_AA32_MODE_FIQ 0x00000011 | |
45 | #define PSR_AA32_MODE_IRQ 0x00000012 | |
46 | #define PSR_AA32_MODE_SVC 0x00000013 | |
47 | #define PSR_AA32_MODE_ABT 0x00000017 | |
48 | #define PSR_AA32_MODE_HYP 0x0000001a | |
49 | #define PSR_AA32_MODE_UND 0x0000001b | |
50 | #define PSR_AA32_MODE_SYS 0x0000001f | |
51 | #define PSR_AA32_T_BIT 0x00000020 | |
52 | #define PSR_AA32_F_BIT 0x00000040 | |
53 | #define PSR_AA32_I_BIT 0x00000080 | |
54 | #define PSR_AA32_A_BIT 0x00000100 | |
55 | #define PSR_AA32_E_BIT 0x00000200 | |
8f04e8e6 | 56 | #define PSR_AA32_SSBS_BIT 0x00800000 |
25086263 MR |
57 | #define PSR_AA32_DIT_BIT 0x01000000 |
58 | #define PSR_AA32_Q_BIT 0x08000000 | |
59 | #define PSR_AA32_V_BIT 0x10000000 | |
60 | #define PSR_AA32_C_BIT 0x20000000 | |
61 | #define PSR_AA32_Z_BIT 0x40000000 | |
62 | #define PSR_AA32_N_BIT 0x80000000 | |
63 | #define PSR_AA32_IT_MASK 0x0600fc00 /* If-Then execution state mask */ | |
64 | #define PSR_AA32_GE_MASK 0x000f0000 | |
65 | ||
66 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
67 | #define PSR_AA32_ENDSTATE PSR_AA32_E_BIT | |
68 | #else | |
69 | #define PSR_AA32_ENDSTATE 0 | |
70 | #endif | |
71 | ||
72 | /* AArch32 CPSR bits, as seen in AArch32 */ | |
25086263 | 73 | #define COMPAT_PSR_DIT_BIT 0x00200000 |
2d888f48 | 74 | |
60ffc30d CM |
75 | /* |
76 | * These are 'magic' values for PTRACE_PEEKUSR that return info about where a | |
77 | * process is located in memory. | |
78 | */ | |
7606c37d CM |
79 | #define COMPAT_PT_TEXT_ADDR 0x10000 |
80 | #define COMPAT_PT_DATA_ADDR 0x10004 | |
81 | #define COMPAT_PT_TEXT_END_ADDR 0x10008 | |
17c28958 DM |
82 | |
83 | /* | |
84 | * If pt_regs.syscallno == NO_SYSCALL, then the thread is not executing | |
85 | * a syscall -- i.e., its most recent entry into the kernel from | |
86 | * userspace was not via SVC, or otherwise a tracer cancelled the syscall. | |
87 | * | |
88 | * This must have the value -1, for ABI compatibility with ptrace etc. | |
89 | */ | |
90 | #define NO_SYSCALL (-1) | |
91 | ||
60ffc30d | 92 | #ifndef __ASSEMBLY__ |
0a8ea52c | 93 | #include <linux/bug.h> |
17c28958 | 94 | #include <linux/types.h> |
60ffc30d | 95 | |
60ffc30d CM |
96 | /* sizeof(struct user) for AArch32 */ |
97 | #define COMPAT_USER_SZ 296 | |
88483ec6 MZ |
98 | |
99 | /* Architecturally defined mapping between AArch32 and AArch64 registers */ | |
100 | #define compat_usr(x) regs[(x)] | |
2ee0d7fd | 101 | #define compat_fp regs[11] |
60ffc30d | 102 | #define compat_sp regs[13] |
60ffc30d | 103 | #define compat_lr regs[14] |
88483ec6 | 104 | #define compat_sp_hyp regs[15] |
5accd17d RM |
105 | #define compat_lr_irq regs[16] |
106 | #define compat_sp_irq regs[17] | |
107 | #define compat_lr_svc regs[18] | |
108 | #define compat_sp_svc regs[19] | |
109 | #define compat_lr_abt regs[20] | |
110 | #define compat_sp_abt regs[21] | |
111 | #define compat_lr_und regs[22] | |
112 | #define compat_sp_und regs[23] | |
88483ec6 MZ |
113 | #define compat_r8_fiq regs[24] |
114 | #define compat_r9_fiq regs[25] | |
115 | #define compat_r10_fiq regs[26] | |
116 | #define compat_r11_fiq regs[27] | |
117 | #define compat_r12_fiq regs[28] | |
118 | #define compat_sp_fiq regs[29] | |
119 | #define compat_lr_fiq regs[30] | |
60ffc30d | 120 | |
25086263 MR |
121 | static inline unsigned long compat_psr_to_pstate(const unsigned long psr) |
122 | { | |
123 | unsigned long pstate; | |
124 | ||
125 | pstate = psr & ~COMPAT_PSR_DIT_BIT; | |
126 | ||
127 | if (psr & COMPAT_PSR_DIT_BIT) | |
128 | pstate |= PSR_AA32_DIT_BIT; | |
129 | ||
130 | return pstate; | |
131 | } | |
132 | ||
133 | static inline unsigned long pstate_to_compat_psr(const unsigned long pstate) | |
134 | { | |
135 | unsigned long psr; | |
136 | ||
137 | psr = pstate & ~PSR_AA32_DIT_BIT; | |
138 | ||
139 | if (pstate & PSR_AA32_DIT_BIT) | |
140 | psr |= COMPAT_PSR_DIT_BIT; | |
141 | ||
142 | return psr; | |
143 | } | |
144 | ||
60ffc30d CM |
145 | /* |
146 | * This struct defines the way the registers are stored on the stack during an | |
147 | * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for | |
148 | * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs. | |
149 | */ | |
150 | struct pt_regs { | |
151 | union { | |
152 | struct user_pt_regs user_regs; | |
153 | struct { | |
154 | u64 regs[31]; | |
155 | u64 sp; | |
156 | u64 pc; | |
157 | u64 pstate; | |
158 | }; | |
159 | }; | |
160 | u64 orig_x0; | |
35d0e6fb DM |
161 | #ifdef __AARCH64EB__ |
162 | u32 unused2; | |
163 | s32 syscallno; | |
164 | #else | |
165 | s32 syscallno; | |
166 | u32 unused2; | |
167 | #endif | |
168 | ||
e19a6ee2 JM |
169 | u64 orig_addr_limit; |
170 | u64 unused; // maintain 16 byte alignment | |
73267498 | 171 | u64 stackframe[2]; |
60ffc30d CM |
172 | }; |
173 | ||
17c28958 DM |
174 | static inline bool in_syscall(struct pt_regs const *regs) |
175 | { | |
176 | return regs->syscallno != NO_SYSCALL; | |
177 | } | |
178 | ||
179 | static inline void forget_syscall(struct pt_regs *regs) | |
180 | { | |
181 | regs->syscallno = NO_SYSCALL; | |
182 | } | |
183 | ||
0a8ea52c DL |
184 | #define MAX_REG_OFFSET offsetof(struct pt_regs, pstate) |
185 | ||
60ffc30d CM |
186 | #define arch_has_single_step() (1) |
187 | ||
188 | #ifdef CONFIG_COMPAT | |
189 | #define compat_thumb_mode(regs) \ | |
d64567f6 | 190 | (((regs)->pstate & PSR_AA32_T_BIT)) |
60ffc30d CM |
191 | #else |
192 | #define compat_thumb_mode(regs) (0) | |
193 | #endif | |
194 | ||
195 | #define user_mode(regs) \ | |
196 | (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t) | |
197 | ||
198 | #define compat_user_mode(regs) \ | |
199 | (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \ | |
200 | (PSR_MODE32_BIT | PSR_MODE_EL0t)) | |
201 | ||
202 | #define processor_mode(regs) \ | |
203 | ((regs)->pstate & PSR_MODE_MASK) | |
204 | ||
205 | #define interrupts_enabled(regs) \ | |
206 | (!((regs)->pstate & PSR_I_BIT)) | |
207 | ||
208 | #define fast_interrupts_enabled(regs) \ | |
209 | (!((regs)->pstate & PSR_F_BIT)) | |
210 | ||
2dd0e8d2 | 211 | #define GET_USP(regs) \ |
2520d039 | 212 | (!compat_user_mode(regs) ? (regs)->sp : (regs)->compat_sp) |
60ffc30d | 213 | |
2dd0e8d2 SP |
214 | #define SET_USP(ptregs, value) \ |
215 | (!compat_user_mode(regs) ? ((regs)->sp = value) : ((regs)->compat_sp = value)) | |
216 | ||
0a8ea52c | 217 | extern int regs_query_register_offset(const char *name); |
0a8ea52c DL |
218 | extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, |
219 | unsigned int n); | |
220 | ||
221 | /** | |
222 | * regs_get_register() - get register value from its offset | |
223 | * @regs: pt_regs from which register value is gotten | |
224 | * @offset: offset of the register. | |
225 | * | |
226 | * regs_get_register returns the value of a register whose offset from @regs. | |
227 | * The @offset is the offset of the register in struct pt_regs. | |
228 | * If @offset is bigger than MAX_REG_OFFSET, this returns 0. | |
229 | */ | |
230 | static inline u64 regs_get_register(struct pt_regs *regs, unsigned int offset) | |
231 | { | |
232 | u64 val = 0; | |
233 | ||
234 | WARN_ON(offset & 7); | |
235 | ||
236 | offset >>= 3; | |
237 | switch (offset) { | |
238 | case 0 ... 30: | |
239 | val = regs->regs[offset]; | |
240 | break; | |
241 | case offsetof(struct pt_regs, sp) >> 3: | |
242 | val = regs->sp; | |
243 | break; | |
244 | case offsetof(struct pt_regs, pc) >> 3: | |
245 | val = regs->pc; | |
246 | break; | |
247 | case offsetof(struct pt_regs, pstate) >> 3: | |
248 | val = regs->pstate; | |
249 | break; | |
250 | default: | |
251 | val = 0; | |
252 | } | |
253 | ||
254 | return val; | |
255 | } | |
256 | ||
6c23e2ff MR |
257 | /* |
258 | * Read a register given an architectural register index r. | |
259 | * This handles the common case where 31 means XZR, not SP. | |
260 | */ | |
261 | static inline unsigned long pt_regs_read_reg(const struct pt_regs *regs, int r) | |
262 | { | |
263 | return (r == 31) ? 0 : regs->regs[r]; | |
264 | } | |
265 | ||
266 | /* | |
267 | * Write a register given an architectural register index r. | |
268 | * This handles the common case where 31 means XZR, not SP. | |
269 | */ | |
270 | static inline void pt_regs_write_reg(struct pt_regs *regs, int r, | |
271 | unsigned long val) | |
272 | { | |
273 | if (r != 31) | |
274 | regs->regs[r] = val; | |
275 | } | |
276 | ||
0a8ea52c DL |
277 | /* Valid only for Kernel mode traps. */ |
278 | static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) | |
279 | { | |
280 | return regs->sp; | |
281 | } | |
282 | ||
d34a3ebd AT |
283 | static inline unsigned long regs_return_value(struct pt_regs *regs) |
284 | { | |
285 | return regs->regs[0]; | |
286 | } | |
287 | ||
dbd4d7ca MR |
288 | /* We must avoid circular header include via sched.h */ |
289 | struct task_struct; | |
290 | int valid_user_regs(struct user_pt_regs *regs, struct task_struct *task); | |
60ffc30d | 291 | |
2dd0e8d2 SP |
292 | #define GET_IP(regs) ((unsigned long)(regs)->pc) |
293 | #define SET_IP(regs, value) ((regs)->pc = ((u64) (value))) | |
294 | ||
295 | #define GET_FP(ptregs) ((unsigned long)(ptregs)->regs[29]) | |
296 | #define SET_FP(ptregs, value) ((ptregs)->regs[29] = ((u64) (value))) | |
297 | ||
298 | #include <asm-generic/ptrace.h> | |
60ffc30d | 299 | |
9842ceae PA |
300 | #define procedure_link_pointer(regs) ((regs)->regs[30]) |
301 | ||
302 | static inline void procedure_link_pointer_set(struct pt_regs *regs, | |
303 | unsigned long val) | |
304 | { | |
305 | procedure_link_pointer(regs) = val; | |
306 | } | |
307 | ||
2dd0e8d2 | 308 | #undef profile_pc |
60ffc30d | 309 | extern unsigned long profile_pc(struct pt_regs *regs); |
60ffc30d | 310 | |
60ffc30d | 311 | #endif /* __ASSEMBLY__ */ |
60ffc30d | 312 | #endif |