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caab277b | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
60ffc30d CM |
2 | /* |
3 | * Based on arch/arm/include/asm/ptrace.h | |
4 | * | |
5 | * Copyright (C) 1996-2003 Russell King | |
6 | * Copyright (C) 2012 ARM Ltd. | |
60ffc30d CM |
7 | */ |
8 | #ifndef __ASM_PTRACE_H | |
9 | #define __ASM_PTRACE_H | |
10 | ||
133d0518 JT |
11 | #include <asm/cpufeature.h> |
12 | ||
4262a727 | 13 | #include <uapi/asm/ptrace.h> |
60ffc30d | 14 | |
974c8e45 MZ |
15 | /* Current Exception Level values, as contained in CurrentEL */ |
16 | #define CurrentEL_EL1 (1 << 2) | |
17 | #define CurrentEL_EL2 (2 << 2) | |
18 | ||
d87a8e65 MR |
19 | #define INIT_PSTATE_EL1 \ |
20 | (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL1h) | |
21 | #define INIT_PSTATE_EL2 \ | |
22 | (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL2h) | |
23 | ||
cdbc81dd JT |
24 | /* |
25 | * PMR values used to mask/unmask interrupts. | |
26 | * | |
27 | * GIC priority masking works as follows: if an IRQ's priority is a higher value | |
28 | * than the value held in PMR, that IRQ is masked. Lowering the value of PMR | |
29 | * means masking more IRQs (or at least that the same IRQs remain masked). | |
30 | * | |
31 | * To mask interrupts, we clear the most significant bit of PMR. | |
bd82d4bd JT |
32 | * |
33 | * Some code sections either automatically switch back to PSR.I or explicitly | |
34 | * require to not use priority masking. If bit GIC_PRIO_PSR_I_SET is included | |
c4b5abba | 35 | * in the priority mask, it indicates that PSR.I should be set and |
bd82d4bd | 36 | * interrupt disabling temporarily does not rely on IRQ priorities. |
cdbc81dd | 37 | */ |
677379bc | 38 | #define GIC_PRIO_IRQON 0xe0 |
33678059 AE |
39 | #define __GIC_PRIO_IRQOFF (GIC_PRIO_IRQON & ~0x80) |
40 | #define __GIC_PRIO_IRQOFF_NS 0xa0 | |
bd82d4bd | 41 | #define GIC_PRIO_PSR_I_SET (1 << 4) |
cdbc81dd | 42 | |
33678059 AE |
43 | #define GIC_PRIO_IRQOFF \ |
44 | ({ \ | |
45 | extern struct static_key_false gic_nonsecure_priorities;\ | |
46 | u8 __prio = __GIC_PRIO_IRQOFF; \ | |
47 | \ | |
48 | if (static_branch_unlikely(&gic_nonsecure_priorities)) \ | |
49 | __prio = __GIC_PRIO_IRQOFF_NS; \ | |
50 | \ | |
51 | __prio; \ | |
52 | }) | |
53 | ||
e4e11cc0 | 54 | /* Additional SPSR bits not exposed in the UABI */ |
d9d7d84d | 55 | #define PSR_MODE_THREAD_BIT (1 << 0) |
e4e11cc0 CD |
56 | #define PSR_IL_BIT (1 << 20) |
57 | ||
60ffc30d | 58 | /* AArch32-specific ptrace requests */ |
27aa55c5 WD |
59 | #define COMPAT_PTRACE_GETREGS 12 |
60 | #define COMPAT_PTRACE_SETREGS 13 | |
61 | #define COMPAT_PTRACE_GET_THREAD_AREA 22 | |
62 | #define COMPAT_PTRACE_SET_SYSCALL 23 | |
60ffc30d CM |
63 | #define COMPAT_PTRACE_GETVFPREGS 27 |
64 | #define COMPAT_PTRACE_SETVFPREGS 28 | |
27aa55c5 WD |
65 | #define COMPAT_PTRACE_GETHBPREGS 29 |
66 | #define COMPAT_PTRACE_SETHBPREGS 30 | |
9ec218b8 | 67 | |
25086263 MR |
68 | /* SPSR_ELx bits for exceptions taken from AArch32 */ |
69 | #define PSR_AA32_MODE_MASK 0x0000001f | |
70 | #define PSR_AA32_MODE_USR 0x00000010 | |
71 | #define PSR_AA32_MODE_FIQ 0x00000011 | |
72 | #define PSR_AA32_MODE_IRQ 0x00000012 | |
73 | #define PSR_AA32_MODE_SVC 0x00000013 | |
74 | #define PSR_AA32_MODE_ABT 0x00000017 | |
75 | #define PSR_AA32_MODE_HYP 0x0000001a | |
76 | #define PSR_AA32_MODE_UND 0x0000001b | |
77 | #define PSR_AA32_MODE_SYS 0x0000001f | |
78 | #define PSR_AA32_T_BIT 0x00000020 | |
79 | #define PSR_AA32_F_BIT 0x00000040 | |
80 | #define PSR_AA32_I_BIT 0x00000080 | |
81 | #define PSR_AA32_A_BIT 0x00000100 | |
82 | #define PSR_AA32_E_BIT 0x00000200 | |
3c2483f1 | 83 | #define PSR_AA32_PAN_BIT 0x00400000 |
8f04e8e6 | 84 | #define PSR_AA32_SSBS_BIT 0x00800000 |
25086263 MR |
85 | #define PSR_AA32_DIT_BIT 0x01000000 |
86 | #define PSR_AA32_Q_BIT 0x08000000 | |
87 | #define PSR_AA32_V_BIT 0x10000000 | |
88 | #define PSR_AA32_C_BIT 0x20000000 | |
89 | #define PSR_AA32_Z_BIT 0x40000000 | |
90 | #define PSR_AA32_N_BIT 0x80000000 | |
91 | #define PSR_AA32_IT_MASK 0x0600fc00 /* If-Then execution state mask */ | |
92 | #define PSR_AA32_GE_MASK 0x000f0000 | |
93 | ||
94 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
95 | #define PSR_AA32_ENDSTATE PSR_AA32_E_BIT | |
96 | #else | |
97 | #define PSR_AA32_ENDSTATE 0 | |
98 | #endif | |
99 | ||
100 | /* AArch32 CPSR bits, as seen in AArch32 */ | |
25086263 | 101 | #define COMPAT_PSR_DIT_BIT 0x00200000 |
2d888f48 | 102 | |
60ffc30d CM |
103 | /* |
104 | * These are 'magic' values for PTRACE_PEEKUSR that return info about where a | |
105 | * process is located in memory. | |
106 | */ | |
7606c37d CM |
107 | #define COMPAT_PT_TEXT_ADDR 0x10000 |
108 | #define COMPAT_PT_DATA_ADDR 0x10004 | |
109 | #define COMPAT_PT_TEXT_END_ADDR 0x10008 | |
17c28958 DM |
110 | |
111 | /* | |
112 | * If pt_regs.syscallno == NO_SYSCALL, then the thread is not executing | |
113 | * a syscall -- i.e., its most recent entry into the kernel from | |
114 | * userspace was not via SVC, or otherwise a tracer cancelled the syscall. | |
115 | * | |
116 | * This must have the value -1, for ABI compatibility with ptrace etc. | |
117 | */ | |
118 | #define NO_SYSCALL (-1) | |
119 | ||
60ffc30d | 120 | #ifndef __ASSEMBLY__ |
0a8ea52c | 121 | #include <linux/bug.h> |
17c28958 | 122 | #include <linux/types.h> |
60ffc30d | 123 | |
60ffc30d CM |
124 | /* sizeof(struct user) for AArch32 */ |
125 | #define COMPAT_USER_SZ 296 | |
88483ec6 MZ |
126 | |
127 | /* Architecturally defined mapping between AArch32 and AArch64 registers */ | |
128 | #define compat_usr(x) regs[(x)] | |
2ee0d7fd | 129 | #define compat_fp regs[11] |
60ffc30d | 130 | #define compat_sp regs[13] |
60ffc30d | 131 | #define compat_lr regs[14] |
88483ec6 | 132 | #define compat_sp_hyp regs[15] |
5accd17d RM |
133 | #define compat_lr_irq regs[16] |
134 | #define compat_sp_irq regs[17] | |
135 | #define compat_lr_svc regs[18] | |
136 | #define compat_sp_svc regs[19] | |
137 | #define compat_lr_abt regs[20] | |
138 | #define compat_sp_abt regs[21] | |
139 | #define compat_lr_und regs[22] | |
140 | #define compat_sp_und regs[23] | |
88483ec6 MZ |
141 | #define compat_r8_fiq regs[24] |
142 | #define compat_r9_fiq regs[25] | |
143 | #define compat_r10_fiq regs[26] | |
144 | #define compat_r11_fiq regs[27] | |
145 | #define compat_r12_fiq regs[28] | |
146 | #define compat_sp_fiq regs[29] | |
147 | #define compat_lr_fiq regs[30] | |
60ffc30d | 148 | |
25086263 MR |
149 | static inline unsigned long compat_psr_to_pstate(const unsigned long psr) |
150 | { | |
151 | unsigned long pstate; | |
152 | ||
153 | pstate = psr & ~COMPAT_PSR_DIT_BIT; | |
154 | ||
155 | if (psr & COMPAT_PSR_DIT_BIT) | |
156 | pstate |= PSR_AA32_DIT_BIT; | |
157 | ||
158 | return pstate; | |
159 | } | |
160 | ||
161 | static inline unsigned long pstate_to_compat_psr(const unsigned long pstate) | |
162 | { | |
163 | unsigned long psr; | |
164 | ||
165 | psr = pstate & ~PSR_AA32_DIT_BIT; | |
166 | ||
167 | if (pstate & PSR_AA32_DIT_BIT) | |
168 | psr |= COMPAT_PSR_DIT_BIT; | |
169 | ||
170 | return psr; | |
171 | } | |
172 | ||
60ffc30d CM |
173 | /* |
174 | * This struct defines the way the registers are stored on the stack during an | |
175 | * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for | |
176 | * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs. | |
177 | */ | |
178 | struct pt_regs { | |
179 | union { | |
180 | struct user_pt_regs user_regs; | |
181 | struct { | |
182 | u64 regs[31]; | |
183 | u64 sp; | |
184 | u64 pc; | |
185 | u64 pstate; | |
186 | }; | |
187 | }; | |
188 | u64 orig_x0; | |
35d0e6fb DM |
189 | #ifdef __AARCH64EB__ |
190 | u32 unused2; | |
191 | s32 syscallno; | |
192 | #else | |
193 | s32 syscallno; | |
194 | u32 unused2; | |
195 | #endif | |
3d2403fd | 196 | u64 sdei_ttbr1; |
133d0518 JT |
197 | /* Only valid when ARM64_HAS_IRQ_PRIO_MASKING is enabled. */ |
198 | u64 pmr_save; | |
73267498 | 199 | u64 stackframe[2]; |
60ffc30d CM |
200 | }; |
201 | ||
17c28958 DM |
202 | static inline bool in_syscall(struct pt_regs const *regs) |
203 | { | |
204 | return regs->syscallno != NO_SYSCALL; | |
205 | } | |
206 | ||
207 | static inline void forget_syscall(struct pt_regs *regs) | |
208 | { | |
209 | regs->syscallno = NO_SYSCALL; | |
210 | } | |
211 | ||
0a8ea52c DL |
212 | #define MAX_REG_OFFSET offsetof(struct pt_regs, pstate) |
213 | ||
60ffc30d CM |
214 | #define arch_has_single_step() (1) |
215 | ||
216 | #ifdef CONFIG_COMPAT | |
217 | #define compat_thumb_mode(regs) \ | |
d64567f6 | 218 | (((regs)->pstate & PSR_AA32_T_BIT)) |
60ffc30d CM |
219 | #else |
220 | #define compat_thumb_mode(regs) (0) | |
221 | #endif | |
222 | ||
223 | #define user_mode(regs) \ | |
224 | (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t) | |
225 | ||
226 | #define compat_user_mode(regs) \ | |
227 | (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \ | |
228 | (PSR_MODE32_BIT | PSR_MODE_EL0t)) | |
229 | ||
230 | #define processor_mode(regs) \ | |
231 | ((regs)->pstate & PSR_MODE_MASK) | |
232 | ||
133d0518 JT |
233 | #define irqs_priority_unmasked(regs) \ |
234 | (system_uses_irq_prio_masking() ? \ | |
235 | (regs)->pmr_save == GIC_PRIO_IRQON : \ | |
236 | true) | |
237 | ||
238 | #define interrupts_enabled(regs) \ | |
239 | (!((regs)->pstate & PSR_I_BIT) && irqs_priority_unmasked(regs)) | |
60ffc30d CM |
240 | |
241 | #define fast_interrupts_enabled(regs) \ | |
242 | (!((regs)->pstate & PSR_F_BIT)) | |
243 | ||
56a5d003 CH |
244 | static inline unsigned long user_stack_pointer(struct pt_regs *regs) |
245 | { | |
246 | if (compat_user_mode(regs)) | |
247 | return regs->compat_sp; | |
248 | return regs->sp; | |
249 | } | |
2dd0e8d2 | 250 | |
0a8ea52c | 251 | extern int regs_query_register_offset(const char *name); |
0a8ea52c DL |
252 | extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, |
253 | unsigned int n); | |
254 | ||
255 | /** | |
256 | * regs_get_register() - get register value from its offset | |
257 | * @regs: pt_regs from which register value is gotten | |
258 | * @offset: offset of the register. | |
259 | * | |
260 | * regs_get_register returns the value of a register whose offset from @regs. | |
261 | * The @offset is the offset of the register in struct pt_regs. | |
262 | * If @offset is bigger than MAX_REG_OFFSET, this returns 0. | |
263 | */ | |
264 | static inline u64 regs_get_register(struct pt_regs *regs, unsigned int offset) | |
265 | { | |
266 | u64 val = 0; | |
267 | ||
268 | WARN_ON(offset & 7); | |
269 | ||
270 | offset >>= 3; | |
271 | switch (offset) { | |
272 | case 0 ... 30: | |
273 | val = regs->regs[offset]; | |
274 | break; | |
275 | case offsetof(struct pt_regs, sp) >> 3: | |
276 | val = regs->sp; | |
277 | break; | |
278 | case offsetof(struct pt_regs, pc) >> 3: | |
279 | val = regs->pc; | |
280 | break; | |
281 | case offsetof(struct pt_regs, pstate) >> 3: | |
282 | val = regs->pstate; | |
283 | break; | |
284 | default: | |
285 | val = 0; | |
286 | } | |
287 | ||
288 | return val; | |
289 | } | |
290 | ||
6c23e2ff MR |
291 | /* |
292 | * Read a register given an architectural register index r. | |
293 | * This handles the common case where 31 means XZR, not SP. | |
294 | */ | |
295 | static inline unsigned long pt_regs_read_reg(const struct pt_regs *regs, int r) | |
296 | { | |
297 | return (r == 31) ? 0 : regs->regs[r]; | |
298 | } | |
299 | ||
300 | /* | |
301 | * Write a register given an architectural register index r. | |
302 | * This handles the common case where 31 means XZR, not SP. | |
303 | */ | |
304 | static inline void pt_regs_write_reg(struct pt_regs *regs, int r, | |
305 | unsigned long val) | |
306 | { | |
307 | if (r != 31) | |
308 | regs->regs[r] = val; | |
309 | } | |
310 | ||
0a8ea52c DL |
311 | /* Valid only for Kernel mode traps. */ |
312 | static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) | |
313 | { | |
314 | return regs->sp; | |
315 | } | |
316 | ||
d34a3ebd AT |
317 | static inline unsigned long regs_return_value(struct pt_regs *regs) |
318 | { | |
319 | return regs->regs[0]; | |
320 | } | |
321 | ||
42d038c4 LY |
322 | static inline void regs_set_return_value(struct pt_regs *regs, unsigned long rc) |
323 | { | |
324 | regs->regs[0] = rc; | |
325 | } | |
326 | ||
a823c35f MH |
327 | /** |
328 | * regs_get_kernel_argument() - get Nth function argument in kernel | |
329 | * @regs: pt_regs of that context | |
330 | * @n: function argument number (start from 0) | |
331 | * | |
332 | * regs_get_argument() returns @n th argument of the function call. | |
333 | * | |
334 | * Note that this chooses the most likely register mapping. In very rare | |
335 | * cases this may not return correct data, for example, if one of the | |
336 | * function parameters is 16 bytes or bigger. In such cases, we cannot | |
337 | * get access the parameter correctly and the register assignment of | |
338 | * subsequent parameters will be shifted. | |
339 | */ | |
340 | static inline unsigned long regs_get_kernel_argument(struct pt_regs *regs, | |
341 | unsigned int n) | |
342 | { | |
343 | #define NR_REG_ARGUMENTS 8 | |
344 | if (n < NR_REG_ARGUMENTS) | |
345 | return pt_regs_read_reg(regs, n); | |
346 | return 0; | |
347 | } | |
348 | ||
dbd4d7ca MR |
349 | /* We must avoid circular header include via sched.h */ |
350 | struct task_struct; | |
351 | int valid_user_regs(struct user_pt_regs *regs, struct task_struct *task); | |
60ffc30d | 352 | |
56a5d003 CH |
353 | static inline unsigned long instruction_pointer(struct pt_regs *regs) |
354 | { | |
355 | return regs->pc; | |
356 | } | |
357 | static inline void instruction_pointer_set(struct pt_regs *regs, | |
358 | unsigned long val) | |
359 | { | |
360 | regs->pc = val; | |
361 | } | |
2dd0e8d2 | 362 | |
56a5d003 CH |
363 | static inline unsigned long frame_pointer(struct pt_regs *regs) |
364 | { | |
365 | return regs->regs[29]; | |
366 | } | |
60ffc30d | 367 | |
9842ceae PA |
368 | #define procedure_link_pointer(regs) ((regs)->regs[30]) |
369 | ||
370 | static inline void procedure_link_pointer_set(struct pt_regs *regs, | |
371 | unsigned long val) | |
372 | { | |
373 | procedure_link_pointer(regs) = val; | |
374 | } | |
375 | ||
60ffc30d | 376 | extern unsigned long profile_pc(struct pt_regs *regs); |
60ffc30d | 377 | |
60ffc30d | 378 | #endif /* __ASSEMBLY__ */ |
60ffc30d | 379 | #endif |