[linux-2.6-block.git] / arch / arm64 / include / asm / ptrace.h

/*
 * Based on arch/arm/include/asm/ptrace.h
 *
 * Copyright (C) 1996-2003 Russell King
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __ASM_PTRACE_H
#define __ASM_PTRACE_H

#include <uapi/asm/ptrace.h>

/* Current Exception Level values, as contained in CurrentEL */
#define CurrentEL_EL1		(1 << 2)
#define CurrentEL_EL2		(2 << 2)

/* AArch32-specific ptrace requests */
#define COMPAT_PTRACE_GETREGS		12
#define COMPAT_PTRACE_SETREGS		13
#define COMPAT_PTRACE_GET_THREAD_AREA	22
#define COMPAT_PTRACE_SET_SYSCALL	23
#define COMPAT_PTRACE_GETVFPREGS	27
#define COMPAT_PTRACE_SETVFPREGS	28
#define COMPAT_PTRACE_GETHBPREGS	29
#define COMPAT_PTRACE_SETHBPREGS	30

/* SPSR_ELx bits for exceptions taken from AArch32 */
#define PSR_AA32_MODE_MASK	0x0000001f
#define PSR_AA32_MODE_USR	0x00000010
#define PSR_AA32_MODE_FIQ	0x00000011
#define PSR_AA32_MODE_IRQ	0x00000012
#define PSR_AA32_MODE_SVC	0x00000013
#define PSR_AA32_MODE_ABT	0x00000017
#define PSR_AA32_MODE_HYP	0x0000001a
#define PSR_AA32_MODE_UND	0x0000001b
#define PSR_AA32_MODE_SYS	0x0000001f
#define PSR_AA32_T_BIT		0x00000020
#define PSR_AA32_F_BIT		0x00000040
#define PSR_AA32_I_BIT		0x00000080
#define PSR_AA32_A_BIT		0x00000100
#define PSR_AA32_E_BIT		0x00000200
#define PSR_AA32_DIT_BIT	0x01000000
#define PSR_AA32_Q_BIT		0x08000000
#define PSR_AA32_V_BIT		0x10000000
#define PSR_AA32_C_BIT		0x20000000
#define PSR_AA32_Z_BIT		0x40000000
#define PSR_AA32_N_BIT		0x80000000
#define PSR_AA32_IT_MASK	0x0600fc00	/* If-Then execution state mask */
#define PSR_AA32_GE_MASK	0x000f0000

#ifdef CONFIG_CPU_BIG_ENDIAN
#define PSR_AA32_ENDSTATE	PSR_AA32_E_BIT
#else
#define PSR_AA32_ENDSTATE	0
#endif

/* AArch32 CPSR bits, as seen in AArch32 */
#define COMPAT_PSR_DIT_BIT	0x00200000

/*
 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
 * process is located in memory.
 */
#define COMPAT_PT_TEXT_ADDR		0x10000
#define COMPAT_PT_DATA_ADDR		0x10004
#define COMPAT_PT_TEXT_END_ADDR		0x10008

/*
 * If pt_regs.syscallno == NO_SYSCALL, then the thread is not executing
 * a syscall -- i.e., its most recent entry into the kernel from
 * userspace was not via SVC, or otherwise a tracer cancelled the syscall.
 *
 * This must have the value -1, for ABI compatibility with ptrace etc.
 */
#define NO_SYSCALL (-1)

#ifndef __ASSEMBLY__
#include <linux/bug.h>
#include <linux/types.h>

/* sizeof(struct user) for AArch32 */
#define COMPAT_USER_SZ	296

/* Architecturally defined mapping between AArch32 and AArch64 registers */
#define compat_usr(x)	regs[(x)]
#define compat_fp	regs[11]
#define compat_sp	regs[13]
#define compat_lr	regs[14]
#define compat_sp_hyp	regs[15]
#define compat_lr_irq	regs[16]
#define compat_sp_irq	regs[17]
#define compat_lr_svc	regs[18]
#define compat_sp_svc	regs[19]
#define compat_lr_abt	regs[20]
#define compat_sp_abt	regs[21]
#define compat_lr_und	regs[22]
#define compat_sp_und	regs[23]
#define compat_r8_fiq	regs[24]
#define compat_r9_fiq	regs[25]
#define compat_r10_fiq	regs[26]
#define compat_r11_fiq	regs[27]
#define compat_r12_fiq	regs[28]
#define compat_sp_fiq	regs[29]
#define compat_lr_fiq	regs[30]

static inline unsigned long compat_psr_to_pstate(const unsigned long psr)
{
	unsigned long pstate;

	pstate = psr & ~COMPAT_PSR_DIT_BIT;

	if (psr & COMPAT_PSR_DIT_BIT)
		pstate |= PSR_AA32_DIT_BIT;

	return pstate;
}

static inline unsigned long pstate_to_compat_psr(const unsigned long pstate)
{
	unsigned long psr;

	psr = pstate & ~PSR_AA32_DIT_BIT;

	if (pstate & PSR_AA32_DIT_BIT)
		psr |= COMPAT_PSR_DIT_BIT;

	return psr;
}

/*
 * This struct defines the way the registers are stored on the stack during an
 * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for
 * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs.
 */
struct pt_regs {
	union {
		struct user_pt_regs user_regs;
		struct {
			u64 regs[31];
			u64 sp;
			u64 pc;
			u64 pstate;
		};
	};
	u64 orig_x0;
#ifdef __AARCH64EB__
	u32 unused2;
	s32 syscallno;
#else
	s32 syscallno;
	u32 unused2;
#endif

	u64 orig_addr_limit;
	u64 unused;	// maintain 16 byte alignment
	u64 stackframe[2];
};

static inline bool in_syscall(struct pt_regs const *regs)
{
	return regs->syscallno != NO_SYSCALL;
}

static inline void forget_syscall(struct pt_regs *regs)
{
	regs->syscallno = NO_SYSCALL;
}

#define MAX_REG_OFFSET offsetof(struct pt_regs, pstate)

#define arch_has_single_step()	(1)

#ifdef CONFIG_COMPAT
#define compat_thumb_mode(regs) \
	(((regs)->pstate & PSR_AA32_T_BIT))
#else
#define compat_thumb_mode(regs) (0)
#endif

#define user_mode(regs)	\
	(((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t)

#define compat_user_mode(regs)	\
	(((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \
	 (PSR_MODE32_BIT | PSR_MODE_EL0t))

#define processor_mode(regs) \
	((regs)->pstate & PSR_MODE_MASK)

#define interrupts_enabled(regs) \
	(!((regs)->pstate & PSR_I_BIT))

#define fast_interrupts_enabled(regs) \
	(!((regs)->pstate & PSR_F_BIT))

#define GET_USP(regs) \
	(!compat_user_mode(regs) ? (regs)->sp : (regs)->compat_sp)

#define SET_USP(ptregs, value) \
	(!compat_user_mode(regs) ? ((regs)->sp = value) : ((regs)->compat_sp = value))

extern int regs_query_register_offset(const char *name);
extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
					       unsigned int n);

/**
 * regs_get_register() - get register value from its offset
 * @regs:	pt_regs from which register value is gotten
 * @offset:	offset of the register.
 *
 * regs_get_register returns the value of a register whose offset from @regs.
 * The @offset is the offset of the register in struct pt_regs.
 * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
 */
static inline u64 regs_get_register(struct pt_regs *regs, unsigned int offset)
{
	u64 val = 0;

	WARN_ON(offset & 7);

	offset >>= 3;
	switch (offset) {
	case 0 ... 30:
		val = regs->regs[offset];
		break;
	case offsetof(struct pt_regs, sp) >> 3:
		val = regs->sp;
		break;
	case offsetof(struct pt_regs, pc) >> 3:
		val = regs->pc;
		break;
	case offsetof(struct pt_regs, pstate) >> 3:
		val = regs->pstate;
		break;
	default:
		val = 0;
	}

	return val;
}

/*
 * Read a register given an architectural register index r.
 * This handles the common case where 31 means XZR, not SP.
 */
static inline unsigned long pt_regs_read_reg(const struct pt_regs *regs, int r)
{
	return (r == 31) ? 0 : regs->regs[r];
}

/*
 * Write a register given an architectural register index r.
 * This handles the common case where 31 means XZR, not SP.
 */
static inline void pt_regs_write_reg(struct pt_regs *regs, int r,
				     unsigned long val)
{
	if (r != 31)
		regs->regs[r] = val;
}

/* Valid only for Kernel mode traps. */
static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
{
	return regs->sp;
}

static inline unsigned long regs_return_value(struct pt_regs *regs)
{
	return regs->regs[0];
}

/* We must avoid circular header include via sched.h */
struct task_struct;
int valid_user_regs(struct user_pt_regs *regs, struct task_struct *task);

#define GET_IP(regs)		((unsigned long)(regs)->pc)
#define SET_IP(regs, value)	((regs)->pc = ((u64) (value)))

#define GET_FP(ptregs)		((unsigned long)(ptregs)->regs[29])
#define SET_FP(ptregs, value)	((ptregs)->regs[29] = ((u64) (value)))

#include <asm-generic/ptrace.h>

#define procedure_link_pointer(regs)	((regs)->regs[30])

static inline void procedure_link_pointer_set(struct pt_regs *regs,
					   unsigned long val)
{
	procedure_link_pointer(regs) = val;
}

#undef profile_pc
extern unsigned long profile_pc(struct pt_regs *regs);

#endif /* __ASSEMBLY__ */
#endif
Commit	Line	Data
60ffc30d CM	1	/*
	2	* Based on arch/arm/include/asm/ptrace.h
	3	*
	4	* Copyright (C) 1996-2003 Russell King
	5	* Copyright (C) 2012 ARM Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19	#ifndef __ASM_PTRACE_H
	20	#define __ASM_PTRACE_H
	21
4262a727	22	#include <uapi/asm/ptrace.h>
60ffc30d	23
974c8e45 MZ	24	/* Current Exception Level values, as contained in CurrentEL */
	25	#define CurrentEL_EL1 (1 << 2)
	26	#define CurrentEL_EL2 (2 << 2)
	27
60ffc30d	28	/* AArch32-specific ptrace requests */
27aa55c5 WD	29	#define COMPAT_PTRACE_GETREGS 12
	30	#define COMPAT_PTRACE_SETREGS 13
	31	#define COMPAT_PTRACE_GET_THREAD_AREA 22
	32	#define COMPAT_PTRACE_SET_SYSCALL 23
60ffc30d CM	33	#define COMPAT_PTRACE_GETVFPREGS 27
60ffc30d CM	34	#define COMPAT_PTRACE_SETVFPREGS 28
27aa55c5 WD	35	#define COMPAT_PTRACE_GETHBPREGS 29
27aa55c5 WD	36	#define COMPAT_PTRACE_SETHBPREGS 30
9ec218b8	37
25086263 MR	38	/* SPSR_ELx bits for exceptions taken from AArch32 */
	39	#define PSR_AA32_MODE_MASK 0x0000001f
	40	#define PSR_AA32_MODE_USR 0x00000010
	41	#define PSR_AA32_MODE_FIQ 0x00000011
	42	#define PSR_AA32_MODE_IRQ 0x00000012
	43	#define PSR_AA32_MODE_SVC 0x00000013
	44	#define PSR_AA32_MODE_ABT 0x00000017
	45	#define PSR_AA32_MODE_HYP 0x0000001a
	46	#define PSR_AA32_MODE_UND 0x0000001b
	47	#define PSR_AA32_MODE_SYS 0x0000001f
	48	#define PSR_AA32_T_BIT 0x00000020
	49	#define PSR_AA32_F_BIT 0x00000040
	50	#define PSR_AA32_I_BIT 0x00000080
	51	#define PSR_AA32_A_BIT 0x00000100
	52	#define PSR_AA32_E_BIT 0x00000200
	53	#define PSR_AA32_DIT_BIT 0x01000000
	54	#define PSR_AA32_Q_BIT 0x08000000
	55	#define PSR_AA32_V_BIT 0x10000000
	56	#define PSR_AA32_C_BIT 0x20000000
	57	#define PSR_AA32_Z_BIT 0x40000000
	58	#define PSR_AA32_N_BIT 0x80000000
	59	#define PSR_AA32_IT_MASK 0x0600fc00 /* If-Then execution state mask */
	60	#define PSR_AA32_GE_MASK 0x000f0000
	61
	62	#ifdef CONFIG_CPU_BIG_ENDIAN
	63	#define PSR_AA32_ENDSTATE PSR_AA32_E_BIT
	64	#else
	65	#define PSR_AA32_ENDSTATE 0
	66	#endif
	67
	68	/* AArch32 CPSR bits, as seen in AArch32 */
25086263	69	#define COMPAT_PSR_DIT_BIT 0x00200000
2d888f48	70
60ffc30d CM	71	/*
	72	* These are 'magic' values for PTRACE_PEEKUSR that return info about where a
	73	* process is located in memory.
	74	*/
7606c37d CM	75	#define COMPAT_PT_TEXT_ADDR 0x10000
	76	#define COMPAT_PT_DATA_ADDR 0x10004
	77	#define COMPAT_PT_TEXT_END_ADDR 0x10008
17c28958 DM	78
	79	/*
	80	* If pt_regs.syscallno == NO_SYSCALL, then the thread is not executing
	81	* a syscall -- i.e., its most recent entry into the kernel from
	82	* userspace was not via SVC, or otherwise a tracer cancelled the syscall.
	83	*
	84	* This must have the value -1, for ABI compatibility with ptrace etc.
	85	*/
	86	#define NO_SYSCALL (-1)
	87
60ffc30d	88	#ifndef __ASSEMBLY__
0a8ea52c	89	#include <linux/bug.h>
17c28958	90	#include <linux/types.h>
60ffc30d	91
60ffc30d CM	92	/* sizeof(struct user) for AArch32 */
60ffc30d CM	93	#define COMPAT_USER_SZ 296
88483ec6 MZ	94
	95	/* Architecturally defined mapping between AArch32 and AArch64 registers */
	96	#define compat_usr(x) regs[(x)]
2ee0d7fd	97	#define compat_fp regs[11]
60ffc30d	98	#define compat_sp regs[13]
60ffc30d	99	#define compat_lr regs[14]
88483ec6	100	#define compat_sp_hyp regs[15]
5accd17d RM	101	#define compat_lr_irq regs[16]
	102	#define compat_sp_irq regs[17]
	103	#define compat_lr_svc regs[18]
	104	#define compat_sp_svc regs[19]
	105	#define compat_lr_abt regs[20]
	106	#define compat_sp_abt regs[21]
	107	#define compat_lr_und regs[22]
	108	#define compat_sp_und regs[23]
88483ec6 MZ	109	#define compat_r8_fiq regs[24]
	110	#define compat_r9_fiq regs[25]
	111	#define compat_r10_fiq regs[26]
	112	#define compat_r11_fiq regs[27]
	113	#define compat_r12_fiq regs[28]
	114	#define compat_sp_fiq regs[29]
	115	#define compat_lr_fiq regs[30]
60ffc30d	116
25086263 MR	117	static inline unsigned long compat_psr_to_pstate(const unsigned long psr)
	118	{
	119	unsigned long pstate;
	120
	121	pstate = psr & ~COMPAT_PSR_DIT_BIT;
	122
	123	if (psr & COMPAT_PSR_DIT_BIT)
	124	pstate \|= PSR_AA32_DIT_BIT;
	125
	126	return pstate;
	127	}
	128
	129	static inline unsigned long pstate_to_compat_psr(const unsigned long pstate)
	130	{
	131	unsigned long psr;
	132
	133	psr = pstate & ~PSR_AA32_DIT_BIT;
	134
	135	if (pstate & PSR_AA32_DIT_BIT)
	136	psr \|= COMPAT_PSR_DIT_BIT;
	137
	138	return psr;
	139	}
	140
60ffc30d CM	141	/*
	142	* This struct defines the way the registers are stored on the stack during an
	143	* exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for
	144	* stack alignment). struct user_pt_regs must form a prefix of struct pt_regs.
	145	*/
	146	struct pt_regs {
	147	union {
	148	struct user_pt_regs user_regs;
	149	struct {
	150	u64 regs[31];
	151	u64 sp;
	152	u64 pc;
	153	u64 pstate;
	154	};
	155	};
	156	u64 orig_x0;
35d0e6fb DM	157	#ifdef __AARCH64EB__
	158	u32 unused2;
	159	s32 syscallno;
	160	#else
	161	s32 syscallno;
	162	u32 unused2;
	163	#endif
	164
e19a6ee2 JM	165	u64 orig_addr_limit;
e19a6ee2 JM	166	u64 unused; // maintain 16 byte alignment
73267498	167	u64 stackframe[2];
60ffc30d CM	168	};
60ffc30d CM	169
17c28958 DM	170	static inline bool in_syscall(struct pt_regs const *regs)
	171	{
	172	return regs->syscallno != NO_SYSCALL;
	173	}
	174
	175	static inline void forget_syscall(struct pt_regs *regs)
	176	{
	177	regs->syscallno = NO_SYSCALL;
	178	}
	179
0a8ea52c DL	180	#define MAX_REG_OFFSET offsetof(struct pt_regs, pstate)
0a8ea52c DL	181
60ffc30d CM	182	#define arch_has_single_step() (1)
	183
	184	#ifdef CONFIG_COMPAT
	185	#define compat_thumb_mode(regs) \
d64567f6	186	(((regs)->pstate & PSR_AA32_T_BIT))
60ffc30d CM	187	#else
	188	#define compat_thumb_mode(regs) (0)
	189	#endif
	190
	191	#define user_mode(regs) \
	192	(((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t)
	193
	194	#define compat_user_mode(regs) \
	195	(((regs)->pstate & (PSR_MODE32_BIT \| PSR_MODE_MASK)) == \
	196	(PSR_MODE32_BIT \| PSR_MODE_EL0t))
	197
	198	#define processor_mode(regs) \
	199	((regs)->pstate & PSR_MODE_MASK)
	200
	201	#define interrupts_enabled(regs) \
	202	(!((regs)->pstate & PSR_I_BIT))
	203
	204	#define fast_interrupts_enabled(regs) \
	205	(!((regs)->pstate & PSR_F_BIT))
	206
2dd0e8d2	207	#define GET_USP(regs) \
2520d039	208	(!compat_user_mode(regs) ? (regs)->sp : (regs)->compat_sp)
60ffc30d	209
2dd0e8d2 SP	210	#define SET_USP(ptregs, value) \
	211	(!compat_user_mode(regs) ? ((regs)->sp = value) : ((regs)->compat_sp = value))
	212
0a8ea52c	213	extern int regs_query_register_offset(const char *name);
0a8ea52c DL	214	extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
	215	unsigned int n);
	216
	217	/**
	218	* regs_get_register() - get register value from its offset
	219	* @regs: pt_regs from which register value is gotten
	220	* @offset: offset of the register.
	221	*
	222	* regs_get_register returns the value of a register whose offset from @regs.
	223	* The @offset is the offset of the register in struct pt_regs.
	224	* If @offset is bigger than MAX_REG_OFFSET, this returns 0.
	225	*/
	226	static inline u64 regs_get_register(struct pt_regs *regs, unsigned int offset)
	227	{
	228	u64 val = 0;
	229
	230	WARN_ON(offset & 7);
	231
	232	offset >>= 3;
	233	switch (offset) {
	234	case 0 ... 30:
	235	val = regs->regs[offset];
	236	break;
	237	case offsetof(struct pt_regs, sp) >> 3:
	238	val = regs->sp;
	239	break;
	240	case offsetof(struct pt_regs, pc) >> 3:
	241	val = regs->pc;
	242	break;
	243	case offsetof(struct pt_regs, pstate) >> 3:
	244	val = regs->pstate;
	245	break;
	246	default:
	247	val = 0;
	248	}
	249
	250	return val;
	251	}
	252
6c23e2ff MR	253	/*
	254	* Read a register given an architectural register index r.
	255	* This handles the common case where 31 means XZR, not SP.
	256	*/
	257	static inline unsigned long pt_regs_read_reg(const struct pt_regs *regs, int r)
	258	{
	259	return (r == 31) ? 0 : regs->regs[r];
	260	}
	261
	262	/*
	263	* Write a register given an architectural register index r.
	264	* This handles the common case where 31 means XZR, not SP.
	265	*/
	266	static inline void pt_regs_write_reg(struct pt_regs *regs, int r,
	267	unsigned long val)
	268	{
	269	if (r != 31)
	270	regs->regs[r] = val;
	271	}
	272
0a8ea52c DL	273	/* Valid only for Kernel mode traps. */
	274	static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
	275	{
	276	return regs->sp;
	277	}
	278
d34a3ebd AT	279	static inline unsigned long regs_return_value(struct pt_regs *regs)
	280	{
	281	return regs->regs[0];
	282	}
	283
dbd4d7ca MR	284	/* We must avoid circular header include via sched.h */
	285	struct task_struct;
	286	int valid_user_regs(struct user_pt_regs regs, struct task_struct task);
60ffc30d	287
2dd0e8d2 SP	288	#define GET_IP(regs) ((unsigned long)(regs)->pc)
	289	#define SET_IP(regs, value) ((regs)->pc = ((u64) (value)))
	290
	291	#define GET_FP(ptregs) ((unsigned long)(ptregs)->regs[29])
	292	#define SET_FP(ptregs, value) ((ptregs)->regs[29] = ((u64) (value)))
	293
	294	#include <asm-generic/ptrace.h>
60ffc30d	295
9842ceae PA	296	#define procedure_link_pointer(regs) ((regs)->regs[30])
	297
	298	static inline void procedure_link_pointer_set(struct pt_regs *regs,
	299	unsigned long val)
	300	{
	301	procedure_link_pointer(regs) = val;
	302	}
	303
2dd0e8d2	304	#undef profile_pc
60ffc30d	305	extern unsigned long profile_pc(struct pt_regs *regs);
60ffc30d	306
60ffc30d	307	#endif /* __ASSEMBLY__ */
60ffc30d	308	#endif