[linux-2.6-block.git] / arch / arm64 / include / asm / processor.h

/*
 * Based on arch/arm/include/asm/processor.h
 *
 * Copyright (C) 1995-1999 Russell King
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __ASM_PROCESSOR_H
#define __ASM_PROCESSOR_H

/*
 * Default implementation of macro that returns current
 * instruction pointer ("program counter").
 */
#define current_text_addr() ({ __label__ _l; _l: &&_l;})

#ifdef __KERNEL__

#include <linux/string.h>

#include <asm/alternative.h>
#include <asm/fpsimd.h>
#include <asm/hw_breakpoint.h>
#include <asm/lse.h>
#include <asm/pgtable-hwdef.h>
#include <asm/ptrace.h>
#include <asm/types.h>

#ifdef __KERNEL__
#define STACK_TOP_MAX		TASK_SIZE_64
#ifdef CONFIG_COMPAT
#define AARCH32_VECTORS_BASE	0xffff0000
#define STACK_TOP		(test_thread_flag(TIF_32BIT) ? \
				AARCH32_VECTORS_BASE : STACK_TOP_MAX)
#else
#define STACK_TOP		STACK_TOP_MAX
#endif /* CONFIG_COMPAT */

extern phys_addr_t arm64_dma_phys_limit;
#define ARCH_LOW_ADDRESS_LIMIT	(arm64_dma_phys_limit - 1)
#endif /* __KERNEL__ */

struct debug_info {
	/* Have we suspended stepping by a debugger? */
	int			suspended_step;
	/* Allow breakpoints and watchpoints to be disabled for this thread. */
	int			bps_disabled;
	int			wps_disabled;
	/* Hardware breakpoints pinned to this task. */
	struct perf_event	*hbp_break[ARM_MAX_BRP];
	struct perf_event	*hbp_watch[ARM_MAX_WRP];
};

struct cpu_context {
	unsigned long x19;
	unsigned long x20;
	unsigned long x21;
	unsigned long x22;
	unsigned long x23;
	unsigned long x24;
	unsigned long x25;
	unsigned long x26;
	unsigned long x27;
	unsigned long x28;
	unsigned long fp;
	unsigned long sp;
	unsigned long pc;
};

struct thread_struct {
	struct cpu_context	cpu_context;	/* cpu context */
	unsigned long		tp_value;	/* TLS register */
#ifdef CONFIG_COMPAT
	unsigned long		tp2_value;
#endif
	struct fpsimd_state	fpsimd_state;
	unsigned long		fault_address;	/* fault info */
	unsigned long		fault_code;	/* ESR_EL1 value */
	struct debug_info	debug;		/* debugging */
};

#ifdef CONFIG_COMPAT
#define task_user_tls(t)						\
({									\
	unsigned long *__tls;						\
	if (is_compat_thread(task_thread_info(t)))			\
		__tls = &(t)->thread.tp2_value;				\
	else								\
		__tls = &(t)->thread.tp_value;				\
	__tls;								\
 })
#else
#define task_user_tls(t)	(&(t)->thread.tp_value)
#endif

#define INIT_THREAD  {	}

static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
{
	memset(regs, 0, sizeof(*regs));
	regs->syscallno = ~0UL;
	regs->pc = pc;
}

static inline void start_thread(struct pt_regs *regs, unsigned long pc,
				unsigned long sp)
{
	start_thread_common(regs, pc);
	regs->pstate = PSR_MODE_EL0t;
	regs->sp = sp;
}

#ifdef CONFIG_COMPAT
static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
				       unsigned long sp)
{
	start_thread_common(regs, pc);
	regs->pstate = COMPAT_PSR_MODE_USR;
	if (pc & 1)
		regs->pstate |= COMPAT_PSR_T_BIT;

#ifdef __AARCH64EB__
	regs->pstate |= COMPAT_PSR_E_BIT;
#endif

	regs->compat_sp = sp;
}
#endif

/* Forward declaration, a strange C thing */
struct task_struct;

/* Free all resources held by a thread. */
extern void release_thread(struct task_struct *);

unsigned long get_wchan(struct task_struct *p);

static inline void cpu_relax(void)
{
	asm volatile("yield" ::: "memory");
}

#define cpu_relax_lowlatency()                cpu_relax()

/* Thread switching */
extern struct task_struct *cpu_switch_to(struct task_struct *prev,
					 struct task_struct *next);

#define task_pt_regs(p) \
	((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1)

#define KSTK_EIP(tsk)	((unsigned long)task_pt_regs(tsk)->pc)
#define KSTK_ESP(tsk)	user_stack_pointer(task_pt_regs(tsk))

/*
 * Prefetching support
 */
#define ARCH_HAS_PREFETCH
static inline void prefetch(const void *ptr)
{
	asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
}

#define ARCH_HAS_PREFETCHW
static inline void prefetchw(const void *ptr)
{
	asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
}

#define ARCH_HAS_SPINLOCK_PREFETCH
static inline void spin_lock_prefetch(const void *ptr)
{
	asm volatile(ARM64_LSE_ATOMIC_INSN(
		     "prfm pstl1strm, %a0",
		     "nop") : : "p" (ptr));
}

#define HAVE_ARCH_PICK_MMAP_LAYOUT

#endif

void cpu_enable_pan(void *__unused);
void cpu_enable_uao(void *__unused);
void cpu_enable_cache_maint_trap(void *__unused);

#endif /* __ASM_PROCESSOR_H */
Commit	Line	Data
9cce7a43 CM	1	/*
	2	* Based on arch/arm/include/asm/processor.h
	3	*
	4	* Copyright (C) 1995-1999 Russell King
	5	* Copyright (C) 2012 ARM Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19	#ifndef __ASM_PROCESSOR_H
	20	#define __ASM_PROCESSOR_H
	21
	22	/*
	23	* Default implementation of macro that returns current
	24	* instruction pointer ("program counter").
	25	*/
	26	#define current_text_addr() ({ __label__ _l; _l: &&_l;})
	27
	28	#ifdef __KERNEL__
	29
	30	#include <linux/string.h>
	31
cd5e10bd	32	#include <asm/alternative.h>
9cce7a43 CM	33	#include <asm/fpsimd.h>
9cce7a43 CM	34	#include <asm/hw_breakpoint.h>
afb83cc3	35	#include <asm/lse.h>
2ec4560b	36	#include <asm/pgtable-hwdef.h>
9cce7a43 CM	37	#include <asm/ptrace.h>
	38	#include <asm/types.h>
	39
	40	#ifdef __KERNEL__
	41	#define STACK_TOP_MAX TASK_SIZE_64
	42	#ifdef CONFIG_COMPAT
	43	#define AARCH32_VECTORS_BASE 0xffff0000
	44	#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
	45	AARCH32_VECTORS_BASE : STACK_TOP_MAX)
	46	#else
	47	#define STACK_TOP STACK_TOP_MAX
	48	#endif /* CONFIG_COMPAT */
f483a853	49
a1e50a82 CM	50	extern phys_addr_t arm64_dma_phys_limit;
a1e50a82 CM	51	#define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
9cce7a43 CM	52	#endif /* __KERNEL__ */
	53
	54	struct debug_info {
	55	/* Have we suspended stepping by a debugger? */
	56	int suspended_step;
	57	/* Allow breakpoints and watchpoints to be disabled for this thread. */
	58	int bps_disabled;
	59	int wps_disabled;
	60	/* Hardware breakpoints pinned to this task. */
	61	struct perf_event *hbp_break[ARM_MAX_BRP];
	62	struct perf_event *hbp_watch[ARM_MAX_WRP];
	63	};
	64
	65	struct cpu_context {
	66	unsigned long x19;
	67	unsigned long x20;
	68	unsigned long x21;
	69	unsigned long x22;
	70	unsigned long x23;
	71	unsigned long x24;
	72	unsigned long x25;
	73	unsigned long x26;
	74	unsigned long x27;
	75	unsigned long x28;
	76	unsigned long fp;
	77	unsigned long sp;
	78	unsigned long pc;
	79	};
	80
	81	struct thread_struct {
	82	struct cpu_context cpu_context; /* cpu context */
d00a3810 WD	83	unsigned long tp_value; /* TLS register */
	84	#ifdef CONFIG_COMPAT
	85	unsigned long tp2_value;
	86	#endif
9cce7a43 CM	87	struct fpsimd_state fpsimd_state;
9cce7a43 CM	88	unsigned long fault_address; /* fault info */
9141300a	89	unsigned long fault_code; /* ESR_EL1 value */
9cce7a43 CM	90	struct debug_info debug; /* debugging */
	91	};
	92
d00a3810 WD	93	#ifdef CONFIG_COMPAT
	94	#define task_user_tls(t) \
	95	({ \
	96	unsigned long *__tls; \
	97	if (is_compat_thread(task_thread_info(t))) \
	98	__tls = &(t)->thread.tp2_value; \
	99	else \
	100	__tls = &(t)->thread.tp_value; \
	101	__tls; \
	102	})
	103	#else
	104	#define task_user_tls(t) (&(t)->thread.tp_value)
	105	#endif
	106
9cce7a43 CM	107	#define INIT_THREAD { }
	108
	109	static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
	110	{
	111	memset(regs, 0, sizeof(*regs));
	112	regs->syscallno = ~0UL;
	113	regs->pc = pc;
	114	}
	115
	116	static inline void start_thread(struct pt_regs *regs, unsigned long pc,
	117	unsigned long sp)
	118	{
9cce7a43 CM	119	start_thread_common(regs, pc);
	120	regs->pstate = PSR_MODE_EL0t;
	121	regs->sp = sp;
9cce7a43 CM	122	}
	123
	124	#ifdef CONFIG_COMPAT
	125	static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
	126	unsigned long sp)
	127	{
9cce7a43 CM	128	start_thread_common(regs, pc);
	129	regs->pstate = COMPAT_PSR_MODE_USR;
	130	if (pc & 1)
	131	regs->pstate \|= COMPAT_PSR_T_BIT;
a795a38e WD	132
	133	#ifdef __AARCH64EB__
	134	regs->pstate \|= COMPAT_PSR_E_BIT;
	135	#endif
	136
9cce7a43	137	regs->compat_sp = sp;
9cce7a43 CM	138	}
	139	#endif
	140
	141	/* Forward declaration, a strange C thing */
	142	struct task_struct;
	143
	144	/* Free all resources held by a thread. */
	145	extern void release_thread(struct task_struct *);
	146
9cce7a43 CM	147	unsigned long get_wchan(struct task_struct *p);
9cce7a43 CM	148
1baa82f4 PC	149	static inline void cpu_relax(void)
	150	{
	151	asm volatile("yield" ::: "memory");
	152	}
	153
3a6bfbc9	154	#define cpu_relax_lowlatency() cpu_relax()
9cce7a43 CM	155
	156	/* Thread switching */
	157	extern struct task_struct cpu_switch_to(struct task_struct prev,
	158	struct task_struct *next);
	159
9cce7a43 CM	160	#define task_pt_regs(p) \
	161	((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1)
	162
ebe6152e	163	#define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc)
3168a743	164	#define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk))
9cce7a43 CM	165
	166	/*
	167	* Prefetching support
	168	*/
	169	#define ARCH_HAS_PREFETCH
	170	static inline void prefetch(const void *ptr)
	171	{
	172	asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
	173	}
	174
	175	#define ARCH_HAS_PREFETCHW
	176	static inline void prefetchw(const void *ptr)
	177	{
	178	asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
	179	}
	180
	181	#define ARCH_HAS_SPINLOCK_PREFETCH
cd5e10bd	182	static inline void spin_lock_prefetch(const void *ptr)
9cce7a43	183	{
cd5e10bd WD	184	asm volatile(ARM64_LSE_ATOMIC_INSN(
	185	"prfm pstl1strm, %a0",
	186	"nop") : : "p" (ptr));
9cce7a43 CM	187	}
	188
	189	#define HAVE_ARCH_PICK_MMAP_LAYOUT
	190
	191	#endif
	192
dbb4e152	193	void cpu_enable_pan(void *__unused);
57f4959b	194	void cpu_enable_uao(void *__unused);
7dd01aef	195	void cpu_enable_cache_maint_trap(void *__unused);
338d4f49	196
9cce7a43	197	#endif /* __ASM_PROCESSOR_H */