[linux-block.git] / arch / arm64 / include / asm / processor.h

/*
 * Based on arch/arm/include/asm/processor.h
 *
 * Copyright (C) 1995-1999 Russell King
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __ASM_PROCESSOR_H
#define __ASM_PROCESSOR_H

#define TASK_SIZE_64		(UL(1) << VA_BITS)

#ifndef __ASSEMBLY__

/*
 * Default implementation of macro that returns current
 * instruction pointer ("program counter").
 */
#define current_text_addr() ({ __label__ _l; _l: &&_l;})

#ifdef __KERNEL__

#include <linux/string.h>

#include <asm/alternative.h>
#include <asm/fpsimd.h>
#include <asm/hw_breakpoint.h>
#include <asm/lse.h>
#include <asm/pgtable-hwdef.h>
#include <asm/ptrace.h>
#include <asm/types.h>

/*
 * TASK_SIZE - the maximum size of a user space task.
 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
 */
#ifdef CONFIG_COMPAT
#define TASK_SIZE_32		UL(0x100000000)
#define TASK_SIZE		(test_thread_flag(TIF_32BIT) ? \
				TASK_SIZE_32 : TASK_SIZE_64)
#define TASK_SIZE_OF(tsk)	(test_tsk_thread_flag(tsk, TIF_32BIT) ? \
				TASK_SIZE_32 : TASK_SIZE_64)
#else
#define TASK_SIZE		TASK_SIZE_64
#endif /* CONFIG_COMPAT */

#define TASK_UNMAPPED_BASE	(PAGE_ALIGN(TASK_SIZE / 4))

#define STACK_TOP_MAX		TASK_SIZE_64
#ifdef CONFIG_COMPAT
#define AARCH32_VECTORS_BASE	0xffff0000
#define STACK_TOP		(test_thread_flag(TIF_32BIT) ? \
				AARCH32_VECTORS_BASE : STACK_TOP_MAX)
#else
#define STACK_TOP		STACK_TOP_MAX
#endif /* CONFIG_COMPAT */

extern phys_addr_t arm64_dma_phys_limit;
#define ARCH_LOW_ADDRESS_LIMIT	(arm64_dma_phys_limit - 1)

struct debug_info {
#ifdef CONFIG_HAVE_HW_BREAKPOINT
	/* Have we suspended stepping by a debugger? */
	int			suspended_step;
	/* Allow breakpoints and watchpoints to be disabled for this thread. */
	int			bps_disabled;
	int			wps_disabled;
	/* Hardware breakpoints pinned to this task. */
	struct perf_event	*hbp_break[ARM_MAX_BRP];
	struct perf_event	*hbp_watch[ARM_MAX_WRP];
#endif
};

struct cpu_context {
	unsigned long x19;
	unsigned long x20;
	unsigned long x21;
	unsigned long x22;
	unsigned long x23;
	unsigned long x24;
	unsigned long x25;
	unsigned long x26;
	unsigned long x27;
	unsigned long x28;
	unsigned long fp;
	unsigned long sp;
	unsigned long pc;
};

struct thread_struct {
	struct cpu_context	cpu_context;	/* cpu context */
	unsigned long		tp_value;	/* TLS register */
#ifdef CONFIG_COMPAT
	unsigned long		tp2_value;
#endif
	struct fpsimd_state	fpsimd_state;
	void			*sve_state;	/* SVE registers, if any */
	unsigned int		sve_vl;		/* SVE vector length */
	unsigned int		sve_vl_onexec;	/* SVE vl after next exec */
	unsigned long		fault_address;	/* fault info */
	unsigned long		fault_code;	/* ESR_EL1 value */
	struct debug_info	debug;		/* debugging */
};

#ifdef CONFIG_COMPAT
#define task_user_tls(t)						\
({									\
	unsigned long *__tls;						\
	if (is_compat_thread(task_thread_info(t)))			\
		__tls = &(t)->thread.tp2_value;				\
	else								\
		__tls = &(t)->thread.tp_value;				\
	__tls;								\
 })
#else
#define task_user_tls(t)	(&(t)->thread.tp_value)
#endif

/* Sync TPIDR_EL0 back to thread_struct for current */
void tls_preserve_current_state(void);

#define INIT_THREAD  {	}

static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
{
	memset(regs, 0, sizeof(*regs));
	forget_syscall(regs);
	regs->pc = pc;
}

static inline void start_thread(struct pt_regs *regs, unsigned long pc,
				unsigned long sp)
{
	start_thread_common(regs, pc);
	regs->pstate = PSR_MODE_EL0t;
	regs->sp = sp;
}

#ifdef CONFIG_COMPAT
static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
				       unsigned long sp)
{
	start_thread_common(regs, pc);
	regs->pstate = COMPAT_PSR_MODE_USR;
	if (pc & 1)
		regs->pstate |= COMPAT_PSR_T_BIT;

#ifdef __AARCH64EB__
	regs->pstate |= COMPAT_PSR_E_BIT;
#endif

	regs->compat_sp = sp;
}
#endif

/* Forward declaration, a strange C thing */
struct task_struct;

/* Free all resources held by a thread. */
extern void release_thread(struct task_struct *);

unsigned long get_wchan(struct task_struct *p);

static inline void cpu_relax(void)
{
	asm volatile("yield" ::: "memory");
}

/* Thread switching */
extern struct task_struct *cpu_switch_to(struct task_struct *prev,
					 struct task_struct *next);

#define task_pt_regs(p) \
	((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)

#define KSTK_EIP(tsk)	((unsigned long)task_pt_regs(tsk)->pc)
#define KSTK_ESP(tsk)	user_stack_pointer(task_pt_regs(tsk))

/*
 * Prefetching support
 */
#define ARCH_HAS_PREFETCH
static inline void prefetch(const void *ptr)
{
	asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
}

#define ARCH_HAS_PREFETCHW
static inline void prefetchw(const void *ptr)
{
	asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
}

#define ARCH_HAS_SPINLOCK_PREFETCH
static inline void spin_lock_prefetch(const void *ptr)
{
	asm volatile(ARM64_LSE_ATOMIC_INSN(
		     "prfm pstl1strm, %a0",
		     "nop") : : "p" (ptr));
}

#define HAVE_ARCH_PICK_MMAP_LAYOUT

#endif

int cpu_enable_pan(void *__unused);
int cpu_enable_cache_maint_trap(void *__unused);

/* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */
#define SVE_SET_VL(arg)	sve_set_current_vl(arg)
#define SVE_GET_VL()	sve_get_current_vl()

#endif /* __ASSEMBLY__ */
#endif /* __ASM_PROCESSOR_H */
Commit	Line	Data
9cce7a43 CM	1	/*
	2	* Based on arch/arm/include/asm/processor.h
	3	*
	4	* Copyright (C) 1995-1999 Russell King
	5	* Copyright (C) 2012 ARM Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19	#ifndef __ASM_PROCESSOR_H
	20	#define __ASM_PROCESSOR_H
	21
eef94a3d YN	22	#define TASK_SIZE_64 (UL(1) << VA_BITS)
	23
	24	#ifndef __ASSEMBLY__
	25
9cce7a43 CM	26	/*
	27	* Default implementation of macro that returns current
	28	* instruction pointer ("program counter").
	29	*/
	30	#define current_text_addr() ({ __label__ _l; _l: &&_l;})
	31
	32	#ifdef __KERNEL__
	33
	34	#include <linux/string.h>
	35
cd5e10bd	36	#include <asm/alternative.h>
9cce7a43 CM	37	#include <asm/fpsimd.h>
9cce7a43 CM	38	#include <asm/hw_breakpoint.h>
afb83cc3	39	#include <asm/lse.h>
2ec4560b	40	#include <asm/pgtable-hwdef.h>
9cce7a43 CM	41	#include <asm/ptrace.h>
	42	#include <asm/types.h>
	43
eef94a3d YN	44	/*
	45	* TASK_SIZE - the maximum size of a user space task.
	46	* TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
	47	*/
	48	#ifdef CONFIG_COMPAT
	49	#define TASK_SIZE_32 UL(0x100000000)
	50	#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
	51	TASK_SIZE_32 : TASK_SIZE_64)
	52	#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
	53	TASK_SIZE_32 : TASK_SIZE_64)
	54	#else
	55	#define TASK_SIZE TASK_SIZE_64
	56	#endif /* CONFIG_COMPAT */
	57
	58	#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4))
	59
9cce7a43 CM	60	#define STACK_TOP_MAX TASK_SIZE_64
	61	#ifdef CONFIG_COMPAT
	62	#define AARCH32_VECTORS_BASE 0xffff0000
	63	#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
	64	AARCH32_VECTORS_BASE : STACK_TOP_MAX)
	65	#else
	66	#define STACK_TOP STACK_TOP_MAX
	67	#endif /* CONFIG_COMPAT */
f483a853	68
a1e50a82 CM	69	extern phys_addr_t arm64_dma_phys_limit;
a1e50a82 CM	70	#define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
9cce7a43 CM	71
9cce7a43 CM	72	struct debug_info {
fda89d9e	73	#ifdef CONFIG_HAVE_HW_BREAKPOINT
9cce7a43 CM	74	/* Have we suspended stepping by a debugger? */
	75	int suspended_step;
	76	/* Allow breakpoints and watchpoints to be disabled for this thread. */
	77	int bps_disabled;
	78	int wps_disabled;
	79	/* Hardware breakpoints pinned to this task. */
	80	struct perf_event *hbp_break[ARM_MAX_BRP];
	81	struct perf_event *hbp_watch[ARM_MAX_WRP];
fda89d9e	82	#endif
9cce7a43 CM	83	};
	84
	85	struct cpu_context {
	86	unsigned long x19;
	87	unsigned long x20;
	88	unsigned long x21;
	89	unsigned long x22;
	90	unsigned long x23;
	91	unsigned long x24;
	92	unsigned long x25;
	93	unsigned long x26;
	94	unsigned long x27;
	95	unsigned long x28;
	96	unsigned long fp;
	97	unsigned long sp;
	98	unsigned long pc;
	99	};
	100
	101	struct thread_struct {
	102	struct cpu_context cpu_context; /* cpu context */
d00a3810 WD	103	unsigned long tp_value; /* TLS register */
	104	#ifdef CONFIG_COMPAT
	105	unsigned long tp2_value;
	106	#endif
9cce7a43	107	struct fpsimd_state fpsimd_state;
bc0ee476 DM	108	void sve_state; / SVE registers, if any */
bc0ee476 DM	109	unsigned int sve_vl; /* SVE vector length */
79ab047c	110	unsigned int sve_vl_onexec; /* SVE vl after next exec */
9cce7a43	111	unsigned long fault_address; /* fault info */
9141300a	112	unsigned long fault_code; /* ESR_EL1 value */
9cce7a43 CM	113	struct debug_info debug; /* debugging */
	114	};
	115
d00a3810 WD	116	#ifdef CONFIG_COMPAT
	117	#define task_user_tls(t) \
	118	({ \
	119	unsigned long *__tls; \
	120	if (is_compat_thread(task_thread_info(t))) \
	121	__tls = &(t)->thread.tp2_value; \
	122	else \
	123	__tls = &(t)->thread.tp_value; \
	124	__tls; \
	125	})
	126	#else
	127	#define task_user_tls(t) (&(t)->thread.tp_value)
	128	#endif
	129
936eb65c DM	130	/* Sync TPIDR_EL0 back to thread_struct for current */
	131	void tls_preserve_current_state(void);
	132
9cce7a43 CM	133	#define INIT_THREAD { }
	134
	135	static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
	136	{
	137	memset(regs, 0, sizeof(*regs));
17c28958	138	forget_syscall(regs);
9cce7a43 CM	139	regs->pc = pc;
	140	}
	141
	142	static inline void start_thread(struct pt_regs *regs, unsigned long pc,
	143	unsigned long sp)
	144	{
9cce7a43 CM	145	start_thread_common(regs, pc);
	146	regs->pstate = PSR_MODE_EL0t;
	147	regs->sp = sp;
9cce7a43 CM	148	}
	149
	150	#ifdef CONFIG_COMPAT
	151	static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
	152	unsigned long sp)
	153	{
9cce7a43 CM	154	start_thread_common(regs, pc);
	155	regs->pstate = COMPAT_PSR_MODE_USR;
	156	if (pc & 1)
	157	regs->pstate \|= COMPAT_PSR_T_BIT;
a795a38e WD	158
	159	#ifdef __AARCH64EB__
	160	regs->pstate \|= COMPAT_PSR_E_BIT;
	161	#endif
	162
9cce7a43	163	regs->compat_sp = sp;
9cce7a43 CM	164	}
	165	#endif
	166
	167	/* Forward declaration, a strange C thing */
	168	struct task_struct;
	169
	170	/* Free all resources held by a thread. */
	171	extern void release_thread(struct task_struct *);
	172
9cce7a43 CM	173	unsigned long get_wchan(struct task_struct *p);
9cce7a43 CM	174
1baa82f4 PC	175	static inline void cpu_relax(void)
	176	{
	177	asm volatile("yield" ::: "memory");
	178	}
	179
9cce7a43 CM	180	/* Thread switching */
	181	extern struct task_struct cpu_switch_to(struct task_struct prev,
	182	struct task_struct *next);
	183
9cce7a43	184	#define task_pt_regs(p) \
34be98f4	185	((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
9cce7a43	186
ebe6152e	187	#define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc)
3168a743	188	#define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk))
9cce7a43 CM	189
	190	/*
	191	* Prefetching support
	192	*/
	193	#define ARCH_HAS_PREFETCH
	194	static inline void prefetch(const void *ptr)
	195	{
	196	asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
	197	}
	198
	199	#define ARCH_HAS_PREFETCHW
	200	static inline void prefetchw(const void *ptr)
	201	{
	202	asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
	203	}
	204
	205	#define ARCH_HAS_SPINLOCK_PREFETCH
cd5e10bd	206	static inline void spin_lock_prefetch(const void *ptr)
9cce7a43	207	{
cd5e10bd WD	208	asm volatile(ARM64_LSE_ATOMIC_INSN(
	209	"prfm pstl1strm, %a0",
	210	"nop") : : "p" (ptr));
9cce7a43 CM	211	}
	212
	213	#define HAVE_ARCH_PICK_MMAP_LAYOUT
	214
	215	#endif
	216
2a6dcb2b	217	int cpu_enable_pan(void *__unused);
2a6dcb2b	218	int cpu_enable_cache_maint_trap(void *__unused);
338d4f49	219
2d2123bc DM	220	/* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */
	221	#define SVE_SET_VL(arg) sve_set_current_vl(arg)
	222	#define SVE_GET_VL() sve_get_current_vl()
	223
eef94a3d	224	#endif /* __ASSEMBLY__ */
9cce7a43	225	#endif /* __ASM_PROCESSOR_H */