[linux-2.6-block.git] / arch / arm64 / include / asm / pgtable-prot.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2016 ARM Ltd.
 */
#ifndef __ASM_PGTABLE_PROT_H
#define __ASM_PGTABLE_PROT_H

#include <asm/memory.h>
#include <asm/pgtable-hwdef.h>

#include <linux/const.h>

/*
 * Software defined PTE bits definition.
 */
#define PTE_WRITE		(PTE_DBM)		 /* same as DBM (51) */
#define PTE_SWP_EXCLUSIVE	(_AT(pteval_t, 1) << 2)	 /* only for swp ptes */
#define PTE_DIRTY		(_AT(pteval_t, 1) << 55)
#define PTE_SPECIAL		(_AT(pteval_t, 1) << 56)
#define PTE_DEVMAP		(_AT(pteval_t, 1) << 57)

/*
 * PTE_PRESENT_INVALID=1 & PTE_VALID=0 indicates that the pte's fields should be
 * interpreted according to the HW layout by SW but any attempted HW access to
 * the address will result in a fault. pte_present() returns true.
 */
#define PTE_PRESENT_INVALID	(PTE_NG)		 /* only when !PTE_VALID */

#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
#define PTE_UFFD_WP		(_AT(pteval_t, 1) << 58) /* uffd-wp tracking */
#define PTE_SWP_UFFD_WP		(_AT(pteval_t, 1) << 3)	 /* only for swp ptes */
#else
#define PTE_UFFD_WP		(_AT(pteval_t, 0))
#define PTE_SWP_UFFD_WP		(_AT(pteval_t, 0))
#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */

#define _PROT_DEFAULT		(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)

#define PROT_DEFAULT		(PTE_TYPE_PAGE | PTE_MAYBE_NG | PTE_MAYBE_SHARED | PTE_AF)
#define PROT_SECT_DEFAULT	(PMD_TYPE_SECT | PMD_MAYBE_NG | PMD_MAYBE_SHARED | PMD_SECT_AF)

#define PROT_DEVICE_nGnRnE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
#define PROT_DEVICE_nGnRE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
#define PROT_NORMAL_NC		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
#define PROT_NORMAL		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
#define PROT_NORMAL_TAGGED	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_TAGGED))

#define PROT_SECT_DEVICE_nGnRE	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
#define PROT_SECT_NORMAL	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PTE_WRITE | PMD_ATTRINDX(MT_NORMAL))
#define PROT_SECT_NORMAL_EXEC	(PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))

#define _PAGE_DEFAULT		(_PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))

#define _PAGE_KERNEL		(PROT_NORMAL)
#define _PAGE_KERNEL_RO		((PROT_NORMAL & ~PTE_WRITE) | PTE_RDONLY)
#define _PAGE_KERNEL_ROX	((PROT_NORMAL & ~(PTE_WRITE | PTE_PXN)) | PTE_RDONLY)
#define _PAGE_KERNEL_EXEC	(PROT_NORMAL & ~PTE_PXN)
#define _PAGE_KERNEL_EXEC_CONT	((PROT_NORMAL & ~PTE_PXN) | PTE_CONT)

#define _PAGE_SHARED		(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
#define _PAGE_SHARED_EXEC	(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_WRITE)
#define _PAGE_READONLY		(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
#define _PAGE_READONLY_EXEC	(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN)
#define _PAGE_EXECONLY		(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)

#ifndef __ASSEMBLY__

#include <asm/cpufeature.h>
#include <asm/pgtable-types.h>
#include <asm/rsi.h>

extern bool arm64_use_ng_mappings;
extern unsigned long prot_ns_shared;

#define PROT_NS_SHARED		(is_realm_world() ? prot_ns_shared : 0)

#define PTE_MAYBE_NG		(arm64_use_ng_mappings ? PTE_NG : 0)
#define PMD_MAYBE_NG		(arm64_use_ng_mappings ? PMD_SECT_NG : 0)

#ifndef CONFIG_ARM64_LPA2
#define lpa2_is_enabled()	false
#define PTE_MAYBE_SHARED	PTE_SHARED
#define PMD_MAYBE_SHARED	PMD_SECT_S
#define PHYS_MASK_SHIFT		(CONFIG_ARM64_PA_BITS)
#else
static inline bool __pure lpa2_is_enabled(void)
{
	return read_tcr() & TCR_DS;
}

#define PTE_MAYBE_SHARED	(lpa2_is_enabled() ? 0 : PTE_SHARED)
#define PMD_MAYBE_SHARED	(lpa2_is_enabled() ? 0 : PMD_SECT_S)
#define PHYS_MASK_SHIFT		(lpa2_is_enabled() ? CONFIG_ARM64_PA_BITS : 48)
#endif

/*
 * Highest possible physical address supported.
 */
#define PHYS_MASK		((UL(1) << PHYS_MASK_SHIFT) - 1)

/*
 * If we have userspace only BTI we don't want to mark kernel pages
 * guarded even if the system does support BTI.
 */
#define PTE_MAYBE_GP		(system_supports_bti_kernel() ? PTE_GP : 0)

#define PAGE_KERNEL		__pgprot(_PAGE_KERNEL)
#define PAGE_KERNEL_RO		__pgprot(_PAGE_KERNEL_RO)
#define PAGE_KERNEL_ROX		__pgprot(_PAGE_KERNEL_ROX)
#define PAGE_KERNEL_EXEC	__pgprot(_PAGE_KERNEL_EXEC)
#define PAGE_KERNEL_EXEC_CONT	__pgprot(_PAGE_KERNEL_EXEC_CONT)

#define PAGE_S2_MEMATTR(attr, has_fwb)					\
	({								\
		u64 __val;						\
		if (has_fwb)						\
			__val = PTE_S2_MEMATTR(MT_S2_FWB_ ## attr);	\
		else							\
			__val = PTE_S2_MEMATTR(MT_S2_ ## attr);		\
		__val;							\
	 })

#define PAGE_NONE		__pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PRESENT_INVALID | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
/* shared+writable pages are clean by default, hence PTE_RDONLY|PTE_WRITE */
#define PAGE_SHARED		__pgprot(_PAGE_SHARED)
#define PAGE_SHARED_EXEC	__pgprot(_PAGE_SHARED_EXEC)
#define PAGE_READONLY		__pgprot(_PAGE_READONLY)
#define PAGE_READONLY_EXEC	__pgprot(_PAGE_READONLY_EXEC)
#define PAGE_EXECONLY		__pgprot(_PAGE_EXECONLY)

#endif /* __ASSEMBLY__ */

#define pte_pi_index(pte) ( \
	((pte & BIT(PTE_PI_IDX_3)) >> (PTE_PI_IDX_3 - 3)) | \
	((pte & BIT(PTE_PI_IDX_2)) >> (PTE_PI_IDX_2 - 2)) | \
	((pte & BIT(PTE_PI_IDX_1)) >> (PTE_PI_IDX_1 - 1)) | \
	((pte & BIT(PTE_PI_IDX_0)) >> (PTE_PI_IDX_0 - 0)))

/*
 * Page types used via Permission Indirection Extension (PIE). PIE uses
 * the USER, DBM, PXN and UXN bits to to generate an index which is used
 * to look up the actual permission in PIR_ELx and PIRE0_EL1. We define
 * combinations we use on non-PIE systems with the same encoding, for
 * convenience these are listed here as comments as are the unallocated
 * encodings.
 */

/* 0: PAGE_DEFAULT                                                  */
/* 1:                                                      PTE_USER */
/* 2:                                          PTE_WRITE            */
/* 3:                                          PTE_WRITE | PTE_USER */
/* 4: PAGE_EXECONLY                  PTE_PXN                        */
/* 5: PAGE_READONLY_EXEC             PTE_PXN |             PTE_USER */
/* 6:                                PTE_PXN | PTE_WRITE            */
/* 7: PAGE_SHARED_EXEC               PTE_PXN | PTE_WRITE | PTE_USER */
/* 8: PAGE_KERNEL_ROX      PTE_UXN                                  */
/* 9: PAGE_GCS_RO          PTE_UXN |                       PTE_USER */
/* a: PAGE_KERNEL_EXEC     PTE_UXN |           PTE_WRITE            */
/* b: PAGE_GCS             PTE_UXN |           PTE_WRITE | PTE_USER */
/* c: PAGE_KERNEL_RO       PTE_UXN | PTE_PXN                        */
/* d: PAGE_READONLY        PTE_UXN | PTE_PXN |             PTE_USER */
/* e: PAGE_KERNEL          PTE_UXN | PTE_PXN | PTE_WRITE            */
/* f: PAGE_SHARED          PTE_UXN | PTE_PXN | PTE_WRITE | PTE_USER */

#define _PAGE_GCS	(_PAGE_DEFAULT | PTE_NG | PTE_UXN | PTE_WRITE | PTE_USER)
#define _PAGE_GCS_RO	(_PAGE_DEFAULT | PTE_NG | PTE_UXN | PTE_USER)

#define PAGE_GCS	__pgprot(_PAGE_GCS)
#define PAGE_GCS_RO	__pgprot(_PAGE_GCS_RO)

#define PIE_E0	( \
	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS),           PIE_GCS)  | \
	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS_RO),        PIE_R)   | \
	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_EXECONLY),      PIE_X_O) | \
	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_READONLY_EXEC), PIE_RX_O)  | \
	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_SHARED_EXEC),   PIE_RWX_O) | \
	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_READONLY),      PIE_R_O)   | \
	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_SHARED),        PIE_RW_O))

#define PIE_E1	( \
	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS),           PIE_NONE_O) | \
	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS_RO),        PIE_NONE_O) | \
	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_EXECONLY),      PIE_NONE_O) | \
	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_READONLY_EXEC), PIE_R)      | \
	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_SHARED_EXEC),   PIE_RW)     | \
	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_READONLY),      PIE_R)      | \
	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_SHARED),        PIE_RW)     | \
	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_KERNEL_ROX),    PIE_RX)     | \
	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_KERNEL_EXEC),   PIE_RWX)    | \
	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_KERNEL_RO),     PIE_R)      | \
	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_KERNEL),        PIE_RW))

#endif /* __ASM_PGTABLE_PROT_H */
Commit	Line	Data
caab277b	1	/* SPDX-License-Identifier: GPL-2.0-only */
3eca86e7 MR	2	/*
3eca86e7 MR	3	* Copyright (C) 2016 ARM Ltd.
3eca86e7 MR	4	*/
	5	#ifndef __ASM_PGTABLE_PROT_H
	6	#define __ASM_PGTABLE_PROT_H
	7
	8	#include <asm/memory.h>
	9	#include <asm/pgtable-hwdef.h>
	10
	11	#include <linux/const.h>
	12
	13	/*
	14	* Software defined PTE bits definition.
	15	*/
3eca86e7	16	#define PTE_WRITE (PTE_DBM) /* same as DBM (51) */
570ef363	17	#define PTE_SWP_EXCLUSIVE (_AT(pteval_t, 1) << 2) /* only for swp ptes */
3eca86e7 MR	18	#define PTE_DIRTY (_AT(pteval_t, 1) << 55)
3eca86e7 MR	19	#define PTE_SPECIAL (_AT(pteval_t, 1) << 56)
73b20c84	20	#define PTE_DEVMAP (_AT(pteval_t, 1) << 57)
3eca86e7	21
b65399f6	22	/*
b28c74e2 RR	23	* PTE_PRESENT_INVALID=1 & PTE_VALID=0 indicates that the pte's fields should be
	24	* interpreted according to the HW layout by SW but any attempted HW access to
	25	* the address will result in a fault. pte_present() returns true.
b65399f6	26	*/
55564814	27	#define PTE_PRESENT_INVALID (PTE_NG) /* only when !PTE_VALID */
b65399f6	28
5b32510a RR	29	#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
	30	#define PTE_UFFD_WP (_AT(pteval_t, 1) << 58) /* uffd-wp tracking */
	31	#define PTE_SWP_UFFD_WP (_AT(pteval_t, 1) << 3) /* only for swp ptes */
	32	#else
	33	#define PTE_UFFD_WP (_AT(pteval_t, 0))
	34	#define PTE_SWP_UFFD_WP (_AT(pteval_t, 0))
	35	#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
	36
fa4cdcca	37	#define _PROT_DEFAULT (PTE_TYPE_PAGE \| PTE_AF \| PTE_SHARED)
fa4cdcca	38
db95ea78 AB	39	#define PROT_DEFAULT (PTE_TYPE_PAGE \| PTE_MAYBE_NG \| PTE_MAYBE_SHARED \| PTE_AF)
db95ea78 AB	40	#define PROT_SECT_DEFAULT (PMD_TYPE_SECT \| PMD_MAYBE_NG \| PMD_MAYBE_SHARED \| PMD_SECT_AF)
fa4cdcca JG	41
	42	#define PROT_DEVICE_nGnRnE (PROT_DEFAULT \| PTE_PXN \| PTE_UXN \| PTE_WRITE \| PTE_ATTRINDX(MT_DEVICE_nGnRnE))
	43	#define PROT_DEVICE_nGnRE (PROT_DEFAULT \| PTE_PXN \| PTE_UXN \| PTE_WRITE \| PTE_ATTRINDX(MT_DEVICE_nGnRE))
	44	#define PROT_NORMAL_NC (PROT_DEFAULT \| PTE_PXN \| PTE_UXN \| PTE_WRITE \| PTE_ATTRINDX(MT_NORMAL_NC))
	45	#define PROT_NORMAL (PROT_DEFAULT \| PTE_PXN \| PTE_UXN \| PTE_WRITE \| PTE_ATTRINDX(MT_NORMAL))
	46	#define PROT_NORMAL_TAGGED (PROT_DEFAULT \| PTE_PXN \| PTE_UXN \| PTE_WRITE \| PTE_ATTRINDX(MT_NORMAL_TAGGED))
	47
	48	#define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT \| PMD_SECT_PXN \| PMD_SECT_UXN \| PMD_ATTRINDX(MT_DEVICE_nGnRE))
	49	#define PROT_SECT_NORMAL (PROT_SECT_DEFAULT \| PMD_SECT_PXN \| PMD_SECT_UXN \| PTE_WRITE \| PMD_ATTRINDX(MT_NORMAL))
	50	#define PROT_SECT_NORMAL_EXEC (PROT_SECT_DEFAULT \| PMD_SECT_UXN \| PMD_ATTRINDX(MT_NORMAL))
	51
	52	#define _PAGE_DEFAULT (_PROT_DEFAULT \| PTE_ATTRINDX(MT_NORMAL))
	53
	54	#define _PAGE_KERNEL (PROT_NORMAL)
	55	#define _PAGE_KERNEL_RO ((PROT_NORMAL & ~PTE_WRITE) \| PTE_RDONLY)
	56	#define _PAGE_KERNEL_ROX ((PROT_NORMAL & ~(PTE_WRITE \| PTE_PXN)) \| PTE_RDONLY)
	57	#define _PAGE_KERNEL_EXEC (PROT_NORMAL & ~PTE_PXN)
	58	#define _PAGE_KERNEL_EXEC_CONT ((PROT_NORMAL & ~PTE_PXN) \| PTE_CONT)
	59
	60	#define _PAGE_SHARED (_PAGE_DEFAULT \| PTE_USER \| PTE_RDONLY \| PTE_NG \| PTE_PXN \| PTE_UXN \| PTE_WRITE)
	61	#define _PAGE_SHARED_EXEC (_PAGE_DEFAULT \| PTE_USER \| PTE_RDONLY \| PTE_NG \| PTE_PXN \| PTE_WRITE)
	62	#define _PAGE_READONLY (_PAGE_DEFAULT \| PTE_USER \| PTE_RDONLY \| PTE_NG \| PTE_PXN \| PTE_UXN)
	63	#define _PAGE_READONLY_EXEC (_PAGE_DEFAULT \| PTE_USER \| PTE_RDONLY \| PTE_NG \| PTE_PXN)
	64	#define _PAGE_EXECONLY (_PAGE_DEFAULT \| PTE_RDONLY \| PTE_NG \| PTE_PXN)
	65
3eca86e7 MR	66	#ifndef __ASSEMBLY__
3eca86e7 MR	67
c8027285	68	#include <asm/cpufeature.h>
3eca86e7	69	#include <asm/pgtable-types.h>
39930695	70	#include <asm/rsi.h>
3eca86e7	71
c8355785	72	extern bool arm64_use_ng_mappings;
39930695 SP	73	extern unsigned long prot_ns_shared;
	74
	75	#define PROT_NS_SHARED (is_realm_world() ? prot_ns_shared : 0)
c8355785	76
c8355785 WD	77	#define PTE_MAYBE_NG (arm64_use_ng_mappings ? PTE_NG : 0)
c8355785 WD	78	#define PMD_MAYBE_NG (arm64_use_ng_mappings ? PMD_SECT_NG : 0)
41acec62	79
db95ea78	80	#ifndef CONFIG_ARM64_LPA2
936a4ec2	81	#define lpa2_is_enabled() false
db95ea78 AB	82	#define PTE_MAYBE_SHARED PTE_SHARED
db95ea78 AB	83	#define PMD_MAYBE_SHARED PMD_SECT_S
bf74bb73	84	#define PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS)
db95ea78 AB	85	#else
	86	static inline bool __pure lpa2_is_enabled(void)
	87	{
	88	return read_tcr() & TCR_DS;
	89	}
	90
	91	#define PTE_MAYBE_SHARED (lpa2_is_enabled() ? 0 : PTE_SHARED)
	92	#define PMD_MAYBE_SHARED (lpa2_is_enabled() ? 0 : PMD_SECT_S)
bf74bb73	93	#define PHYS_MASK_SHIFT (lpa2_is_enabled() ? CONFIG_ARM64_PA_BITS : 48)
db95ea78	94	#endif
936a4ec2	95
bf74bb73 AB	96	/*
	97	* Highest possible physical address supported.
	98	*/
	99	#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
	100
e4e9f6df MB	101	/*
	102	* If we have userspace only BTI we don't want to mark kernel pages
	103	* guarded even if the system does support BTI.
	104	*/
bbbb6577	105	#define PTE_MAYBE_GP (system_supports_bti_kernel() ? PTE_GP : 0)
c8027285	106
fa4cdcca JG	107	#define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
	108	#define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL_RO)
	109	#define PAGE_KERNEL_ROX __pgprot(_PAGE_KERNEL_ROX)
	110	#define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL_EXEC)
	111	#define PAGE_KERNEL_EXEC_CONT __pgprot(_PAGE_KERNEL_EXEC_CONT)
3eca86e7	112
bc224df1	113	#define PAGE_S2_MEMATTR(attr, has_fwb) \
e48d53a9 MZ	114	({ \
e48d53a9 MZ	115	u64 __val; \
bc224df1	116	if (has_fwb) \
e48d53a9 MZ	117	__val = PTE_S2_MEMATTR(MT_S2_FWB_ ## attr); \
	118	else \
	119	__val = PTE_S2_MEMATTR(MT_S2_ ## attr); \
	120	__val; \
	121	})
	122
f0f5863a	123	#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) \| PTE_PRESENT_INVALID \| PTE_RDONLY \| PTE_NG \| PTE_PXN \| PTE_UXN)
aa57157b	124	/* shared+writable pages are clean by default, hence PTE_RDONLY\|PTE_WRITE */
fa4cdcca JG	125	#define PAGE_SHARED __pgprot(_PAGE_SHARED)
	126	#define PAGE_SHARED_EXEC __pgprot(_PAGE_SHARED_EXEC)
	127	#define PAGE_READONLY __pgprot(_PAGE_READONLY)
	128	#define PAGE_READONLY_EXEC __pgprot(_PAGE_READONLY_EXEC)
	129	#define PAGE_EXECONLY __pgprot(_PAGE_EXECONLY)
3eca86e7	130
3eca86e7 MR	131	#endif /* __ASSEMBLY__ */
3eca86e7 MR	132
eeda243d JG	133	#define pte_pi_index(pte) ( \
	134	((pte & BIT(PTE_PI_IDX_3)) >> (PTE_PI_IDX_3 - 3)) \| \
	135	((pte & BIT(PTE_PI_IDX_2)) >> (PTE_PI_IDX_2 - 2)) \| \
	136	((pte & BIT(PTE_PI_IDX_1)) >> (PTE_PI_IDX_1 - 1)) \| \
	137	((pte & BIT(PTE_PI_IDX_0)) >> (PTE_PI_IDX_0 - 0)))
	138
	139	/*
	140	* Page types used via Permission Indirection Extension (PIE). PIE uses
	141	* the USER, DBM, PXN and UXN bits to to generate an index which is used
	142	* to look up the actual permission in PIR_ELx and PIRE0_EL1. We define
	143	* combinations we use on non-PIE systems with the same encoding, for
	144	* convenience these are listed here as comments as are the unallocated
	145	* encodings.
	146	*/
	147
	148	/* 0: PAGE_DEFAULT */
	149	/* 1: PTE_USER */
	150	/* 2: PTE_WRITE */
	151	/* 3: PTE_WRITE \| PTE_USER */
	152	/* 4: PAGE_EXECONLY PTE_PXN */
	153	/* 5: PAGE_READONLY_EXEC PTE_PXN \| PTE_USER */
	154	/* 6: PTE_PXN \| PTE_WRITE */
	155	/* 7: PAGE_SHARED_EXEC PTE_PXN \| PTE_WRITE \| PTE_USER */
	156	/* 8: PAGE_KERNEL_ROX PTE_UXN */
092055f1	157	/* 9: PAGE_GCS_RO PTE_UXN \| PTE_USER */
eeda243d	158	/* a: PAGE_KERNEL_EXEC PTE_UXN \| PTE_WRITE */
092055f1	159	/* b: PAGE_GCS PTE_UXN \| PTE_WRITE \| PTE_USER */
eeda243d JG	160	/* c: PAGE_KERNEL_RO PTE_UXN \| PTE_PXN */
	161	/* d: PAGE_READONLY PTE_UXN \| PTE_PXN \| PTE_USER */
	162	/* e: PAGE_KERNEL PTE_UXN \| PTE_PXN \| PTE_WRITE */
	163	/* f: PAGE_SHARED PTE_UXN \| PTE_PXN \| PTE_WRITE \| PTE_USER */
	164
092055f1 MB	165	#define _PAGE_GCS (_PAGE_DEFAULT \| PTE_NG \| PTE_UXN \| PTE_WRITE \| PTE_USER)
	166	#define _PAGE_GCS_RO (_PAGE_DEFAULT \| PTE_NG \| PTE_UXN \| PTE_USER)
	167
	168	#define PAGE_GCS __pgprot(_PAGE_GCS)
	169	#define PAGE_GCS_RO __pgprot(_PAGE_GCS_RO)
	170
eeda243d	171	#define PIE_E0 ( \
f91a3a60 KB	172	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS), PIE_GCS) \| \
	173	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS_RO), PIE_R) \| \
	174	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_EXECONLY), PIE_X_O) \| \
	175	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_READONLY_EXEC), PIE_RX_O) \| \
	176	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_SHARED_EXEC), PIE_RWX_O) \| \
	177	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_READONLY), PIE_R_O) \| \
	178	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_SHARED), PIE_RW_O))
eeda243d JG	179
eeda243d JG	180	#define PIE_E1 ( \
f91a3a60 KB	181	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS), PIE_NONE_O) \| \
	182	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS_RO), PIE_NONE_O) \| \
	183	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_EXECONLY), PIE_NONE_O) \| \
	184	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_READONLY_EXEC), PIE_R) \| \
	185	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_SHARED_EXEC), PIE_RW) \| \
	186	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_READONLY), PIE_R) \| \
	187	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_SHARED), PIE_RW) \| \
	188	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_KERNEL_ROX), PIE_RX) \| \
	189	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_KERNEL_EXEC), PIE_RWX) \| \
	190	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_KERNEL_RO), PIE_R) \| \
	191	PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_KERNEL), PIE_RW))
eeda243d	192
3eca86e7	193	#endif /* __ASM_PGTABLE_PROT_H */