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37c43753 MZ |
1 | /* |
2 | * Copyright (C) 2012,2013 - ARM Ltd | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #ifndef __ARM64_KVM_MMU_H__ | |
19 | #define __ARM64_KVM_MMU_H__ | |
20 | ||
21 | #include <asm/page.h> | |
22 | #include <asm/memory.h> | |
20475f78 | 23 | #include <asm/cpufeature.h> |
37c43753 MZ |
24 | |
25 | /* | |
cedbb8b7 | 26 | * As ARMv8.0 only has the TTBR0_EL2 register, we cannot express |
37c43753 MZ |
27 | * "negative" addresses. This makes it impossible to directly share |
28 | * mappings with the kernel. | |
29 | * | |
30 | * Instead, give the HYP mode its own VA region at a fixed offset from | |
31 | * the kernel by just masking the top bits (which are all ones for a | |
32 | * kernel address). | |
cedbb8b7 MZ |
33 | * |
34 | * ARMv8.1 (using VHE) does have a TTBR1_EL2, and doesn't use these | |
35 | * macros (the entire kernel runs at EL2). | |
37c43753 MZ |
36 | */ |
37 | #define HYP_PAGE_OFFSET_SHIFT VA_BITS | |
38 | #define HYP_PAGE_OFFSET_MASK ((UL(1) << HYP_PAGE_OFFSET_SHIFT) - 1) | |
39 | #define HYP_PAGE_OFFSET (PAGE_OFFSET & HYP_PAGE_OFFSET_MASK) | |
40 | ||
41 | /* | |
42 | * Our virtual mapping for the idmap-ed MMU-enable code. Must be | |
43 | * shared across all the page-tables. Conveniently, we use the last | |
44 | * possible page, where no kernel mapping will ever exist. | |
45 | */ | |
46 | #define TRAMPOLINE_VA (HYP_PAGE_OFFSET_MASK & PAGE_MASK) | |
47 | ||
38f791a4 CD |
48 | /* |
49 | * KVM_MMU_CACHE_MIN_PAGES is the number of stage2 page table translation | |
50 | * levels in addition to the PGD and potentially the PUD which are | |
51 | * pre-allocated (we pre-allocate the fake PGD and the PUD when the Stage-2 | |
52 | * tables use one level of tables less than the kernel. | |
53 | */ | |
54 | #ifdef CONFIG_ARM64_64K_PAGES | |
55 | #define KVM_MMU_CACHE_MIN_PAGES 1 | |
56 | #else | |
57 | #define KVM_MMU_CACHE_MIN_PAGES 2 | |
58 | #endif | |
59 | ||
37c43753 MZ |
60 | #ifdef __ASSEMBLY__ |
61 | ||
cedbb8b7 MZ |
62 | #include <asm/alternative.h> |
63 | #include <asm/cpufeature.h> | |
64 | ||
37c43753 MZ |
65 | /* |
66 | * Convert a kernel VA into a HYP VA. | |
67 | * reg: VA to be converted. | |
68 | */ | |
69 | .macro kern_hyp_va reg | |
cedbb8b7 | 70 | alternative_if_not ARM64_HAS_VIRT_HOST_EXTN |
37c43753 | 71 | and \reg, \reg, #HYP_PAGE_OFFSET_MASK |
cedbb8b7 MZ |
72 | alternative_else |
73 | nop | |
74 | alternative_endif | |
37c43753 MZ |
75 | .endm |
76 | ||
77 | #else | |
78 | ||
38f791a4 | 79 | #include <asm/pgalloc.h> |
37c43753 MZ |
80 | #include <asm/cachetype.h> |
81 | #include <asm/cacheflush.h> | |
e4c5a685 AB |
82 | #include <asm/mmu_context.h> |
83 | #include <asm/pgtable.h> | |
37c43753 MZ |
84 | |
85 | #define KERN_TO_HYP(kva) ((unsigned long)kva - PAGE_OFFSET + HYP_PAGE_OFFSET) | |
86 | ||
87 | /* | |
dbff124e | 88 | * We currently only support a 40bit IPA. |
37c43753 | 89 | */ |
dbff124e | 90 | #define KVM_PHYS_SHIFT (40) |
37c43753 MZ |
91 | #define KVM_PHYS_SIZE (1UL << KVM_PHYS_SHIFT) |
92 | #define KVM_PHYS_MASK (KVM_PHYS_SIZE - 1UL) | |
93 | ||
37c43753 MZ |
94 | int create_hyp_mappings(void *from, void *to); |
95 | int create_hyp_io_mappings(void *from, void *to, phys_addr_t); | |
96 | void free_boot_hyp_pgd(void); | |
97 | void free_hyp_pgds(void); | |
98 | ||
957db105 | 99 | void stage2_unmap_vm(struct kvm *kvm); |
37c43753 MZ |
100 | int kvm_alloc_stage2_pgd(struct kvm *kvm); |
101 | void kvm_free_stage2_pgd(struct kvm *kvm); | |
102 | int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa, | |
c40f2f8f | 103 | phys_addr_t pa, unsigned long size, bool writable); |
37c43753 MZ |
104 | |
105 | int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run); | |
106 | ||
107 | void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu); | |
108 | ||
109 | phys_addr_t kvm_mmu_get_httbr(void); | |
110 | phys_addr_t kvm_mmu_get_boot_httbr(void); | |
111 | phys_addr_t kvm_get_idmap_vector(void); | |
67f69197 | 112 | phys_addr_t kvm_get_idmap_start(void); |
37c43753 MZ |
113 | int kvm_mmu_init(void); |
114 | void kvm_clear_hyp_idmap(void); | |
115 | ||
116 | #define kvm_set_pte(ptep, pte) set_pte(ptep, pte) | |
ad361f09 | 117 | #define kvm_set_pmd(pmdp, pmd) set_pmd(pmdp, pmd) |
37c43753 | 118 | |
37c43753 | 119 | static inline void kvm_clean_pgd(pgd_t *pgd) {} |
38f791a4 | 120 | static inline void kvm_clean_pmd(pmd_t *pmd) {} |
37c43753 MZ |
121 | static inline void kvm_clean_pmd_entry(pmd_t *pmd) {} |
122 | static inline void kvm_clean_pte(pte_t *pte) {} | |
123 | static inline void kvm_clean_pte_entry(pte_t *pte) {} | |
124 | ||
125 | static inline void kvm_set_s2pte_writable(pte_t *pte) | |
126 | { | |
127 | pte_val(*pte) |= PTE_S2_RDWR; | |
128 | } | |
129 | ||
ad361f09 CD |
130 | static inline void kvm_set_s2pmd_writable(pmd_t *pmd) |
131 | { | |
132 | pmd_val(*pmd) |= PMD_S2_RDWR; | |
133 | } | |
134 | ||
8199ed0e MS |
135 | static inline void kvm_set_s2pte_readonly(pte_t *pte) |
136 | { | |
137 | pte_val(*pte) = (pte_val(*pte) & ~PTE_S2_RDWR) | PTE_S2_RDONLY; | |
138 | } | |
139 | ||
140 | static inline bool kvm_s2pte_readonly(pte_t *pte) | |
141 | { | |
142 | return (pte_val(*pte) & PTE_S2_RDWR) == PTE_S2_RDONLY; | |
143 | } | |
144 | ||
145 | static inline void kvm_set_s2pmd_readonly(pmd_t *pmd) | |
146 | { | |
147 | pmd_val(*pmd) = (pmd_val(*pmd) & ~PMD_S2_RDWR) | PMD_S2_RDONLY; | |
148 | } | |
149 | ||
150 | static inline bool kvm_s2pmd_readonly(pmd_t *pmd) | |
151 | { | |
152 | return (pmd_val(*pmd) & PMD_S2_RDWR) == PMD_S2_RDONLY; | |
153 | } | |
154 | ||
155 | ||
a3c8bd31 MZ |
156 | #define kvm_pgd_addr_end(addr, end) pgd_addr_end(addr, end) |
157 | #define kvm_pud_addr_end(addr, end) pud_addr_end(addr, end) | |
158 | #define kvm_pmd_addr_end(addr, end) pmd_addr_end(addr, end) | |
159 | ||
38f791a4 CD |
160 | /* |
161 | * In the case where PGDIR_SHIFT is larger than KVM_PHYS_SHIFT, we can address | |
162 | * the entire IPA input range with a single pgd entry, and we would only need | |
163 | * one pgd entry. Note that in this case, the pgd is actually not used by | |
164 | * the MMU for Stage-2 translations, but is merely a fake pgd used as a data | |
165 | * structure for the kernel pgtable macros to work. | |
166 | */ | |
167 | #if PGDIR_SHIFT > KVM_PHYS_SHIFT | |
168 | #define PTRS_PER_S2_PGD_SHIFT 0 | |
169 | #else | |
170 | #define PTRS_PER_S2_PGD_SHIFT (KVM_PHYS_SHIFT - PGDIR_SHIFT) | |
171 | #endif | |
172 | #define PTRS_PER_S2_PGD (1 << PTRS_PER_S2_PGD_SHIFT) | |
38f791a4 | 173 | |
04b8dc85 MZ |
174 | #define kvm_pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_S2_PGD - 1)) |
175 | ||
38f791a4 CD |
176 | /* |
177 | * If we are concatenating first level stage-2 page tables, we would have less | |
178 | * than or equal to 16 pointers in the fake PGD, because that's what the | |
9f25e6ad | 179 | * architecture allows. In this case, (4 - CONFIG_PGTABLE_LEVELS) |
38f791a4 CD |
180 | * represents the first level for the host, and we add 1 to go to the next |
181 | * level (which uses contatenation) for the stage-2 tables. | |
182 | */ | |
183 | #if PTRS_PER_S2_PGD <= 16 | |
9f25e6ad | 184 | #define KVM_PREALLOC_LEVEL (4 - CONFIG_PGTABLE_LEVELS + 1) |
38f791a4 CD |
185 | #else |
186 | #define KVM_PREALLOC_LEVEL (0) | |
187 | #endif | |
188 | ||
38f791a4 CD |
189 | static inline void *kvm_get_hwpgd(struct kvm *kvm) |
190 | { | |
191 | pgd_t *pgd = kvm->arch.pgd; | |
192 | pud_t *pud; | |
193 | ||
194 | if (KVM_PREALLOC_LEVEL == 0) | |
195 | return pgd; | |
196 | ||
197 | pud = pud_offset(pgd, 0); | |
198 | if (KVM_PREALLOC_LEVEL == 1) | |
199 | return pud; | |
200 | ||
201 | BUG_ON(KVM_PREALLOC_LEVEL != 2); | |
202 | return pmd_offset(pud, 0); | |
203 | } | |
204 | ||
a987370f | 205 | static inline unsigned int kvm_get_hwpgd_size(void) |
38f791a4 | 206 | { |
a987370f MZ |
207 | if (KVM_PREALLOC_LEVEL > 0) |
208 | return PTRS_PER_S2_PGD * PAGE_SIZE; | |
209 | return PTRS_PER_S2_PGD * sizeof(pgd_t); | |
38f791a4 CD |
210 | } |
211 | ||
4f853a71 CD |
212 | static inline bool kvm_page_empty(void *ptr) |
213 | { | |
214 | struct page *ptr_page = virt_to_page(ptr); | |
215 | return page_count(ptr_page) == 1; | |
216 | } | |
217 | ||
38f791a4 CD |
218 | #define kvm_pte_table_empty(kvm, ptep) kvm_page_empty(ptep) |
219 | ||
220 | #ifdef __PAGETABLE_PMD_FOLDED | |
221 | #define kvm_pmd_table_empty(kvm, pmdp) (0) | |
222 | #else | |
223 | #define kvm_pmd_table_empty(kvm, pmdp) \ | |
224 | (kvm_page_empty(pmdp) && (!(kvm) || KVM_PREALLOC_LEVEL < 2)) | |
225 | #endif | |
226 | ||
227 | #ifdef __PAGETABLE_PUD_FOLDED | |
228 | #define kvm_pud_table_empty(kvm, pudp) (0) | |
4f853a71 | 229 | #else |
38f791a4 CD |
230 | #define kvm_pud_table_empty(kvm, pudp) \ |
231 | (kvm_page_empty(pudp) && (!(kvm) || KVM_PREALLOC_LEVEL < 1)) | |
4f853a71 | 232 | #endif |
4f853a71 CD |
233 | |
234 | ||
37c43753 MZ |
235 | struct kvm; |
236 | ||
2d58b733 MZ |
237 | #define kvm_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l)) |
238 | ||
239 | static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) | |
37c43753 | 240 | { |
2d58b733 MZ |
241 | return (vcpu_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101; |
242 | } | |
243 | ||
ba049e93 DW |
244 | static inline void __coherent_cache_guest_page(struct kvm_vcpu *vcpu, |
245 | kvm_pfn_t pfn, | |
0d3e4d4f MZ |
246 | unsigned long size, |
247 | bool ipa_uncached) | |
2d58b733 | 248 | { |
0d3e4d4f MZ |
249 | void *va = page_address(pfn_to_page(pfn)); |
250 | ||
840f4bfb | 251 | if (!vcpu_has_cache_enabled(vcpu) || ipa_uncached) |
0d3e4d4f | 252 | kvm_flush_dcache_to_poc(va, size); |
2d58b733 | 253 | |
37c43753 | 254 | if (!icache_is_aliasing()) { /* PIPT */ |
0d3e4d4f MZ |
255 | flush_icache_range((unsigned long)va, |
256 | (unsigned long)va + size); | |
37c43753 MZ |
257 | } else if (!icache_is_aivivt()) { /* non ASID-tagged VIVT */ |
258 | /* any kind of VIPT cache */ | |
259 | __flush_icache_all(); | |
260 | } | |
261 | } | |
262 | ||
363ef89f MZ |
263 | static inline void __kvm_flush_dcache_pte(pte_t pte) |
264 | { | |
265 | struct page *page = pte_page(pte); | |
266 | kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE); | |
267 | } | |
268 | ||
269 | static inline void __kvm_flush_dcache_pmd(pmd_t pmd) | |
270 | { | |
271 | struct page *page = pmd_page(pmd); | |
272 | kvm_flush_dcache_to_poc(page_address(page), PMD_SIZE); | |
273 | } | |
274 | ||
275 | static inline void __kvm_flush_dcache_pud(pud_t pud) | |
276 | { | |
277 | struct page *page = pud_page(pud); | |
278 | kvm_flush_dcache_to_poc(page_address(page), PUD_SIZE); | |
279 | } | |
280 | ||
4fda342c | 281 | #define kvm_virt_to_phys(x) __virt_to_phys((unsigned long)(x)) |
37c43753 | 282 | |
3c1e7165 MZ |
283 | void kvm_set_way_flush(struct kvm_vcpu *vcpu); |
284 | void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled); | |
9d218a1f | 285 | |
e4c5a685 AB |
286 | static inline bool __kvm_cpu_uses_extended_idmap(void) |
287 | { | |
288 | return __cpu_uses_extended_idmap(); | |
289 | } | |
290 | ||
291 | static inline void __kvm_extend_hypmap(pgd_t *boot_hyp_pgd, | |
292 | pgd_t *hyp_pgd, | |
293 | pgd_t *merged_hyp_pgd, | |
294 | unsigned long hyp_idmap_start) | |
295 | { | |
296 | int idmap_idx; | |
297 | ||
298 | /* | |
299 | * Use the first entry to access the HYP mappings. It is | |
300 | * guaranteed to be free, otherwise we wouldn't use an | |
301 | * extended idmap. | |
302 | */ | |
303 | VM_BUG_ON(pgd_val(merged_hyp_pgd[0])); | |
304 | merged_hyp_pgd[0] = __pgd(__pa(hyp_pgd) | PMD_TYPE_TABLE); | |
305 | ||
306 | /* | |
307 | * Create another extended level entry that points to the boot HYP map, | |
308 | * which contains an ID mapping of the HYP init code. We essentially | |
309 | * merge the boot and runtime HYP maps by doing so, but they don't | |
310 | * overlap anyway, so this is fine. | |
311 | */ | |
312 | idmap_idx = hyp_idmap_start >> VA_BITS; | |
313 | VM_BUG_ON(pgd_val(merged_hyp_pgd[idmap_idx])); | |
314 | merged_hyp_pgd[idmap_idx] = __pgd(__pa(boot_hyp_pgd) | PMD_TYPE_TABLE); | |
315 | } | |
316 | ||
20475f78 VM |
317 | static inline unsigned int kvm_get_vmid_bits(void) |
318 | { | |
319 | int reg = read_system_reg(SYS_ID_AA64MMFR1_EL1); | |
320 | ||
28c5dcb2 | 321 | return (cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR1_VMIDBITS_SHIFT) == 2) ? 16 : 8; |
20475f78 VM |
322 | } |
323 | ||
37c43753 MZ |
324 | #endif /* __ASSEMBLY__ */ |
325 | #endif /* __ARM64_KVM_MMU_H__ */ |