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37c43753 MZ |
1 | /* |
2 | * Copyright (C) 2012,2013 - ARM Ltd | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #ifndef __ARM64_KVM_MMU_H__ | |
19 | #define __ARM64_KVM_MMU_H__ | |
20 | ||
21 | #include <asm/page.h> | |
22 | #include <asm/memory.h> | |
20475f78 | 23 | #include <asm/cpufeature.h> |
37c43753 MZ |
24 | |
25 | /* | |
cedbb8b7 | 26 | * As ARMv8.0 only has the TTBR0_EL2 register, we cannot express |
37c43753 MZ |
27 | * "negative" addresses. This makes it impossible to directly share |
28 | * mappings with the kernel. | |
29 | * | |
30 | * Instead, give the HYP mode its own VA region at a fixed offset from | |
31 | * the kernel by just masking the top bits (which are all ones for a | |
82a81bff | 32 | * kernel address). We need to find out how many bits to mask. |
cedbb8b7 | 33 | * |
82a81bff MZ |
34 | * We want to build a set of page tables that cover both parts of the |
35 | * idmap (the trampoline page used to initialize EL2), and our normal | |
36 | * runtime VA space, at the same time. | |
37 | * | |
38 | * Given that the kernel uses VA_BITS for its entire address space, | |
39 | * and that half of that space (VA_BITS - 1) is used for the linear | |
40 | * mapping, we can also limit the EL2 space to (VA_BITS - 1). | |
41 | * | |
42 | * The main question is "Within the VA_BITS space, does EL2 use the | |
43 | * top or the bottom half of that space to shadow the kernel's linear | |
44 | * mapping?". As we need to idmap the trampoline page, this is | |
45 | * determined by the range in which this page lives. | |
46 | * | |
47 | * If the page is in the bottom half, we have to use the top half. If | |
48 | * the page is in the top half, we have to use the bottom half: | |
49 | * | |
2077be67 | 50 | * T = __pa_symbol(__hyp_idmap_text_start) |
82a81bff MZ |
51 | * if (T & BIT(VA_BITS - 1)) |
52 | * HYP_VA_MIN = 0 //idmap in upper half | |
53 | * else | |
54 | * HYP_VA_MIN = 1 << (VA_BITS - 1) | |
55 | * HYP_VA_MAX = HYP_VA_MIN + (1 << (VA_BITS - 1)) - 1 | |
56 | * | |
57 | * This of course assumes that the trampoline page exists within the | |
58 | * VA_BITS range. If it doesn't, then it means we're in the odd case | |
59 | * where the kernel idmap (as well as HYP) uses more levels than the | |
60 | * kernel runtime page tables (as seen when the kernel is configured | |
61 | * for 4k pages, 39bits VA, and yet memory lives just above that | |
62 | * limit, forcing the idmap to use 4 levels of page tables while the | |
63 | * kernel itself only uses 3). In this particular case, it doesn't | |
64 | * matter which side of VA_BITS we use, as we're guaranteed not to | |
65 | * conflict with anything. | |
66 | * | |
67 | * When using VHE, there are no separate hyp mappings and all KVM | |
68 | * functionality is already mapped as part of the main kernel | |
69 | * mappings, and none of this applies in that case. | |
37c43753 | 70 | */ |
d53d9bc6 | 71 | |
37c43753 MZ |
72 | #ifdef __ASSEMBLY__ |
73 | ||
cedbb8b7 | 74 | #include <asm/alternative.h> |
cedbb8b7 | 75 | |
37c43753 MZ |
76 | /* |
77 | * Convert a kernel VA into a HYP VA. | |
78 | * reg: VA to be converted. | |
fd81e6bf | 79 | * |
2b4d1606 MZ |
80 | * The actual code generation takes place in kvm_update_va_mask, and |
81 | * the instructions below are only there to reserve the space and | |
82 | * perform the register allocation (kvm_update_va_mask uses the | |
83 | * specific registers encoded in the instructions). | |
37c43753 MZ |
84 | */ |
85 | .macro kern_hyp_va reg | |
2b4d1606 | 86 | alternative_cb kvm_update_va_mask |
ed57cac8 MZ |
87 | and \reg, \reg, #1 /* mask with va_mask */ |
88 | ror \reg, \reg, #1 /* rotate to the first tag bit */ | |
89 | add \reg, \reg, #0 /* insert the low 12 bits of the tag */ | |
90 | add \reg, \reg, #0, lsl 12 /* insert the top 12 bits of the tag */ | |
91 | ror \reg, \reg, #63 /* rotate back */ | |
2b4d1606 | 92 | alternative_cb_end |
37c43753 MZ |
93 | .endm |
94 | ||
95 | #else | |
96 | ||
38f791a4 | 97 | #include <asm/pgalloc.h> |
02f7760e | 98 | #include <asm/cache.h> |
37c43753 | 99 | #include <asm/cacheflush.h> |
e4c5a685 AB |
100 | #include <asm/mmu_context.h> |
101 | #include <asm/pgtable.h> | |
37c43753 | 102 | |
2b4d1606 MZ |
103 | void kvm_update_va_mask(struct alt_instr *alt, |
104 | __le32 *origptr, __le32 *updptr, int nr_inst); | |
105 | ||
fd81e6bf MZ |
106 | static inline unsigned long __kern_hyp_va(unsigned long v) |
107 | { | |
ed57cac8 MZ |
108 | asm volatile(ALTERNATIVE_CB("and %0, %0, #1\n" |
109 | "ror %0, %0, #1\n" | |
110 | "add %0, %0, #0\n" | |
111 | "add %0, %0, #0, lsl 12\n" | |
112 | "ror %0, %0, #63\n", | |
2b4d1606 MZ |
113 | kvm_update_va_mask) |
114 | : "+r" (v)); | |
fd81e6bf MZ |
115 | return v; |
116 | } | |
117 | ||
94d0e598 | 118 | #define kern_hyp_va(v) ((typeof(v))(__kern_hyp_va((unsigned long)(v)))) |
37c43753 | 119 | |
44a497ab MZ |
120 | /* |
121 | * Obtain the PC-relative address of a kernel symbol | |
122 | * s: symbol | |
123 | * | |
124 | * The goal of this macro is to return a symbol's address based on a | |
125 | * PC-relative computation, as opposed to a loading the VA from a | |
126 | * constant pool or something similar. This works well for HYP, as an | |
127 | * absolute VA is guaranteed to be wrong. Only use this if trying to | |
128 | * obtain the address of a symbol (i.e. not something you obtained by | |
129 | * following a pointer). | |
130 | */ | |
131 | #define hyp_symbol_addr(s) \ | |
132 | ({ \ | |
133 | typeof(s) *addr; \ | |
134 | asm("adrp %0, %1\n" \ | |
135 | "add %0, %0, :lo12:%1\n" \ | |
136 | : "=r" (addr) : "S" (&s)); \ | |
137 | addr; \ | |
138 | }) | |
139 | ||
37c43753 | 140 | /* |
dbff124e | 141 | * We currently only support a 40bit IPA. |
37c43753 | 142 | */ |
dbff124e | 143 | #define KVM_PHYS_SHIFT (40) |
e55cac5b | 144 | |
13ac4bbc | 145 | #define kvm_phys_shift(kvm) VTCR_EL2_IPA(kvm->arch.vtcr) |
e55cac5b SP |
146 | #define kvm_phys_size(kvm) (_AC(1, ULL) << kvm_phys_shift(kvm)) |
147 | #define kvm_phys_mask(kvm) (kvm_phys_size(kvm) - _AC(1, ULL)) | |
37c43753 | 148 | |
865b30cd SP |
149 | static inline bool kvm_page_empty(void *ptr) |
150 | { | |
151 | struct page *ptr_page = virt_to_page(ptr); | |
152 | return page_count(ptr_page) == 1; | |
153 | } | |
37c43753 | 154 | |
c0ef6326 SP |
155 | #include <asm/stage2_pgtable.h> |
156 | ||
c8dddecd | 157 | int create_hyp_mappings(void *from, void *to, pgprot_t prot); |
807a3784 | 158 | int create_hyp_io_mappings(phys_addr_t phys_addr, size_t size, |
1bb32a44 MZ |
159 | void __iomem **kaddr, |
160 | void __iomem **haddr); | |
dc2e4633 MZ |
161 | int create_hyp_exec_mappings(phys_addr_t phys_addr, size_t size, |
162 | void **haddr); | |
37c43753 MZ |
163 | void free_hyp_pgds(void); |
164 | ||
957db105 | 165 | void stage2_unmap_vm(struct kvm *kvm); |
37c43753 MZ |
166 | int kvm_alloc_stage2_pgd(struct kvm *kvm); |
167 | void kvm_free_stage2_pgd(struct kvm *kvm); | |
168 | int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa, | |
c40f2f8f | 169 | phys_addr_t pa, unsigned long size, bool writable); |
37c43753 MZ |
170 | |
171 | int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run); | |
172 | ||
173 | void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu); | |
174 | ||
175 | phys_addr_t kvm_mmu_get_httbr(void); | |
37c43753 MZ |
176 | phys_addr_t kvm_get_idmap_vector(void); |
177 | int kvm_mmu_init(void); | |
178 | void kvm_clear_hyp_idmap(void); | |
179 | ||
0db9dd8a MZ |
180 | #define kvm_mk_pmd(ptep) \ |
181 | __pmd(__phys_to_pmd_val(__pa(ptep)) | PMD_TYPE_TABLE) | |
182 | #define kvm_mk_pud(pmdp) \ | |
183 | __pud(__phys_to_pud_val(__pa(pmdp)) | PMD_TYPE_TABLE) | |
184 | #define kvm_mk_pgd(pudp) \ | |
185 | __pgd(__phys_to_pgd_val(__pa(pudp)) | PUD_TYPE_TABLE) | |
186 | ||
f8df7338 PA |
187 | #define kvm_pfn_pte(pfn, prot) pfn_pte(pfn, prot) |
188 | #define kvm_pfn_pmd(pfn, prot) pfn_pmd(pfn, prot) | |
189 | ||
190 | #define kvm_pmd_mkhuge(pmd) pmd_mkhuge(pmd) | |
191 | ||
06485053 | 192 | static inline pte_t kvm_s2pte_mkwrite(pte_t pte) |
37c43753 | 193 | { |
06485053 CM |
194 | pte_val(pte) |= PTE_S2_RDWR; |
195 | return pte; | |
37c43753 MZ |
196 | } |
197 | ||
06485053 | 198 | static inline pmd_t kvm_s2pmd_mkwrite(pmd_t pmd) |
ad361f09 | 199 | { |
06485053 CM |
200 | pmd_val(pmd) |= PMD_S2_RDWR; |
201 | return pmd; | |
ad361f09 CD |
202 | } |
203 | ||
d0e22b4a MZ |
204 | static inline pte_t kvm_s2pte_mkexec(pte_t pte) |
205 | { | |
206 | pte_val(pte) &= ~PTE_S2_XN; | |
207 | return pte; | |
208 | } | |
209 | ||
210 | static inline pmd_t kvm_s2pmd_mkexec(pmd_t pmd) | |
211 | { | |
212 | pmd_val(pmd) &= ~PMD_S2_XN; | |
213 | return pmd; | |
214 | } | |
215 | ||
20a004e7 | 216 | static inline void kvm_set_s2pte_readonly(pte_t *ptep) |
8199ed0e | 217 | { |
0966253d CM |
218 | pteval_t old_pteval, pteval; |
219 | ||
20a004e7 | 220 | pteval = READ_ONCE(pte_val(*ptep)); |
0966253d CM |
221 | do { |
222 | old_pteval = pteval; | |
223 | pteval &= ~PTE_S2_RDWR; | |
224 | pteval |= PTE_S2_RDONLY; | |
20a004e7 | 225 | pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, pteval); |
0966253d | 226 | } while (pteval != old_pteval); |
8199ed0e MS |
227 | } |
228 | ||
20a004e7 | 229 | static inline bool kvm_s2pte_readonly(pte_t *ptep) |
8199ed0e | 230 | { |
20a004e7 | 231 | return (READ_ONCE(pte_val(*ptep)) & PTE_S2_RDWR) == PTE_S2_RDONLY; |
8199ed0e MS |
232 | } |
233 | ||
20a004e7 | 234 | static inline bool kvm_s2pte_exec(pte_t *ptep) |
7a3796d2 | 235 | { |
20a004e7 | 236 | return !(READ_ONCE(pte_val(*ptep)) & PTE_S2_XN); |
7a3796d2 MZ |
237 | } |
238 | ||
20a004e7 | 239 | static inline void kvm_set_s2pmd_readonly(pmd_t *pmdp) |
8199ed0e | 240 | { |
20a004e7 | 241 | kvm_set_s2pte_readonly((pte_t *)pmdp); |
8199ed0e MS |
242 | } |
243 | ||
20a004e7 | 244 | static inline bool kvm_s2pmd_readonly(pmd_t *pmdp) |
8199ed0e | 245 | { |
20a004e7 | 246 | return kvm_s2pte_readonly((pte_t *)pmdp); |
38f791a4 CD |
247 | } |
248 | ||
20a004e7 | 249 | static inline bool kvm_s2pmd_exec(pmd_t *pmdp) |
7a3796d2 | 250 | { |
20a004e7 | 251 | return !(READ_ONCE(pmd_val(*pmdp)) & PMD_S2_XN); |
7a3796d2 MZ |
252 | } |
253 | ||
4ea5af53 PA |
254 | static inline void kvm_set_s2pud_readonly(pud_t *pudp) |
255 | { | |
256 | kvm_set_s2pte_readonly((pte_t *)pudp); | |
257 | } | |
258 | ||
259 | static inline bool kvm_s2pud_readonly(pud_t *pudp) | |
260 | { | |
261 | return kvm_s2pte_readonly((pte_t *)pudp); | |
262 | } | |
263 | ||
86d1c55e PA |
264 | static inline bool kvm_s2pud_exec(pud_t *pudp) |
265 | { | |
266 | return !(READ_ONCE(pud_val(*pudp)) & PUD_S2_XN); | |
267 | } | |
268 | ||
66f877fa | 269 | #define hyp_pte_table_empty(ptep) kvm_page_empty(ptep) |
38f791a4 CD |
270 | |
271 | #ifdef __PAGETABLE_PMD_FOLDED | |
66f877fa | 272 | #define hyp_pmd_table_empty(pmdp) (0) |
38f791a4 | 273 | #else |
66f877fa | 274 | #define hyp_pmd_table_empty(pmdp) kvm_page_empty(pmdp) |
38f791a4 CD |
275 | #endif |
276 | ||
277 | #ifdef __PAGETABLE_PUD_FOLDED | |
66f877fa | 278 | #define hyp_pud_table_empty(pudp) (0) |
4f853a71 | 279 | #else |
66f877fa | 280 | #define hyp_pud_table_empty(pudp) kvm_page_empty(pudp) |
4f853a71 | 281 | #endif |
4f853a71 | 282 | |
37c43753 MZ |
283 | struct kvm; |
284 | ||
2d58b733 MZ |
285 | #define kvm_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l)) |
286 | ||
287 | static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) | |
37c43753 | 288 | { |
8d404c4c | 289 | return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101; |
2d58b733 MZ |
290 | } |
291 | ||
17ab9d57 | 292 | static inline void __clean_dcache_guest_page(kvm_pfn_t pfn, unsigned long size) |
2d58b733 | 293 | { |
0d3e4d4f MZ |
294 | void *va = page_address(pfn_to_page(pfn)); |
295 | ||
e48d53a9 MZ |
296 | /* |
297 | * With FWB, we ensure that the guest always accesses memory using | |
298 | * cacheable attributes, and we don't have to clean to PoC when | |
299 | * faulting in pages. Furthermore, FWB implies IDC, so cleaning to | |
300 | * PoU is not required either in this case. | |
301 | */ | |
302 | if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) | |
303 | return; | |
304 | ||
8f36ebaf | 305 | kvm_flush_dcache_to_poc(va, size); |
a15f6939 | 306 | } |
2d58b733 | 307 | |
17ab9d57 | 308 | static inline void __invalidate_icache_guest_page(kvm_pfn_t pfn, |
a15f6939 MZ |
309 | unsigned long size) |
310 | { | |
87da236e | 311 | if (icache_is_aliasing()) { |
37c43753 MZ |
312 | /* any kind of VIPT cache */ |
313 | __flush_icache_all(); | |
87da236e WD |
314 | } else if (is_kernel_in_hyp_mode() || !icache_is_vpipt()) { |
315 | /* PIPT or VPIPT at EL2 (see comment in __kvm_tlb_flush_vmid_ipa) */ | |
a15f6939 MZ |
316 | void *va = page_address(pfn_to_page(pfn)); |
317 | ||
4fee9473 MZ |
318 | invalidate_icache_range((unsigned long)va, |
319 | (unsigned long)va + size); | |
37c43753 MZ |
320 | } |
321 | } | |
322 | ||
363ef89f MZ |
323 | static inline void __kvm_flush_dcache_pte(pte_t pte) |
324 | { | |
e48d53a9 MZ |
325 | if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) { |
326 | struct page *page = pte_page(pte); | |
327 | kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE); | |
328 | } | |
363ef89f MZ |
329 | } |
330 | ||
331 | static inline void __kvm_flush_dcache_pmd(pmd_t pmd) | |
332 | { | |
e48d53a9 MZ |
333 | if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) { |
334 | struct page *page = pmd_page(pmd); | |
335 | kvm_flush_dcache_to_poc(page_address(page), PMD_SIZE); | |
336 | } | |
363ef89f MZ |
337 | } |
338 | ||
339 | static inline void __kvm_flush_dcache_pud(pud_t pud) | |
340 | { | |
e48d53a9 MZ |
341 | if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) { |
342 | struct page *page = pud_page(pud); | |
343 | kvm_flush_dcache_to_poc(page_address(page), PUD_SIZE); | |
344 | } | |
363ef89f MZ |
345 | } |
346 | ||
2077be67 | 347 | #define kvm_virt_to_phys(x) __pa_symbol(x) |
37c43753 | 348 | |
3c1e7165 MZ |
349 | void kvm_set_way_flush(struct kvm_vcpu *vcpu); |
350 | void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled); | |
9d218a1f | 351 | |
e4c5a685 AB |
352 | static inline bool __kvm_cpu_uses_extended_idmap(void) |
353 | { | |
fa2a8445 KM |
354 | return __cpu_uses_extended_idmap_level(); |
355 | } | |
356 | ||
357 | static inline unsigned long __kvm_idmap_ptrs_per_pgd(void) | |
358 | { | |
359 | return idmap_ptrs_per_pgd; | |
e4c5a685 AB |
360 | } |
361 | ||
19338304 KM |
362 | /* |
363 | * Can't use pgd_populate here, because the extended idmap adds an extra level | |
364 | * above CONFIG_PGTABLE_LEVELS (which is 2 or 3 if we're using the extended | |
365 | * idmap), and pgd_populate is only available if CONFIG_PGTABLE_LEVELS = 4. | |
366 | */ | |
e4c5a685 AB |
367 | static inline void __kvm_extend_hypmap(pgd_t *boot_hyp_pgd, |
368 | pgd_t *hyp_pgd, | |
369 | pgd_t *merged_hyp_pgd, | |
370 | unsigned long hyp_idmap_start) | |
371 | { | |
372 | int idmap_idx; | |
75387b92 | 373 | u64 pgd_addr; |
e4c5a685 AB |
374 | |
375 | /* | |
376 | * Use the first entry to access the HYP mappings. It is | |
377 | * guaranteed to be free, otherwise we wouldn't use an | |
378 | * extended idmap. | |
379 | */ | |
380 | VM_BUG_ON(pgd_val(merged_hyp_pgd[0])); | |
75387b92 KM |
381 | pgd_addr = __phys_to_pgd_val(__pa(hyp_pgd)); |
382 | merged_hyp_pgd[0] = __pgd(pgd_addr | PMD_TYPE_TABLE); | |
e4c5a685 AB |
383 | |
384 | /* | |
385 | * Create another extended level entry that points to the boot HYP map, | |
386 | * which contains an ID mapping of the HYP init code. We essentially | |
387 | * merge the boot and runtime HYP maps by doing so, but they don't | |
388 | * overlap anyway, so this is fine. | |
389 | */ | |
390 | idmap_idx = hyp_idmap_start >> VA_BITS; | |
391 | VM_BUG_ON(pgd_val(merged_hyp_pgd[idmap_idx])); | |
75387b92 KM |
392 | pgd_addr = __phys_to_pgd_val(__pa(boot_hyp_pgd)); |
393 | merged_hyp_pgd[idmap_idx] = __pgd(pgd_addr | PMD_TYPE_TABLE); | |
e4c5a685 AB |
394 | } |
395 | ||
20475f78 VM |
396 | static inline unsigned int kvm_get_vmid_bits(void) |
397 | { | |
46823dd1 | 398 | int reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); |
20475f78 | 399 | |
28c5dcb2 | 400 | return (cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR1_VMIDBITS_SHIFT) == 2) ? 16 : 8; |
20475f78 VM |
401 | } |
402 | ||
bf308242 AP |
403 | /* |
404 | * We are not in the kvm->srcu critical section most of the time, so we take | |
405 | * the SRCU read lock here. Since we copy the data from the user page, we | |
406 | * can immediately drop the lock again. | |
407 | */ | |
408 | static inline int kvm_read_guest_lock(struct kvm *kvm, | |
409 | gpa_t gpa, void *data, unsigned long len) | |
410 | { | |
411 | int srcu_idx = srcu_read_lock(&kvm->srcu); | |
412 | int ret = kvm_read_guest(kvm, gpa, data, len); | |
413 | ||
414 | srcu_read_unlock(&kvm->srcu, srcu_idx); | |
415 | ||
416 | return ret; | |
417 | } | |
418 | ||
dee39247 MZ |
419 | #ifdef CONFIG_KVM_INDIRECT_VECTORS |
420 | /* | |
421 | * EL2 vectors can be mapped and rerouted in a number of ways, | |
422 | * depending on the kernel configuration and CPU present: | |
423 | * | |
424 | * - If the CPU has the ARM64_HARDEN_BRANCH_PREDICTOR cap, the | |
425 | * hardening sequence is placed in one of the vector slots, which is | |
426 | * executed before jumping to the real vectors. | |
427 | * | |
428 | * - If the CPU has both the ARM64_HARDEN_EL2_VECTORS cap and the | |
429 | * ARM64_HARDEN_BRANCH_PREDICTOR cap, the slot containing the | |
430 | * hardening sequence is mapped next to the idmap page, and executed | |
431 | * before jumping to the real vectors. | |
432 | * | |
433 | * - If the CPU only has the ARM64_HARDEN_EL2_VECTORS cap, then an | |
434 | * empty slot is selected, mapped next to the idmap page, and | |
435 | * executed before jumping to the real vectors. | |
436 | * | |
437 | * Note that ARM64_HARDEN_EL2_VECTORS is somewhat incompatible with | |
438 | * VHE, as we don't have hypervisor-specific mappings. If the system | |
439 | * is VHE and yet selects this capability, it will be ignored. | |
440 | */ | |
6840bdd7 MZ |
441 | #include <asm/mmu.h> |
442 | ||
dee39247 MZ |
443 | extern void *__kvm_bp_vect_base; |
444 | extern int __kvm_harden_el2_vector_slot; | |
445 | ||
6840bdd7 MZ |
446 | static inline void *kvm_get_hyp_vector(void) |
447 | { | |
448 | struct bp_hardening_data *data = arm64_get_bp_hardening_data(); | |
dee39247 MZ |
449 | void *vect = kern_hyp_va(kvm_ksym_ref(__kvm_hyp_vector)); |
450 | int slot = -1; | |
6840bdd7 | 451 | |
dee39247 MZ |
452 | if (cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR) && data->fn) { |
453 | vect = kern_hyp_va(kvm_ksym_ref(__bp_harden_hyp_vecs_start)); | |
454 | slot = data->hyp_vectors_slot; | |
455 | } | |
6840bdd7 | 456 | |
dee39247 MZ |
457 | if (this_cpu_has_cap(ARM64_HARDEN_EL2_VECTORS) && !has_vhe()) { |
458 | vect = __kvm_bp_vect_base; | |
459 | if (slot == -1) | |
460 | slot = __kvm_harden_el2_vector_slot; | |
6840bdd7 MZ |
461 | } |
462 | ||
dee39247 MZ |
463 | if (slot != -1) |
464 | vect += slot * SZ_2K; | |
465 | ||
6840bdd7 MZ |
466 | return vect; |
467 | } | |
468 | ||
dee39247 | 469 | /* This is only called on a !VHE system */ |
6840bdd7 MZ |
470 | static inline int kvm_map_vectors(void) |
471 | { | |
dee39247 MZ |
472 | /* |
473 | * HBP = ARM64_HARDEN_BRANCH_PREDICTOR | |
474 | * HEL2 = ARM64_HARDEN_EL2_VECTORS | |
475 | * | |
476 | * !HBP + !HEL2 -> use direct vectors | |
477 | * HBP + !HEL2 -> use hardened vectors in place | |
478 | * !HBP + HEL2 -> allocate one vector slot and use exec mapping | |
479 | * HBP + HEL2 -> use hardened vertors and use exec mapping | |
480 | */ | |
481 | if (cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR)) { | |
482 | __kvm_bp_vect_base = kvm_ksym_ref(__bp_harden_hyp_vecs_start); | |
483 | __kvm_bp_vect_base = kern_hyp_va(__kvm_bp_vect_base); | |
484 | } | |
485 | ||
486 | if (cpus_have_const_cap(ARM64_HARDEN_EL2_VECTORS)) { | |
487 | phys_addr_t vect_pa = __pa_symbol(__bp_harden_hyp_vecs_start); | |
488 | unsigned long size = (__bp_harden_hyp_vecs_end - | |
489 | __bp_harden_hyp_vecs_start); | |
490 | ||
491 | /* | |
492 | * Always allocate a spare vector slot, as we don't | |
493 | * know yet which CPUs have a BP hardening slot that | |
494 | * we can reuse. | |
495 | */ | |
496 | __kvm_harden_el2_vector_slot = atomic_inc_return(&arm64_el2_vector_last_slot); | |
497 | BUG_ON(__kvm_harden_el2_vector_slot >= BP_HARDEN_EL2_SLOTS); | |
498 | return create_hyp_exec_mappings(vect_pa, size, | |
499 | &__kvm_bp_vect_base); | |
500 | } | |
501 | ||
4340ba80 | 502 | return 0; |
6840bdd7 | 503 | } |
6840bdd7 MZ |
504 | #else |
505 | static inline void *kvm_get_hyp_vector(void) | |
506 | { | |
3c5e8123 | 507 | return kern_hyp_va(kvm_ksym_ref(__kvm_hyp_vector)); |
6840bdd7 MZ |
508 | } |
509 | ||
510 | static inline int kvm_map_vectors(void) | |
511 | { | |
512 | return 0; | |
513 | } | |
514 | #endif | |
515 | ||
55e3748e MZ |
516 | #ifdef CONFIG_ARM64_SSBD |
517 | DECLARE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required); | |
518 | ||
519 | static inline int hyp_map_aux_data(void) | |
520 | { | |
521 | int cpu, err; | |
522 | ||
523 | for_each_possible_cpu(cpu) { | |
524 | u64 *ptr; | |
525 | ||
526 | ptr = per_cpu_ptr(&arm64_ssbd_callback_required, cpu); | |
527 | err = create_hyp_mappings(ptr, ptr + 1, PAGE_HYP); | |
528 | if (err) | |
529 | return err; | |
530 | } | |
531 | return 0; | |
532 | } | |
533 | #else | |
534 | static inline int hyp_map_aux_data(void) | |
535 | { | |
536 | return 0; | |
537 | } | |
538 | #endif | |
539 | ||
529c4b05 KM |
540 | #define kvm_phys_to_vttbr(addr) phys_to_ttbr(addr) |
541 | ||
59558330 SP |
542 | /* |
543 | * Get the magic number 'x' for VTTBR:BADDR of this KVM instance. | |
544 | * With v8.2 LVA extensions, 'x' should be a minimum of 6 with | |
545 | * 52bit IPS. | |
546 | */ | |
547 | static inline int arm64_vttbr_x(u32 ipa_shift, u32 levels) | |
548 | { | |
549 | int x = ARM64_VTTBR_X(ipa_shift, levels); | |
550 | ||
551 | return (IS_ENABLED(CONFIG_ARM64_PA_BITS_52) && x < 6) ? 6 : x; | |
552 | } | |
553 | ||
554 | static inline u64 vttbr_baddr_mask(u32 ipa_shift, u32 levels) | |
555 | { | |
556 | unsigned int x = arm64_vttbr_x(ipa_shift, levels); | |
557 | ||
558 | return GENMASK_ULL(PHYS_MASK_SHIFT - 1, x); | |
559 | } | |
560 | ||
561 | static inline u64 kvm_vttbr_baddr_mask(struct kvm *kvm) | |
562 | { | |
563 | return vttbr_baddr_mask(kvm_phys_shift(kvm), kvm_stage2_levels(kvm)); | |
564 | } | |
565 | ||
ab510027 VM |
566 | static inline bool kvm_cpu_has_cnp(void) |
567 | { | |
568 | return system_supports_cnp(); | |
569 | } | |
570 | ||
37c43753 MZ |
571 | #endif /* __ASSEMBLY__ */ |
572 | #endif /* __ARM64_KVM_MMU_H__ */ |