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37c43753 MZ |
1 | /* |
2 | * Copyright (C) 2012,2013 - ARM Ltd | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #ifndef __ARM64_KVM_MMU_H__ | |
19 | #define __ARM64_KVM_MMU_H__ | |
20 | ||
21 | #include <asm/page.h> | |
22 | #include <asm/memory.h> | |
20475f78 | 23 | #include <asm/cpufeature.h> |
37c43753 MZ |
24 | |
25 | /* | |
cedbb8b7 | 26 | * As ARMv8.0 only has the TTBR0_EL2 register, we cannot express |
37c43753 MZ |
27 | * "negative" addresses. This makes it impossible to directly share |
28 | * mappings with the kernel. | |
29 | * | |
30 | * Instead, give the HYP mode its own VA region at a fixed offset from | |
31 | * the kernel by just masking the top bits (which are all ones for a | |
82a81bff | 32 | * kernel address). We need to find out how many bits to mask. |
cedbb8b7 | 33 | * |
82a81bff MZ |
34 | * We want to build a set of page tables that cover both parts of the |
35 | * idmap (the trampoline page used to initialize EL2), and our normal | |
36 | * runtime VA space, at the same time. | |
37 | * | |
38 | * Given that the kernel uses VA_BITS for its entire address space, | |
39 | * and that half of that space (VA_BITS - 1) is used for the linear | |
40 | * mapping, we can also limit the EL2 space to (VA_BITS - 1). | |
41 | * | |
42 | * The main question is "Within the VA_BITS space, does EL2 use the | |
43 | * top or the bottom half of that space to shadow the kernel's linear | |
44 | * mapping?". As we need to idmap the trampoline page, this is | |
45 | * determined by the range in which this page lives. | |
46 | * | |
47 | * If the page is in the bottom half, we have to use the top half. If | |
48 | * the page is in the top half, we have to use the bottom half: | |
49 | * | |
50 | * T = __virt_to_phys(__hyp_idmap_text_start) | |
51 | * if (T & BIT(VA_BITS - 1)) | |
52 | * HYP_VA_MIN = 0 //idmap in upper half | |
53 | * else | |
54 | * HYP_VA_MIN = 1 << (VA_BITS - 1) | |
55 | * HYP_VA_MAX = HYP_VA_MIN + (1 << (VA_BITS - 1)) - 1 | |
56 | * | |
57 | * This of course assumes that the trampoline page exists within the | |
58 | * VA_BITS range. If it doesn't, then it means we're in the odd case | |
59 | * where the kernel idmap (as well as HYP) uses more levels than the | |
60 | * kernel runtime page tables (as seen when the kernel is configured | |
61 | * for 4k pages, 39bits VA, and yet memory lives just above that | |
62 | * limit, forcing the idmap to use 4 levels of page tables while the | |
63 | * kernel itself only uses 3). In this particular case, it doesn't | |
64 | * matter which side of VA_BITS we use, as we're guaranteed not to | |
65 | * conflict with anything. | |
66 | * | |
67 | * When using VHE, there are no separate hyp mappings and all KVM | |
68 | * functionality is already mapped as part of the main kernel | |
69 | * mappings, and none of this applies in that case. | |
37c43753 | 70 | */ |
d53d9bc6 MZ |
71 | |
72 | #define HYP_PAGE_OFFSET_HIGH_MASK ((UL(1) << VA_BITS) - 1) | |
73 | #define HYP_PAGE_OFFSET_LOW_MASK ((UL(1) << (VA_BITS - 1)) - 1) | |
74 | ||
75 | /* Temporary compat define */ | |
76 | #define HYP_PAGE_OFFSET_MASK HYP_PAGE_OFFSET_HIGH_MASK | |
37c43753 MZ |
77 | |
78 | /* | |
79 | * Our virtual mapping for the idmap-ed MMU-enable code. Must be | |
80 | * shared across all the page-tables. Conveniently, we use the last | |
81 | * possible page, where no kernel mapping will ever exist. | |
82 | */ | |
83 | #define TRAMPOLINE_VA (HYP_PAGE_OFFSET_MASK & PAGE_MASK) | |
84 | ||
85 | #ifdef __ASSEMBLY__ | |
86 | ||
cedbb8b7 MZ |
87 | #include <asm/alternative.h> |
88 | #include <asm/cpufeature.h> | |
89 | ||
37c43753 MZ |
90 | /* |
91 | * Convert a kernel VA into a HYP VA. | |
92 | * reg: VA to be converted. | |
fd81e6bf MZ |
93 | * |
94 | * This generates the following sequences: | |
95 | * - High mask: | |
96 | * and x0, x0, #HYP_PAGE_OFFSET_HIGH_MASK | |
97 | * nop | |
98 | * - Low mask: | |
99 | * and x0, x0, #HYP_PAGE_OFFSET_HIGH_MASK | |
100 | * and x0, x0, #HYP_PAGE_OFFSET_LOW_MASK | |
101 | * - VHE: | |
102 | * nop | |
103 | * nop | |
104 | * | |
105 | * The "low mask" version works because the mask is a strict subset of | |
106 | * the "high mask", hence performing the first mask for nothing. | |
107 | * Should be completely invisible on any viable CPU. | |
37c43753 MZ |
108 | */ |
109 | .macro kern_hyp_va reg | |
fd81e6bf MZ |
110 | alternative_if_not ARM64_HAS_VIRT_HOST_EXTN |
111 | and \reg, \reg, #HYP_PAGE_OFFSET_HIGH_MASK | |
cedbb8b7 MZ |
112 | alternative_else |
113 | nop | |
114 | alternative_endif | |
fd81e6bf MZ |
115 | alternative_if_not ARM64_HYP_OFFSET_LOW |
116 | nop | |
117 | alternative_else | |
118 | and \reg, \reg, #HYP_PAGE_OFFSET_LOW_MASK | |
119 | alternative_endif | |
37c43753 MZ |
120 | .endm |
121 | ||
122 | #else | |
123 | ||
38f791a4 | 124 | #include <asm/pgalloc.h> |
37c43753 MZ |
125 | #include <asm/cachetype.h> |
126 | #include <asm/cacheflush.h> | |
e4c5a685 AB |
127 | #include <asm/mmu_context.h> |
128 | #include <asm/pgtable.h> | |
37c43753 | 129 | |
fd81e6bf MZ |
130 | static inline unsigned long __kern_hyp_va(unsigned long v) |
131 | { | |
132 | asm volatile(ALTERNATIVE("and %0, %0, %1", | |
133 | "nop", | |
134 | ARM64_HAS_VIRT_HOST_EXTN) | |
135 | : "+r" (v) | |
136 | : "i" (HYP_PAGE_OFFSET_HIGH_MASK)); | |
137 | asm volatile(ALTERNATIVE("nop", | |
138 | "and %0, %0, %1", | |
139 | ARM64_HYP_OFFSET_LOW) | |
140 | : "+r" (v) | |
141 | : "i" (HYP_PAGE_OFFSET_LOW_MASK)); | |
142 | return v; | |
143 | } | |
144 | ||
145 | #define kern_hyp_va(v) (typeof(v))(__kern_hyp_va((unsigned long)(v))) | |
146 | #define KERN_TO_HYP(v) kern_hyp_va(v) | |
37c43753 MZ |
147 | |
148 | /* | |
dbff124e | 149 | * We currently only support a 40bit IPA. |
37c43753 | 150 | */ |
dbff124e | 151 | #define KVM_PHYS_SHIFT (40) |
37c43753 MZ |
152 | #define KVM_PHYS_SIZE (1UL << KVM_PHYS_SHIFT) |
153 | #define KVM_PHYS_MASK (KVM_PHYS_SIZE - 1UL) | |
154 | ||
c0ef6326 SP |
155 | #include <asm/stage2_pgtable.h> |
156 | ||
c8dddecd | 157 | int create_hyp_mappings(void *from, void *to, pgprot_t prot); |
37c43753 | 158 | int create_hyp_io_mappings(void *from, void *to, phys_addr_t); |
37c43753 MZ |
159 | void free_hyp_pgds(void); |
160 | ||
957db105 | 161 | void stage2_unmap_vm(struct kvm *kvm); |
37c43753 MZ |
162 | int kvm_alloc_stage2_pgd(struct kvm *kvm); |
163 | void kvm_free_stage2_pgd(struct kvm *kvm); | |
164 | int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa, | |
c40f2f8f | 165 | phys_addr_t pa, unsigned long size, bool writable); |
37c43753 MZ |
166 | |
167 | int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run); | |
168 | ||
169 | void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu); | |
170 | ||
171 | phys_addr_t kvm_mmu_get_httbr(void); | |
37c43753 | 172 | phys_addr_t kvm_get_idmap_vector(void); |
67f69197 | 173 | phys_addr_t kvm_get_idmap_start(void); |
37c43753 MZ |
174 | int kvm_mmu_init(void); |
175 | void kvm_clear_hyp_idmap(void); | |
176 | ||
177 | #define kvm_set_pte(ptep, pte) set_pte(ptep, pte) | |
ad361f09 | 178 | #define kvm_set_pmd(pmdp, pmd) set_pmd(pmdp, pmd) |
37c43753 | 179 | |
37c43753 | 180 | static inline void kvm_clean_pgd(pgd_t *pgd) {} |
38f791a4 | 181 | static inline void kvm_clean_pmd(pmd_t *pmd) {} |
37c43753 MZ |
182 | static inline void kvm_clean_pmd_entry(pmd_t *pmd) {} |
183 | static inline void kvm_clean_pte(pte_t *pte) {} | |
184 | static inline void kvm_clean_pte_entry(pte_t *pte) {} | |
185 | ||
06485053 | 186 | static inline pte_t kvm_s2pte_mkwrite(pte_t pte) |
37c43753 | 187 | { |
06485053 CM |
188 | pte_val(pte) |= PTE_S2_RDWR; |
189 | return pte; | |
37c43753 MZ |
190 | } |
191 | ||
06485053 | 192 | static inline pmd_t kvm_s2pmd_mkwrite(pmd_t pmd) |
ad361f09 | 193 | { |
06485053 CM |
194 | pmd_val(pmd) |= PMD_S2_RDWR; |
195 | return pmd; | |
ad361f09 CD |
196 | } |
197 | ||
8199ed0e MS |
198 | static inline void kvm_set_s2pte_readonly(pte_t *pte) |
199 | { | |
06485053 CM |
200 | pteval_t pteval; |
201 | unsigned long tmp; | |
202 | ||
203 | asm volatile("// kvm_set_s2pte_readonly\n" | |
204 | " prfm pstl1strm, %2\n" | |
205 | "1: ldxr %0, %2\n" | |
206 | " and %0, %0, %3 // clear PTE_S2_RDWR\n" | |
207 | " orr %0, %0, %4 // set PTE_S2_RDONLY\n" | |
208 | " stxr %w1, %0, %2\n" | |
209 | " cbnz %w1, 1b\n" | |
210 | : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*pte)) | |
211 | : "L" (~PTE_S2_RDWR), "L" (PTE_S2_RDONLY)); | |
8199ed0e MS |
212 | } |
213 | ||
214 | static inline bool kvm_s2pte_readonly(pte_t *pte) | |
215 | { | |
216 | return (pte_val(*pte) & PTE_S2_RDWR) == PTE_S2_RDONLY; | |
217 | } | |
218 | ||
219 | static inline void kvm_set_s2pmd_readonly(pmd_t *pmd) | |
220 | { | |
06485053 | 221 | kvm_set_s2pte_readonly((pte_t *)pmd); |
8199ed0e MS |
222 | } |
223 | ||
224 | static inline bool kvm_s2pmd_readonly(pmd_t *pmd) | |
225 | { | |
06485053 | 226 | return kvm_s2pte_readonly((pte_t *)pmd); |
38f791a4 CD |
227 | } |
228 | ||
4f853a71 CD |
229 | static inline bool kvm_page_empty(void *ptr) |
230 | { | |
231 | struct page *ptr_page = virt_to_page(ptr); | |
232 | return page_count(ptr_page) == 1; | |
233 | } | |
234 | ||
66f877fa | 235 | #define hyp_pte_table_empty(ptep) kvm_page_empty(ptep) |
38f791a4 CD |
236 | |
237 | #ifdef __PAGETABLE_PMD_FOLDED | |
66f877fa | 238 | #define hyp_pmd_table_empty(pmdp) (0) |
38f791a4 | 239 | #else |
66f877fa | 240 | #define hyp_pmd_table_empty(pmdp) kvm_page_empty(pmdp) |
38f791a4 CD |
241 | #endif |
242 | ||
243 | #ifdef __PAGETABLE_PUD_FOLDED | |
66f877fa | 244 | #define hyp_pud_table_empty(pudp) (0) |
4f853a71 | 245 | #else |
66f877fa | 246 | #define hyp_pud_table_empty(pudp) kvm_page_empty(pudp) |
4f853a71 | 247 | #endif |
4f853a71 | 248 | |
37c43753 MZ |
249 | struct kvm; |
250 | ||
2d58b733 MZ |
251 | #define kvm_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l)) |
252 | ||
253 | static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) | |
37c43753 | 254 | { |
2d58b733 MZ |
255 | return (vcpu_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101; |
256 | } | |
257 | ||
ba049e93 DW |
258 | static inline void __coherent_cache_guest_page(struct kvm_vcpu *vcpu, |
259 | kvm_pfn_t pfn, | |
0d3e4d4f MZ |
260 | unsigned long size, |
261 | bool ipa_uncached) | |
2d58b733 | 262 | { |
0d3e4d4f MZ |
263 | void *va = page_address(pfn_to_page(pfn)); |
264 | ||
840f4bfb | 265 | if (!vcpu_has_cache_enabled(vcpu) || ipa_uncached) |
0d3e4d4f | 266 | kvm_flush_dcache_to_poc(va, size); |
2d58b733 | 267 | |
37c43753 | 268 | if (!icache_is_aliasing()) { /* PIPT */ |
0d3e4d4f MZ |
269 | flush_icache_range((unsigned long)va, |
270 | (unsigned long)va + size); | |
37c43753 MZ |
271 | } else if (!icache_is_aivivt()) { /* non ASID-tagged VIVT */ |
272 | /* any kind of VIPT cache */ | |
273 | __flush_icache_all(); | |
274 | } | |
275 | } | |
276 | ||
363ef89f MZ |
277 | static inline void __kvm_flush_dcache_pte(pte_t pte) |
278 | { | |
279 | struct page *page = pte_page(pte); | |
280 | kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE); | |
281 | } | |
282 | ||
283 | static inline void __kvm_flush_dcache_pmd(pmd_t pmd) | |
284 | { | |
285 | struct page *page = pmd_page(pmd); | |
286 | kvm_flush_dcache_to_poc(page_address(page), PMD_SIZE); | |
287 | } | |
288 | ||
289 | static inline void __kvm_flush_dcache_pud(pud_t pud) | |
290 | { | |
291 | struct page *page = pud_page(pud); | |
292 | kvm_flush_dcache_to_poc(page_address(page), PUD_SIZE); | |
293 | } | |
294 | ||
4fda342c | 295 | #define kvm_virt_to_phys(x) __virt_to_phys((unsigned long)(x)) |
37c43753 | 296 | |
3c1e7165 MZ |
297 | void kvm_set_way_flush(struct kvm_vcpu *vcpu); |
298 | void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled); | |
9d218a1f | 299 | |
e4c5a685 AB |
300 | static inline bool __kvm_cpu_uses_extended_idmap(void) |
301 | { | |
302 | return __cpu_uses_extended_idmap(); | |
303 | } | |
304 | ||
305 | static inline void __kvm_extend_hypmap(pgd_t *boot_hyp_pgd, | |
306 | pgd_t *hyp_pgd, | |
307 | pgd_t *merged_hyp_pgd, | |
308 | unsigned long hyp_idmap_start) | |
309 | { | |
310 | int idmap_idx; | |
311 | ||
312 | /* | |
313 | * Use the first entry to access the HYP mappings. It is | |
314 | * guaranteed to be free, otherwise we wouldn't use an | |
315 | * extended idmap. | |
316 | */ | |
317 | VM_BUG_ON(pgd_val(merged_hyp_pgd[0])); | |
318 | merged_hyp_pgd[0] = __pgd(__pa(hyp_pgd) | PMD_TYPE_TABLE); | |
319 | ||
320 | /* | |
321 | * Create another extended level entry that points to the boot HYP map, | |
322 | * which contains an ID mapping of the HYP init code. We essentially | |
323 | * merge the boot and runtime HYP maps by doing so, but they don't | |
324 | * overlap anyway, so this is fine. | |
325 | */ | |
326 | idmap_idx = hyp_idmap_start >> VA_BITS; | |
327 | VM_BUG_ON(pgd_val(merged_hyp_pgd[idmap_idx])); | |
328 | merged_hyp_pgd[idmap_idx] = __pgd(__pa(boot_hyp_pgd) | PMD_TYPE_TABLE); | |
329 | } | |
330 | ||
20475f78 VM |
331 | static inline unsigned int kvm_get_vmid_bits(void) |
332 | { | |
333 | int reg = read_system_reg(SYS_ID_AA64MMFR1_EL1); | |
334 | ||
28c5dcb2 | 335 | return (cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR1_VMIDBITS_SHIFT) == 2) ? 16 : 8; |
20475f78 VM |
336 | } |
337 | ||
37c43753 MZ |
338 | #endif /* __ASSEMBLY__ */ |
339 | #endif /* __ARM64_KVM_MMU_H__ */ |