[linux-block.git] / arch / arm64 / include / asm / kvm_host.h

/*
 * Copyright (C) 2012,2013 - ARM Ltd
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * Derived from arch/arm/include/asm/kvm_host.h:
 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __ARM64_KVM_HOST_H__
#define __ARM64_KVM_HOST_H__

#include <linux/types.h>
#include <linux/kvm_types.h>
#include <asm/kvm.h>
#include <asm/kvm_asm.h>
#include <asm/kvm_mmio.h>
#include <asm/kvm_perf_event.h>

#define __KVM_HAVE_ARCH_INTC_INITIALIZED

#define KVM_USER_MEM_SLOTS 32
#define KVM_PRIVATE_MEM_SLOTS 4
#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
#define KVM_HALT_POLL_NS_DEFAULT 500000

#include <kvm/arm_vgic.h>
#include <kvm/arm_arch_timer.h>
#include <kvm/arm_pmu.h>

#define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS

#define KVM_VCPU_MAX_FEATURES 3

int __attribute_const__ kvm_target_cpu(void);
int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
int kvm_arch_dev_ioctl_check_extension(long ext);

struct kvm_arch {
	/* The VMID generation used for the virt. memory system */
	u64    vmid_gen;
	u32    vmid;

	/* 1-level 2nd stage table and lock */
	spinlock_t pgd_lock;
	pgd_t *pgd;

	/* VTTBR value associated with above pgd and vmid */
	u64    vttbr;

	/* The maximum number of vCPUs depends on the used GIC model */
	int max_vcpus;

	/* Interrupt controller */
	struct vgic_dist	vgic;

	/* Timer */
	struct arch_timer_kvm	timer;
};

#define KVM_NR_MEM_OBJS     40

/*
 * We don't want allocation failures within the mmu code, so we preallocate
 * enough memory for a single page fault in a cache.
 */
struct kvm_mmu_memory_cache {
	int nobjs;
	void *objects[KVM_NR_MEM_OBJS];
};

struct kvm_vcpu_fault_info {
	u32 esr_el2;		/* Hyp Syndrom Register */
	u64 far_el2;		/* Hyp Fault Address Register */
	u64 hpfar_el2;		/* Hyp IPA Fault Address Register */
};

/*
 * 0 is reserved as an invalid value.
 * Order should be kept in sync with the save/restore code.
 */
enum vcpu_sysreg {
	__INVALID_SYSREG__,
	MPIDR_EL1,	/* MultiProcessor Affinity Register */
	CSSELR_EL1,	/* Cache Size Selection Register */
	SCTLR_EL1,	/* System Control Register */
	ACTLR_EL1,	/* Auxiliary Control Register */
	CPACR_EL1,	/* Coprocessor Access Control */
	TTBR0_EL1,	/* Translation Table Base Register 0 */
	TTBR1_EL1,	/* Translation Table Base Register 1 */
	TCR_EL1,	/* Translation Control Register */
	ESR_EL1,	/* Exception Syndrome Register */
	AFSR0_EL1,	/* Auxilary Fault Status Register 0 */
	AFSR1_EL1,	/* Auxilary Fault Status Register 1 */
	FAR_EL1,	/* Fault Address Register */
	MAIR_EL1,	/* Memory Attribute Indirection Register */
	VBAR_EL1,	/* Vector Base Address Register */
	CONTEXTIDR_EL1,	/* Context ID Register */
	TPIDR_EL0,	/* Thread ID, User R/W */
	TPIDRRO_EL0,	/* Thread ID, User R/O */
	TPIDR_EL1,	/* Thread ID, Privileged */
	AMAIR_EL1,	/* Aux Memory Attribute Indirection Register */
	CNTKCTL_EL1,	/* Timer Control Register (EL1) */
	PAR_EL1,	/* Physical Address Register */
	MDSCR_EL1,	/* Monitor Debug System Control Register */
	MDCCINT_EL1,	/* Monitor Debug Comms Channel Interrupt Enable Reg */

	/* Performance Monitors Registers */
	PMCR_EL0,	/* Control Register */
	PMSELR_EL0,	/* Event Counter Selection Register */
	PMEVCNTR0_EL0,	/* Event Counter Register (0-30) */
	PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
	PMCCNTR_EL0,	/* Cycle Counter Register */
	PMEVTYPER0_EL0,	/* Event Type Register (0-30) */
	PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
	PMCCFILTR_EL0,	/* Cycle Count Filter Register */
	PMCNTENSET_EL0,	/* Count Enable Set Register */

	/* 32bit specific registers. Keep them at the end of the range */
	DACR32_EL2,	/* Domain Access Control Register */
	IFSR32_EL2,	/* Instruction Fault Status Register */
	FPEXC32_EL2,	/* Floating-Point Exception Control Register */
	DBGVCR32_EL2,	/* Debug Vector Catch Register */

	NR_SYS_REGS	/* Nothing after this line! */
};

/* 32bit mapping */
#define c0_MPIDR	(MPIDR_EL1 * 2)	/* MultiProcessor ID Register */
#define c0_CSSELR	(CSSELR_EL1 * 2)/* Cache Size Selection Register */
#define c1_SCTLR	(SCTLR_EL1 * 2)	/* System Control Register */
#define c1_ACTLR	(ACTLR_EL1 * 2)	/* Auxiliary Control Register */
#define c1_CPACR	(CPACR_EL1 * 2)	/* Coprocessor Access Control */
#define c2_TTBR0	(TTBR0_EL1 * 2)	/* Translation Table Base Register 0 */
#define c2_TTBR0_high	(c2_TTBR0 + 1)	/* TTBR0 top 32 bits */
#define c2_TTBR1	(TTBR1_EL1 * 2)	/* Translation Table Base Register 1 */
#define c2_TTBR1_high	(c2_TTBR1 + 1)	/* TTBR1 top 32 bits */
#define c2_TTBCR	(TCR_EL1 * 2)	/* Translation Table Base Control R. */
#define c3_DACR		(DACR32_EL2 * 2)/* Domain Access Control Register */
#define c5_DFSR		(ESR_EL1 * 2)	/* Data Fault Status Register */
#define c5_IFSR		(IFSR32_EL2 * 2)/* Instruction Fault Status Register */
#define c5_ADFSR	(AFSR0_EL1 * 2)	/* Auxiliary Data Fault Status R */
#define c5_AIFSR	(AFSR1_EL1 * 2)	/* Auxiliary Instr Fault Status R */
#define c6_DFAR		(FAR_EL1 * 2)	/* Data Fault Address Register */
#define c6_IFAR		(c6_DFAR + 1)	/* Instruction Fault Address Register */
#define c7_PAR		(PAR_EL1 * 2)	/* Physical Address Register */
#define c7_PAR_high	(c7_PAR + 1)	/* PAR top 32 bits */
#define c10_PRRR	(MAIR_EL1 * 2)	/* Primary Region Remap Register */
#define c10_NMRR	(c10_PRRR + 1)	/* Normal Memory Remap Register */
#define c12_VBAR	(VBAR_EL1 * 2)	/* Vector Base Address Register */
#define c13_CID		(CONTEXTIDR_EL1 * 2)	/* Context ID Register */
#define c13_TID_URW	(TPIDR_EL0 * 2)	/* Thread ID, User R/W */
#define c13_TID_URO	(TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
#define c13_TID_PRIV	(TPIDR_EL1 * 2)	/* Thread ID, Privileged */
#define c10_AMAIR0	(AMAIR_EL1 * 2)	/* Aux Memory Attr Indirection Reg */
#define c10_AMAIR1	(c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
#define c14_CNTKCTL	(CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */

#define cp14_DBGDSCRext	(MDSCR_EL1 * 2)
#define cp14_DBGBCR0	(DBGBCR0_EL1 * 2)
#define cp14_DBGBVR0	(DBGBVR0_EL1 * 2)
#define cp14_DBGBXVR0	(cp14_DBGBVR0 + 1)
#define cp14_DBGWCR0	(DBGWCR0_EL1 * 2)
#define cp14_DBGWVR0	(DBGWVR0_EL1 * 2)
#define cp14_DBGDCCINT	(MDCCINT_EL1 * 2)

#define NR_COPRO_REGS	(NR_SYS_REGS * 2)

struct kvm_cpu_context {
	struct kvm_regs	gp_regs;
	union {
		u64 sys_regs[NR_SYS_REGS];
		u32 copro[NR_COPRO_REGS];
	};
};

typedef struct kvm_cpu_context kvm_cpu_context_t;

struct kvm_vcpu_arch {
	struct kvm_cpu_context ctxt;

	/* HYP configuration */
	u64 hcr_el2;
	u32 mdcr_el2;

	/* Exception Information */
	struct kvm_vcpu_fault_info fault;

	/* Guest debug state */
	u64 debug_flags;

	/*
	 * We maintain more than a single set of debug registers to support
	 * debugging the guest from the host and to maintain separate host and
	 * guest state during world switches. vcpu_debug_state are the debug
	 * registers of the vcpu as the guest sees them.  host_debug_state are
	 * the host registers which are saved and restored during
	 * world switches. external_debug_state contains the debug
	 * values we want to debug the guest. This is set via the
	 * KVM_SET_GUEST_DEBUG ioctl.
	 *
	 * debug_ptr points to the set of debug registers that should be loaded
	 * onto the hardware when running the guest.
	 */
	struct kvm_guest_debug_arch *debug_ptr;
	struct kvm_guest_debug_arch vcpu_debug_state;
	struct kvm_guest_debug_arch external_debug_state;

	/* Pointer to host CPU context */
	kvm_cpu_context_t *host_cpu_context;
	struct kvm_guest_debug_arch host_debug_state;

	/* VGIC state */
	struct vgic_cpu vgic_cpu;
	struct arch_timer_cpu timer_cpu;
	struct kvm_pmu pmu;

	/*
	 * Anything that is not used directly from assembly code goes
	 * here.
	 */

	/*
	 * Guest registers we preserve during guest debugging.
	 *
	 * These shadow registers are updated by the kvm_handle_sys_reg
	 * trap handler if the guest accesses or updates them while we
	 * are using guest debug.
	 */
	struct {
		u32	mdscr_el1;
	} guest_debug_preserved;

	/* vcpu power-off state */
	bool power_off;

	/* Don't run the guest (internal implementation need) */
	bool pause;

	/* IO related fields */
	struct kvm_decode mmio_decode;

	/* Interrupt related fields */
	u64 irq_lines;		/* IRQ and FIQ levels */

	/* Cache some mmu pages needed inside spinlock regions */
	struct kvm_mmu_memory_cache mmu_page_cache;

	/* Target CPU and feature flags */
	int target;
	DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);

	/* Detect first run of a vcpu */
	bool has_run_once;
};

#define vcpu_gp_regs(v)		(&(v)->arch.ctxt.gp_regs)
#define vcpu_sys_reg(v,r)	((v)->arch.ctxt.sys_regs[(r)])
/*
 * CP14 and CP15 live in the same array, as they are backed by the
 * same system registers.
 */
#define vcpu_cp14(v,r)		((v)->arch.ctxt.copro[(r)])
#define vcpu_cp15(v,r)		((v)->arch.ctxt.copro[(r)])

#ifdef CONFIG_CPU_BIG_ENDIAN
#define vcpu_cp15_64_high(v,r)	vcpu_cp15((v),(r))
#define vcpu_cp15_64_low(v,r)	vcpu_cp15((v),(r) + 1)
#else
#define vcpu_cp15_64_high(v,r)	vcpu_cp15((v),(r) + 1)
#define vcpu_cp15_64_low(v,r)	vcpu_cp15((v),(r))
#endif

struct kvm_vm_stat {
	u32 remote_tlb_flush;
};

struct kvm_vcpu_stat {
	u32 halt_successful_poll;
	u32 halt_attempted_poll;
	u32 halt_wakeup;
	u32 hvc_exit_stat;
	u64 wfe_exit_stat;
	u64 wfi_exit_stat;
	u64 mmio_exit_user;
	u64 mmio_exit_kernel;
	u64 exits;
};

int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);

#define KVM_ARCH_WANT_MMU_NOTIFIER
int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
int kvm_unmap_hva_range(struct kvm *kvm,
			unsigned long start, unsigned long end);
void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);

/* We do not have shadow page tables, hence the empty hooks */
static inline void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
							 unsigned long address)
{
}

struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void);

u64 kvm_call_hyp(void *hypfn, ...);
void force_vm_exit(const cpumask_t *mask);
void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);

int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
		int exception_index);

int kvm_perf_init(void);
int kvm_perf_teardown(void);

struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);

static inline void __cpu_init_hyp_mode(phys_addr_t boot_pgd_ptr,
				       phys_addr_t pgd_ptr,
				       unsigned long hyp_stack_ptr,
				       unsigned long vector_ptr)
{
	/*
	 * Call initialization code, and switch to the full blown
	 * HYP code.
	 */
	kvm_call_hyp((void *)boot_pgd_ptr, pgd_ptr,
		     hyp_stack_ptr, vector_ptr);
}

static inline void kvm_arch_hardware_disable(void) {}
static inline void kvm_arch_hardware_unsetup(void) {}
static inline void kvm_arch_sync_events(struct kvm *kvm) {}
static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}

void kvm_arm_init_debug(void);
void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);

/* #define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__) */

static inline void __cpu_init_stage2(void)
{
	kvm_call_hyp(__init_stage2_translation);
}

#endif /* __ARM64_KVM_HOST_H__ */
Commit	Line	Data
4f8d6632 MZ	1	/*
	2	* Copyright (C) 2012,2013 - ARM Ltd
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* Derived from arch/arm/include/asm/kvm_host.h:
	6	* Copyright (C) 2012 - Virtual Open Systems and Columbia University
	7	* Author: Christoffer Dall <c.dall@virtualopensystems.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#ifndef __ARM64_KVM_HOST_H__
	23	#define __ARM64_KVM_HOST_H__
	24
65647300 PB	25	#include <linux/types.h>
65647300 PB	26	#include <linux/kvm_types.h>
4f8d6632	27	#include <asm/kvm.h>
3a3604bc	28	#include <asm/kvm_asm.h>
4f8d6632	29	#include <asm/kvm_mmio.h>
ad882137	30	#include <asm/kvm_perf_event.h>
4f8d6632	31
c1426e4c EA	32	#define __KVM_HAVE_ARCH_INTC_INITIALIZED
c1426e4c EA	33
4f8d6632 MZ	34	#define KVM_USER_MEM_SLOTS 32
	35	#define KVM_PRIVATE_MEM_SLOTS 4
	36	#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
920552b2	37	#define KVM_HALT_POLL_NS_DEFAULT 500000
4f8d6632 MZ	38
	39	#include <kvm/arm_vgic.h>
	40	#include <kvm/arm_arch_timer.h>
04fe4726	41	#include <kvm/arm_pmu.h>
4f8d6632	42
ef748917 ML	43	#define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
ef748917 ML	44
7d0f84aa	45	#define KVM_VCPU_MAX_FEATURES 3
4f8d6632	46
6951e48b	47	int __attribute_const__ kvm_target_cpu(void);
4f8d6632 MZ	48	int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
	49	int kvm_arch_dev_ioctl_check_extension(long ext);
	50
	51	struct kvm_arch {
	52	/* The VMID generation used for the virt. memory system */
	53	u64 vmid_gen;
	54	u32 vmid;
	55
	56	/* 1-level 2nd stage table and lock */
	57	spinlock_t pgd_lock;
	58	pgd_t *pgd;
	59
	60	/* VTTBR value associated with above pgd and vmid */
	61	u64 vttbr;
	62
3caa2d8c AP	63	/* The maximum number of vCPUs depends on the used GIC model */
	64	int max_vcpus;
	65
4f8d6632 MZ	66	/* Interrupt controller */
	67	struct vgic_dist vgic;
	68
	69	/* Timer */
	70	struct arch_timer_kvm timer;
	71	};
	72
	73	#define KVM_NR_MEM_OBJS 40
	74
	75	/*
	76	* We don't want allocation failures within the mmu code, so we preallocate
	77	* enough memory for a single page fault in a cache.
	78	*/
	79	struct kvm_mmu_memory_cache {
	80	int nobjs;
	81	void *objects[KVM_NR_MEM_OBJS];
	82	};
	83
	84	struct kvm_vcpu_fault_info {
	85	u32 esr_el2; /* Hyp Syndrom Register */
	86	u64 far_el2; /* Hyp Fault Address Register */
	87	u64 hpfar_el2; /* Hyp IPA Fault Address Register */
	88	};
	89
9d8415d6 MZ	90	/*
	91	* 0 is reserved as an invalid value.
	92	* Order should be kept in sync with the save/restore code.
	93	*/
	94	enum vcpu_sysreg {
	95	__INVALID_SYSREG__,
	96	MPIDR_EL1, /* MultiProcessor Affinity Register */
	97	CSSELR_EL1, /* Cache Size Selection Register */
	98	SCTLR_EL1, /* System Control Register */
	99	ACTLR_EL1, /* Auxiliary Control Register */
	100	CPACR_EL1, /* Coprocessor Access Control */
	101	TTBR0_EL1, /* Translation Table Base Register 0 */
	102	TTBR1_EL1, /* Translation Table Base Register 1 */
	103	TCR_EL1, /* Translation Control Register */
	104	ESR_EL1, /* Exception Syndrome Register */
	105	AFSR0_EL1, /* Auxilary Fault Status Register 0 */
	106	AFSR1_EL1, /* Auxilary Fault Status Register 1 */
	107	FAR_EL1, /* Fault Address Register */
	108	MAIR_EL1, /* Memory Attribute Indirection Register */
	109	VBAR_EL1, /* Vector Base Address Register */
	110	CONTEXTIDR_EL1, /* Context ID Register */
	111	TPIDR_EL0, /* Thread ID, User R/W */
	112	TPIDRRO_EL0, /* Thread ID, User R/O */
	113	TPIDR_EL1, /* Thread ID, Privileged */
	114	AMAIR_EL1, /* Aux Memory Attribute Indirection Register */
	115	CNTKCTL_EL1, /* Timer Control Register (EL1) */
	116	PAR_EL1, /* Physical Address Register */
	117	MDSCR_EL1, /* Monitor Debug System Control Register */
	118	MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
	119
ab946834 SZ	120	/* Performance Monitors Registers */
ab946834 SZ	121	PMCR_EL0, /* Control Register */
3965c3ce	122	PMSELR_EL0, /* Event Counter Selection Register */
051ff581 SZ	123	PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
	124	PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
	125	PMCCNTR_EL0, /* Cycle Counter Register */
9feb21ac SZ	126	PMEVTYPER0_EL0, /* Event Type Register (0-30) */
	127	PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
	128	PMCCFILTR_EL0, /* Cycle Count Filter Register */
96b0eebc	129	PMCNTENSET_EL0, /* Count Enable Set Register */
ab946834	130
9d8415d6 MZ	131	/* 32bit specific registers. Keep them at the end of the range */
	132	DACR32_EL2, /* Domain Access Control Register */
	133	IFSR32_EL2, /* Instruction Fault Status Register */
	134	FPEXC32_EL2, /* Floating-Point Exception Control Register */
	135	DBGVCR32_EL2, /* Debug Vector Catch Register */
	136
	137	NR_SYS_REGS /* Nothing after this line! */
	138	};
	139
	140	/* 32bit mapping */
	141	#define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
	142	#define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */
	143	#define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */
	144	#define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */
	145	#define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */
	146	#define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
	147	#define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */
	148	#define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
	149	#define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */
	150	#define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */
	151	#define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */
	152	#define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */
	153	#define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
	154	#define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
	155	#define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
	156	#define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */
	157	#define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */
	158	#define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */
	159	#define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */
	160	#define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */
	161	#define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
	162	#define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
	163	#define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */
	164	#define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */
	165	#define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
	166	#define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */
	167	#define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
	168	#define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
	169	#define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
	170
	171	#define cp14_DBGDSCRext (MDSCR_EL1 * 2)
	172	#define cp14_DBGBCR0 (DBGBCR0_EL1 * 2)
	173	#define cp14_DBGBVR0 (DBGBVR0_EL1 * 2)
	174	#define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1)
	175	#define cp14_DBGWCR0 (DBGWCR0_EL1 * 2)
	176	#define cp14_DBGWVR0 (DBGWVR0_EL1 * 2)
	177	#define cp14_DBGDCCINT (MDCCINT_EL1 * 2)
	178
	179	#define NR_COPRO_REGS (NR_SYS_REGS * 2)
	180
4f8d6632 MZ	181	struct kvm_cpu_context {
4f8d6632 MZ	182	struct kvm_regs gp_regs;
40033a61 MZ	183	union {
40033a61 MZ	184	u64 sys_regs[NR_SYS_REGS];
72564016	185	u32 copro[NR_COPRO_REGS];
40033a61	186	};
4f8d6632 MZ	187	};
	188
	189	typedef struct kvm_cpu_context kvm_cpu_context_t;
	190
	191	struct kvm_vcpu_arch {
	192	struct kvm_cpu_context ctxt;
	193
	194	/* HYP configuration */
	195	u64 hcr_el2;
56c7f5e7	196	u32 mdcr_el2;
4f8d6632 MZ	197
	198	/* Exception Information */
	199	struct kvm_vcpu_fault_info fault;
	200
84e690bf	201	/* Guest debug state */
0c557ed4 MZ	202	u64 debug_flags;
0c557ed4 MZ	203
84e690bf AB	204	/*
	205	* We maintain more than a single set of debug registers to support
	206	* debugging the guest from the host and to maintain separate host and
	207	* guest state during world switches. vcpu_debug_state are the debug
	208	* registers of the vcpu as the guest sees them. host_debug_state are
834bf887 AB	209	* the host registers which are saved and restored during
	210	* world switches. external_debug_state contains the debug
	211	* values we want to debug the guest. This is set via the
	212	* KVM_SET_GUEST_DEBUG ioctl.
84e690bf AB	213	*
	214	* debug_ptr points to the set of debug registers that should be loaded
	215	* onto the hardware when running the guest.
	216	*/
	217	struct kvm_guest_debug_arch *debug_ptr;
	218	struct kvm_guest_debug_arch vcpu_debug_state;
834bf887	219	struct kvm_guest_debug_arch external_debug_state;
84e690bf	220
4f8d6632 MZ	221	/* Pointer to host CPU context */
4f8d6632 MZ	222	kvm_cpu_context_t *host_cpu_context;
84e690bf	223	struct kvm_guest_debug_arch host_debug_state;
4f8d6632 MZ	224
	225	/* VGIC state */
	226	struct vgic_cpu vgic_cpu;
	227	struct arch_timer_cpu timer_cpu;
04fe4726	228	struct kvm_pmu pmu;
4f8d6632 MZ	229
	230	/*
	231	* Anything that is not used directly from assembly code goes
	232	* here.
	233	*/
4f8d6632	234
337b99bf AB	235	/*
	236	* Guest registers we preserve during guest debugging.
	237	*
	238	* These shadow registers are updated by the kvm_handle_sys_reg
	239	* trap handler if the guest accesses or updates them while we
	240	* are using guest debug.
	241	*/
	242	struct {
	243	u32 mdscr_el1;
	244	} guest_debug_preserved;
	245
3781528e EA	246	/* vcpu power-off state */
3781528e EA	247	bool power_off;
4f8d6632	248
3b92830a EA	249	/* Don't run the guest (internal implementation need) */
	250	bool pause;
	251
4f8d6632 MZ	252	/* IO related fields */
	253	struct kvm_decode mmio_decode;
	254
	255	/* Interrupt related fields */
	256	u64 irq_lines; /* IRQ and FIQ levels */
	257
	258	/* Cache some mmu pages needed inside spinlock regions */
	259	struct kvm_mmu_memory_cache mmu_page_cache;
	260
	261	/* Target CPU and feature flags */
6c8c0c4d	262	int target;
4f8d6632 MZ	263	DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
	264
	265	/* Detect first run of a vcpu */
	266	bool has_run_once;
	267	};
	268
	269	#define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs)
	270	#define vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)])
72564016 MZ	271	/*
	272	* CP14 and CP15 live in the same array, as they are backed by the
	273	* same system registers.
	274	*/
	275	#define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)])
	276	#define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)])
4f8d6632	277
f0a3eaff	278	#ifdef CONFIG_CPU_BIG_ENDIAN
dedf97e8 MZ	279	#define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r))
dedf97e8 MZ	280	#define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r) + 1)
f0a3eaff	281	#else
dedf97e8 MZ	282	#define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r) + 1)
dedf97e8 MZ	283	#define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r))
f0a3eaff VK	284	#endif
f0a3eaff VK	285
4f8d6632 MZ	286	struct kvm_vm_stat {
	287	u32 remote_tlb_flush;
	288	};
	289
	290	struct kvm_vcpu_stat {
f7819512	291	u32 halt_successful_poll;
62bea5bf	292	u32 halt_attempted_poll;
4f8d6632	293	u32 halt_wakeup;
b19e6892 AT	294	u32 hvc_exit_stat;
	295	u64 wfe_exit_stat;
	296	u64 wfi_exit_stat;
	297	u64 mmio_exit_user;
	298	u64 mmio_exit_kernel;
	299	u64 exits;
4f8d6632 MZ	300	};
4f8d6632 MZ	301
473bdc0e	302	int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
4f8d6632 MZ	303	unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
4f8d6632 MZ	304	int kvm_arm_copy_reg_indices(struct kvm_vcpu vcpu, u64 __user indices);
4f8d6632 MZ	305	int kvm_arm_get_reg(struct kvm_vcpu vcpu, const struct kvm_one_reg reg);
	306	int kvm_arm_set_reg(struct kvm_vcpu vcpu, const struct kvm_one_reg reg);
	307
	308	#define KVM_ARCH_WANT_MMU_NOTIFIER
4f8d6632 MZ	309	int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
	310	int kvm_unmap_hva_range(struct kvm *kvm,
	311	unsigned long start, unsigned long end);
	312	void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
35307b9a MZ	313	int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
35307b9a MZ	314	int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
4f8d6632 MZ	315
4f8d6632 MZ	316	/* We do not have shadow page tables, hence the empty hooks */
fe71557a TC	317	static inline void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
	318	unsigned long address)
	319	{
	320	}
	321
4f8d6632	322	struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
4000be42	323	struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void);
4f8d6632 MZ	324
4f8d6632 MZ	325	u64 kvm_call_hyp(void *hypfn, ...);
cf5d3188	326	void force_vm_exit(const cpumask_t *mask);
8199ed0e	327	void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);
4f8d6632 MZ	328
	329	int handle_exit(struct kvm_vcpu vcpu, struct kvm_run run,
	330	int exception_index);
	331
	332	int kvm_perf_init(void);
	333	int kvm_perf_teardown(void);
	334
4429fc64 AP	335	struct kvm_vcpu kvm_mpidr_to_vcpu(struct kvm kvm, unsigned long mpidr);
4429fc64 AP	336
092bd143 MZ	337	static inline void __cpu_init_hyp_mode(phys_addr_t boot_pgd_ptr,
	338	phys_addr_t pgd_ptr,
	339	unsigned long hyp_stack_ptr,
	340	unsigned long vector_ptr)
	341	{
	342	/*
	343	* Call initialization code, and switch to the full blown
	344	* HYP code.
	345	*/
	346	kvm_call_hyp((void *)boot_pgd_ptr, pgd_ptr,
	347	hyp_stack_ptr, vector_ptr);
	348	}
	349
13a34e06	350	static inline void kvm_arch_hardware_disable(void) {}
0865e636 RK	351	static inline void kvm_arch_hardware_unsetup(void) {}
	352	static inline void kvm_arch_sync_events(struct kvm *kvm) {}
	353	static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
	354	static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
	355
56c7f5e7 AB	356	void kvm_arm_init_debug(void);
	357	void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
	358	void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
84e690bf	359	void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
56c7f5e7	360
21a4179c MZ	361	/* #define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__) */
	362
	363	static inline void __cpu_init_stage2(void)
	364	{
	365	kvm_call_hyp(__init_stage2_translation);
	366	}
	367
4f8d6632	368	#endif /* __ARM64_KVM_HOST_H__ */