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4f8d6632 MZ |
1 | /* |
2 | * Copyright (C) 2012,2013 - ARM Ltd | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * Derived from arch/arm/include/asm/kvm_host.h: | |
6 | * Copyright (C) 2012 - Virtual Open Systems and Columbia University | |
7 | * Author: Christoffer Dall <c.dall@virtualopensystems.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #ifndef __ARM64_KVM_HOST_H__ | |
23 | #define __ARM64_KVM_HOST_H__ | |
24 | ||
65647300 PB |
25 | #include <linux/types.h> |
26 | #include <linux/kvm_types.h> | |
85738e05 | 27 | #include <asm/arch_gicv3.h> |
63a1e1c9 | 28 | #include <asm/cpufeature.h> |
4f5abad9 | 29 | #include <asm/daifflags.h> |
17eed27b | 30 | #include <asm/fpsimd.h> |
4f8d6632 | 31 | #include <asm/kvm.h> |
3a3604bc | 32 | #include <asm/kvm_asm.h> |
4f8d6632 | 33 | #include <asm/kvm_mmio.h> |
32f13955 | 34 | #include <asm/smp_plat.h> |
e6b673b7 | 35 | #include <asm/thread_info.h> |
4f8d6632 | 36 | |
c1426e4c EA |
37 | #define __KVM_HAVE_ARCH_INTC_INITIALIZED |
38 | ||
955a3fc6 | 39 | #define KVM_USER_MEM_SLOTS 512 |
920552b2 | 40 | #define KVM_HALT_POLL_NS_DEFAULT 500000 |
4f8d6632 MZ |
41 | |
42 | #include <kvm/arm_vgic.h> | |
43 | #include <kvm/arm_arch_timer.h> | |
04fe4726 | 44 | #include <kvm/arm_pmu.h> |
4f8d6632 | 45 | |
ef748917 ML |
46 | #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS |
47 | ||
808e7381 | 48 | #define KVM_VCPU_MAX_FEATURES 4 |
4f8d6632 | 49 | |
7b244e2b | 50 | #define KVM_REQ_SLEEP \ |
2387149e | 51 | KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) |
325f9c64 | 52 | #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) |
358b28f0 | 53 | #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) |
b13216cf | 54 | |
61bbe380 CD |
55 | DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use); |
56 | ||
6951e48b | 57 | int __attribute_const__ kvm_target_cpu(void); |
4f8d6632 | 58 | int kvm_reset_vcpu(struct kvm_vcpu *vcpu); |
375bdd3b | 59 | int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext); |
c612505f | 60 | void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start); |
4f8d6632 | 61 | |
e329fb75 | 62 | struct kvm_vmid { |
4f8d6632 MZ |
63 | /* The VMID generation used for the virt. memory system */ |
64 | u64 vmid_gen; | |
65 | u32 vmid; | |
e329fb75 CD |
66 | }; |
67 | ||
68 | struct kvm_arch { | |
69 | struct kvm_vmid vmid; | |
4f8d6632 | 70 | |
7665f3a8 | 71 | /* stage2 entry level table */ |
4f8d6632 | 72 | pgd_t *pgd; |
e329fb75 | 73 | phys_addr_t pgd_phys; |
4f8d6632 | 74 | |
7665f3a8 SP |
75 | /* VTCR_EL2 value for this VM */ |
76 | u64 vtcr; | |
4f8d6632 | 77 | |
94d0e598 MZ |
78 | /* The last vcpu id that ran on each physical CPU */ |
79 | int __percpu *last_vcpu_ran; | |
80 | ||
3caa2d8c AP |
81 | /* The maximum number of vCPUs depends on the used GIC model */ |
82 | int max_vcpus; | |
83 | ||
4f8d6632 MZ |
84 | /* Interrupt controller */ |
85 | struct vgic_dist vgic; | |
85bd0ba1 MZ |
86 | |
87 | /* Mandated version of PSCI */ | |
88 | u32 psci_version; | |
4f8d6632 MZ |
89 | }; |
90 | ||
91 | #define KVM_NR_MEM_OBJS 40 | |
92 | ||
93 | /* | |
94 | * We don't want allocation failures within the mmu code, so we preallocate | |
95 | * enough memory for a single page fault in a cache. | |
96 | */ | |
97 | struct kvm_mmu_memory_cache { | |
98 | int nobjs; | |
99 | void *objects[KVM_NR_MEM_OBJS]; | |
100 | }; | |
101 | ||
102 | struct kvm_vcpu_fault_info { | |
103 | u32 esr_el2; /* Hyp Syndrom Register */ | |
104 | u64 far_el2; /* Hyp Fault Address Register */ | |
105 | u64 hpfar_el2; /* Hyp IPA Fault Address Register */ | |
0067df41 | 106 | u64 disr_el1; /* Deferred [SError] Status Register */ |
4f8d6632 MZ |
107 | }; |
108 | ||
9d8415d6 MZ |
109 | /* |
110 | * 0 is reserved as an invalid value. | |
111 | * Order should be kept in sync with the save/restore code. | |
112 | */ | |
113 | enum vcpu_sysreg { | |
114 | __INVALID_SYSREG__, | |
115 | MPIDR_EL1, /* MultiProcessor Affinity Register */ | |
116 | CSSELR_EL1, /* Cache Size Selection Register */ | |
117 | SCTLR_EL1, /* System Control Register */ | |
118 | ACTLR_EL1, /* Auxiliary Control Register */ | |
119 | CPACR_EL1, /* Coprocessor Access Control */ | |
120 | TTBR0_EL1, /* Translation Table Base Register 0 */ | |
121 | TTBR1_EL1, /* Translation Table Base Register 1 */ | |
122 | TCR_EL1, /* Translation Control Register */ | |
123 | ESR_EL1, /* Exception Syndrome Register */ | |
ef769e32 AB |
124 | AFSR0_EL1, /* Auxiliary Fault Status Register 0 */ |
125 | AFSR1_EL1, /* Auxiliary Fault Status Register 1 */ | |
9d8415d6 MZ |
126 | FAR_EL1, /* Fault Address Register */ |
127 | MAIR_EL1, /* Memory Attribute Indirection Register */ | |
128 | VBAR_EL1, /* Vector Base Address Register */ | |
129 | CONTEXTIDR_EL1, /* Context ID Register */ | |
130 | TPIDR_EL0, /* Thread ID, User R/W */ | |
131 | TPIDRRO_EL0, /* Thread ID, User R/O */ | |
132 | TPIDR_EL1, /* Thread ID, Privileged */ | |
133 | AMAIR_EL1, /* Aux Memory Attribute Indirection Register */ | |
134 | CNTKCTL_EL1, /* Timer Control Register (EL1) */ | |
135 | PAR_EL1, /* Physical Address Register */ | |
136 | MDSCR_EL1, /* Monitor Debug System Control Register */ | |
137 | MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ | |
c773ae2b | 138 | DISR_EL1, /* Deferred Interrupt Status Register */ |
9d8415d6 | 139 | |
ab946834 SZ |
140 | /* Performance Monitors Registers */ |
141 | PMCR_EL0, /* Control Register */ | |
3965c3ce | 142 | PMSELR_EL0, /* Event Counter Selection Register */ |
051ff581 SZ |
143 | PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ |
144 | PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, | |
145 | PMCCNTR_EL0, /* Cycle Counter Register */ | |
9feb21ac SZ |
146 | PMEVTYPER0_EL0, /* Event Type Register (0-30) */ |
147 | PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, | |
148 | PMCCFILTR_EL0, /* Cycle Count Filter Register */ | |
96b0eebc | 149 | PMCNTENSET_EL0, /* Count Enable Set Register */ |
9db52c78 | 150 | PMINTENSET_EL1, /* Interrupt Enable Set Register */ |
76d883c4 | 151 | PMOVSSET_EL0, /* Overflow Flag Status Set Register */ |
7a0adc70 | 152 | PMSWINC_EL0, /* Software Increment Register */ |
d692b8ad | 153 | PMUSERENR_EL0, /* User Enable Register */ |
ab946834 | 154 | |
9d8415d6 MZ |
155 | /* 32bit specific registers. Keep them at the end of the range */ |
156 | DACR32_EL2, /* Domain Access Control Register */ | |
157 | IFSR32_EL2, /* Instruction Fault Status Register */ | |
158 | FPEXC32_EL2, /* Floating-Point Exception Control Register */ | |
159 | DBGVCR32_EL2, /* Debug Vector Catch Register */ | |
160 | ||
161 | NR_SYS_REGS /* Nothing after this line! */ | |
162 | }; | |
163 | ||
164 | /* 32bit mapping */ | |
165 | #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ | |
166 | #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */ | |
167 | #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */ | |
168 | #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */ | |
169 | #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */ | |
170 | #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */ | |
171 | #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */ | |
172 | #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */ | |
173 | #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */ | |
174 | #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */ | |
175 | #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */ | |
176 | #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */ | |
177 | #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */ | |
178 | #define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */ | |
179 | #define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */ | |
180 | #define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */ | |
181 | #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */ | |
182 | #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */ | |
183 | #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */ | |
184 | #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */ | |
185 | #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */ | |
186 | #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */ | |
187 | #define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */ | |
188 | #define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */ | |
189 | #define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */ | |
190 | #define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */ | |
191 | #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */ | |
192 | #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */ | |
193 | #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */ | |
194 | ||
195 | #define cp14_DBGDSCRext (MDSCR_EL1 * 2) | |
196 | #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2) | |
197 | #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2) | |
198 | #define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1) | |
199 | #define cp14_DBGWCR0 (DBGWCR0_EL1 * 2) | |
200 | #define cp14_DBGWVR0 (DBGWVR0_EL1 * 2) | |
201 | #define cp14_DBGDCCINT (MDCCINT_EL1 * 2) | |
202 | ||
203 | #define NR_COPRO_REGS (NR_SYS_REGS * 2) | |
204 | ||
4f8d6632 MZ |
205 | struct kvm_cpu_context { |
206 | struct kvm_regs gp_regs; | |
40033a61 MZ |
207 | union { |
208 | u64 sys_regs[NR_SYS_REGS]; | |
72564016 | 209 | u32 copro[NR_COPRO_REGS]; |
40033a61 | 210 | }; |
c97e166e JM |
211 | |
212 | struct kvm_vcpu *__hyp_running_vcpu; | |
4f8d6632 MZ |
213 | }; |
214 | ||
215 | typedef struct kvm_cpu_context kvm_cpu_context_t; | |
216 | ||
358b28f0 MZ |
217 | struct vcpu_reset_state { |
218 | unsigned long pc; | |
219 | unsigned long r0; | |
220 | bool be; | |
221 | bool reset; | |
222 | }; | |
223 | ||
4f8d6632 MZ |
224 | struct kvm_vcpu_arch { |
225 | struct kvm_cpu_context ctxt; | |
226 | ||
227 | /* HYP configuration */ | |
228 | u64 hcr_el2; | |
56c7f5e7 | 229 | u32 mdcr_el2; |
4f8d6632 MZ |
230 | |
231 | /* Exception Information */ | |
232 | struct kvm_vcpu_fault_info fault; | |
233 | ||
55e3748e MZ |
234 | /* State of various workarounds, see kvm_asm.h for bit assignment */ |
235 | u64 workaround_flags; | |
236 | ||
fa89d31c DM |
237 | /* Miscellaneous vcpu state flags */ |
238 | u64 flags; | |
0c557ed4 | 239 | |
84e690bf AB |
240 | /* |
241 | * We maintain more than a single set of debug registers to support | |
242 | * debugging the guest from the host and to maintain separate host and | |
243 | * guest state during world switches. vcpu_debug_state are the debug | |
244 | * registers of the vcpu as the guest sees them. host_debug_state are | |
834bf887 AB |
245 | * the host registers which are saved and restored during |
246 | * world switches. external_debug_state contains the debug | |
247 | * values we want to debug the guest. This is set via the | |
248 | * KVM_SET_GUEST_DEBUG ioctl. | |
84e690bf AB |
249 | * |
250 | * debug_ptr points to the set of debug registers that should be loaded | |
251 | * onto the hardware when running the guest. | |
252 | */ | |
253 | struct kvm_guest_debug_arch *debug_ptr; | |
254 | struct kvm_guest_debug_arch vcpu_debug_state; | |
834bf887 | 255 | struct kvm_guest_debug_arch external_debug_state; |
84e690bf | 256 | |
4f8d6632 MZ |
257 | /* Pointer to host CPU context */ |
258 | kvm_cpu_context_t *host_cpu_context; | |
e6b673b7 DM |
259 | |
260 | struct thread_info *host_thread_info; /* hyp VA */ | |
261 | struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */ | |
262 | ||
f85279b4 WD |
263 | struct { |
264 | /* {Break,watch}point registers */ | |
265 | struct kvm_guest_debug_arch regs; | |
266 | /* Statistical profiling extension */ | |
267 | u64 pmscr_el1; | |
268 | } host_debug_state; | |
4f8d6632 MZ |
269 | |
270 | /* VGIC state */ | |
271 | struct vgic_cpu vgic_cpu; | |
272 | struct arch_timer_cpu timer_cpu; | |
04fe4726 | 273 | struct kvm_pmu pmu; |
4f8d6632 MZ |
274 | |
275 | /* | |
276 | * Anything that is not used directly from assembly code goes | |
277 | * here. | |
278 | */ | |
4f8d6632 | 279 | |
337b99bf AB |
280 | /* |
281 | * Guest registers we preserve during guest debugging. | |
282 | * | |
283 | * These shadow registers are updated by the kvm_handle_sys_reg | |
284 | * trap handler if the guest accesses or updates them while we | |
285 | * are using guest debug. | |
286 | */ | |
287 | struct { | |
288 | u32 mdscr_el1; | |
289 | } guest_debug_preserved; | |
290 | ||
3781528e EA |
291 | /* vcpu power-off state */ |
292 | bool power_off; | |
4f8d6632 | 293 | |
3b92830a EA |
294 | /* Don't run the guest (internal implementation need) */ |
295 | bool pause; | |
296 | ||
4f8d6632 MZ |
297 | /* IO related fields */ |
298 | struct kvm_decode mmio_decode; | |
299 | ||
4f8d6632 MZ |
300 | /* Cache some mmu pages needed inside spinlock regions */ |
301 | struct kvm_mmu_memory_cache mmu_page_cache; | |
302 | ||
303 | /* Target CPU and feature flags */ | |
6c8c0c4d | 304 | int target; |
4f8d6632 MZ |
305 | DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES); |
306 | ||
307 | /* Detect first run of a vcpu */ | |
308 | bool has_run_once; | |
4715c14b JM |
309 | |
310 | /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ | |
311 | u64 vsesr_el2; | |
d47533da | 312 | |
358b28f0 MZ |
313 | /* Additional reset state */ |
314 | struct vcpu_reset_state reset_state; | |
315 | ||
d47533da CD |
316 | /* True when deferrable sysregs are loaded on the physical CPU, |
317 | * see kvm_vcpu_load_sysregs and kvm_vcpu_put_sysregs. */ | |
318 | bool sysregs_loaded_on_cpu; | |
4f8d6632 MZ |
319 | }; |
320 | ||
fa89d31c DM |
321 | /* vcpu_arch flags field values: */ |
322 | #define KVM_ARM64_DEBUG_DIRTY (1 << 0) | |
e6b673b7 DM |
323 | #define KVM_ARM64_FP_ENABLED (1 << 1) /* guest FP regs loaded */ |
324 | #define KVM_ARM64_FP_HOST (1 << 2) /* host FP regs loaded */ | |
325 | #define KVM_ARM64_HOST_SVE_IN_USE (1 << 3) /* backup for host TIF_SVE */ | |
b3eb56b6 | 326 | #define KVM_ARM64_HOST_SVE_ENABLED (1 << 4) /* SVE enabled for EL0 */ |
fa89d31c | 327 | |
4f8d6632 | 328 | #define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs) |
8d404c4c CD |
329 | |
330 | /* | |
331 | * Only use __vcpu_sys_reg if you know you want the memory backed version of a | |
332 | * register, and not the one most recently accessed by a running VCPU. For | |
333 | * example, for userspace access or for system registers that are never context | |
334 | * switched, but only emulated. | |
335 | */ | |
336 | #define __vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)]) | |
337 | ||
da6f1666 | 338 | u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg); |
d47533da | 339 | void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg); |
8d404c4c | 340 | |
72564016 MZ |
341 | /* |
342 | * CP14 and CP15 live in the same array, as they are backed by the | |
343 | * same system registers. | |
344 | */ | |
345 | #define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)]) | |
346 | #define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)]) | |
4f8d6632 MZ |
347 | |
348 | struct kvm_vm_stat { | |
8a7e75d4 | 349 | ulong remote_tlb_flush; |
4f8d6632 MZ |
350 | }; |
351 | ||
352 | struct kvm_vcpu_stat { | |
8a7e75d4 SJS |
353 | u64 halt_successful_poll; |
354 | u64 halt_attempted_poll; | |
355 | u64 halt_poll_invalid; | |
356 | u64 halt_wakeup; | |
357 | u64 hvc_exit_stat; | |
b19e6892 AT |
358 | u64 wfe_exit_stat; |
359 | u64 wfi_exit_stat; | |
360 | u64 mmio_exit_user; | |
361 | u64 mmio_exit_kernel; | |
362 | u64 exits; | |
4f8d6632 MZ |
363 | }; |
364 | ||
473bdc0e | 365 | int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init); |
4f8d6632 MZ |
366 | unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); |
367 | int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); | |
4f8d6632 MZ |
368 | int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); |
369 | int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); | |
539aee0e JM |
370 | int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, |
371 | struct kvm_vcpu_events *events); | |
b7b27fac | 372 | |
539aee0e JM |
373 | int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, |
374 | struct kvm_vcpu_events *events); | |
4f8d6632 MZ |
375 | |
376 | #define KVM_ARCH_WANT_MMU_NOTIFIER | |
4f8d6632 MZ |
377 | int kvm_unmap_hva_range(struct kvm *kvm, |
378 | unsigned long start, unsigned long end); | |
748c0e31 | 379 | int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); |
35307b9a MZ |
380 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); |
381 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); | |
4f8d6632 | 382 | |
4f8d6632 | 383 | struct kvm_vcpu *kvm_arm_get_running_vcpu(void); |
4000be42 | 384 | struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void); |
b13216cf CD |
385 | void kvm_arm_halt_guest(struct kvm *kvm); |
386 | void kvm_arm_resume_guest(struct kvm *kvm); | |
4f8d6632 | 387 | |
a0bf9776 | 388 | u64 __kvm_call_hyp(void *hypfn, ...); |
18fc7bf8 MZ |
389 | |
390 | /* | |
391 | * The couple of isb() below are there to guarantee the same behaviour | |
392 | * on VHE as on !VHE, where the eret to EL1 acts as a context | |
393 | * synchronization event. | |
394 | */ | |
395 | #define kvm_call_hyp(f, ...) \ | |
396 | do { \ | |
397 | if (has_vhe()) { \ | |
398 | f(__VA_ARGS__); \ | |
399 | isb(); \ | |
400 | } else { \ | |
401 | __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__); \ | |
402 | } \ | |
403 | } while(0) | |
404 | ||
405 | #define kvm_call_hyp_ret(f, ...) \ | |
406 | ({ \ | |
407 | typeof(f(__VA_ARGS__)) ret; \ | |
408 | \ | |
409 | if (has_vhe()) { \ | |
410 | ret = f(__VA_ARGS__); \ | |
411 | isb(); \ | |
412 | } else { \ | |
413 | ret = __kvm_call_hyp(kvm_ksym_ref(f), \ | |
414 | ##__VA_ARGS__); \ | |
415 | } \ | |
416 | \ | |
417 | ret; \ | |
418 | }) | |
22b39ca3 | 419 | |
cf5d3188 | 420 | void force_vm_exit(const cpumask_t *mask); |
8199ed0e | 421 | void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot); |
4f8d6632 MZ |
422 | |
423 | int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, | |
424 | int exception_index); | |
3368bd80 JM |
425 | void handle_exit_early(struct kvm_vcpu *vcpu, struct kvm_run *run, |
426 | int exception_index); | |
4f8d6632 MZ |
427 | |
428 | int kvm_perf_init(void); | |
429 | int kvm_perf_teardown(void); | |
430 | ||
b7b27fac DG |
431 | void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome); |
432 | ||
4429fc64 AP |
433 | struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); |
434 | ||
4464e210 CD |
435 | DECLARE_PER_CPU(kvm_cpu_context_t, kvm_host_cpu_state); |
436 | ||
32f13955 MZ |
437 | static inline void kvm_init_host_cpu_context(kvm_cpu_context_t *cpu_ctxt, |
438 | int cpu) | |
439 | { | |
440 | /* The host's MPIDR is immutable, so let's set it up at boot time */ | |
441 | cpu_ctxt->sys_regs[MPIDR_EL1] = cpu_logical_map(cpu); | |
442 | } | |
443 | ||
7c36447a WD |
444 | void __kvm_enable_ssbs(void); |
445 | ||
12fda812 | 446 | static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr, |
092bd143 MZ |
447 | unsigned long hyp_stack_ptr, |
448 | unsigned long vector_ptr) | |
449 | { | |
9bc03f1d MZ |
450 | /* |
451 | * Calculate the raw per-cpu offset without a translation from the | |
452 | * kernel's mapping to the linear mapping, and store it in tpidr_el2 | |
453 | * so that we can use adr_l to access per-cpu variables in EL2. | |
454 | */ | |
455 | u64 tpidr_el2 = ((u64)this_cpu_ptr(&kvm_host_cpu_state) - | |
456 | (u64)kvm_ksym_ref(kvm_host_cpu_state)); | |
4464e210 | 457 | |
092bd143 | 458 | /* |
63a1e1c9 MR |
459 | * Call initialization code, and switch to the full blown HYP code. |
460 | * If the cpucaps haven't been finalized yet, something has gone very | |
461 | * wrong, and hyp will crash and burn when it uses any | |
462 | * cpus_have_const_cap() wrapper. | |
092bd143 | 463 | */ |
63a1e1c9 | 464 | BUG_ON(!static_branch_likely(&arm64_const_caps_ready)); |
9bc03f1d | 465 | __kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr, tpidr_el2); |
7c36447a WD |
466 | |
467 | /* | |
468 | * Disabling SSBD on a non-VHE system requires us to enable SSBS | |
469 | * at EL2. | |
470 | */ | |
471 | if (!has_vhe() && this_cpu_has_cap(ARM64_SSBS) && | |
472 | arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) { | |
473 | kvm_call_hyp(__kvm_enable_ssbs); | |
474 | } | |
092bd143 | 475 | } |
67f69197 | 476 | |
33e5f4e5 | 477 | static inline bool kvm_arch_requires_vhe(void) |
85acda3b DM |
478 | { |
479 | /* | |
480 | * The Arm architecture specifies that implementation of SVE | |
481 | * requires VHE also to be implemented. The KVM code for arm64 | |
482 | * relies on this when SVE is present: | |
483 | */ | |
484 | if (system_supports_sve()) | |
85acda3b | 485 | return true; |
33e5f4e5 | 486 | |
8b2cca9a MZ |
487 | /* Some implementations have defects that confine them to VHE */ |
488 | if (cpus_have_cap(ARM64_WORKAROUND_1165522)) | |
489 | return true; | |
490 | ||
33e5f4e5 | 491 | return false; |
85acda3b DM |
492 | } |
493 | ||
0865e636 RK |
494 | static inline void kvm_arch_hardware_unsetup(void) {} |
495 | static inline void kvm_arch_sync_events(struct kvm *kvm) {} | |
496 | static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {} | |
497 | static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} | |
3491caf2 | 498 | static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} |
0865e636 | 499 | |
56c7f5e7 AB |
500 | void kvm_arm_init_debug(void); |
501 | void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); | |
502 | void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); | |
84e690bf | 503 | void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); |
bb0c70bc SZ |
504 | int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, |
505 | struct kvm_device_attr *attr); | |
506 | int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, | |
507 | struct kvm_device_attr *attr); | |
508 | int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, | |
509 | struct kvm_device_attr *attr); | |
56c7f5e7 | 510 | |
0f62f0e9 | 511 | static inline void __cpu_init_stage2(void) {} |
21a4179c | 512 | |
e6b673b7 DM |
513 | /* Guest/host FPSIMD coordination helpers */ |
514 | int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); | |
515 | void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); | |
516 | void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); | |
517 | void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); | |
518 | ||
519 | #ifdef CONFIG_KVM /* Avoid conflicts with core headers if CONFIG_KVM=n */ | |
520 | static inline int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) | |
17eed27b | 521 | { |
e6b673b7 | 522 | return kvm_arch_vcpu_run_map_fp(vcpu); |
17eed27b | 523 | } |
e6b673b7 | 524 | #endif |
17eed27b | 525 | |
4f5abad9 JM |
526 | static inline void kvm_arm_vhe_guest_enter(void) |
527 | { | |
528 | local_daif_mask(); | |
85738e05 JT |
529 | |
530 | /* | |
531 | * Having IRQs masked via PMR when entering the guest means the GIC | |
532 | * will not signal the CPU of interrupts of lower priority, and the | |
533 | * only way to get out will be via guest exceptions. | |
534 | * Naturally, we want to avoid this. | |
535 | */ | |
536 | if (system_uses_irq_prio_masking()) { | |
537 | gic_write_pmr(GIC_PRIO_IRQON); | |
538 | dsb(sy); | |
539 | } | |
4f5abad9 JM |
540 | } |
541 | ||
542 | static inline void kvm_arm_vhe_guest_exit(void) | |
543 | { | |
85738e05 JT |
544 | /* |
545 | * local_daif_restore() takes care to properly restore PSTATE.DAIF | |
546 | * and the GIC PMR if the host is using IRQ priorities. | |
547 | */ | |
4f5abad9 | 548 | local_daif_restore(DAIF_PROCCTX_NOIRQ); |
3f5c90b8 CD |
549 | |
550 | /* | |
551 | * When we exit from the guest we change a number of CPU configuration | |
552 | * parameters, such as traps. Make sure these changes take effect | |
553 | * before running the host or additional guests. | |
554 | */ | |
555 | isb(); | |
4f5abad9 | 556 | } |
6167ec5c MZ |
557 | |
558 | static inline bool kvm_arm_harden_branch_predictor(void) | |
559 | { | |
560 | return cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR); | |
561 | } | |
562 | ||
5d81f7dc MZ |
563 | #define KVM_SSBD_UNKNOWN -1 |
564 | #define KVM_SSBD_FORCE_DISABLE 0 | |
565 | #define KVM_SSBD_KERNEL 1 | |
566 | #define KVM_SSBD_FORCE_ENABLE 2 | |
567 | #define KVM_SSBD_MITIGATED 3 | |
568 | ||
569 | static inline int kvm_arm_have_ssbd(void) | |
570 | { | |
571 | switch (arm64_get_ssbd_state()) { | |
572 | case ARM64_SSBD_FORCE_DISABLE: | |
573 | return KVM_SSBD_FORCE_DISABLE; | |
574 | case ARM64_SSBD_KERNEL: | |
575 | return KVM_SSBD_KERNEL; | |
576 | case ARM64_SSBD_FORCE_ENABLE: | |
577 | return KVM_SSBD_FORCE_ENABLE; | |
578 | case ARM64_SSBD_MITIGATED: | |
579 | return KVM_SSBD_MITIGATED; | |
580 | case ARM64_SSBD_UNKNOWN: | |
581 | default: | |
582 | return KVM_SSBD_UNKNOWN; | |
583 | } | |
584 | } | |
585 | ||
bc192cee CD |
586 | void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu); |
587 | void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu); | |
588 | ||
0f62f0e9 SP |
589 | void kvm_set_ipa_limit(void); |
590 | ||
d1e5b0e9 MO |
591 | #define __KVM_HAVE_ARCH_VM_ALLOC |
592 | struct kvm *kvm_arch_alloc_vm(void); | |
593 | void kvm_arch_free_vm(struct kvm *kvm); | |
594 | ||
bca607eb | 595 | int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type); |
5b6c6742 | 596 | |
4f8d6632 | 597 | #endif /* __ARM64_KVM_HOST_H__ */ |