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4f8d6632 MZ |
1 | /* |
2 | * Copyright (C) 2012,2013 - ARM Ltd | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * Derived from arch/arm/include/asm/kvm_host.h: | |
6 | * Copyright (C) 2012 - Virtual Open Systems and Columbia University | |
7 | * Author: Christoffer Dall <c.dall@virtualopensystems.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #ifndef __ARM64_KVM_HOST_H__ | |
23 | #define __ARM64_KVM_HOST_H__ | |
24 | ||
3f61f409 | 25 | #include <linux/bitmap.h> |
65647300 | 26 | #include <linux/types.h> |
3f61f409 | 27 | #include <linux/jump_label.h> |
65647300 | 28 | #include <linux/kvm_types.h> |
3f61f409 | 29 | #include <linux/percpu.h> |
85738e05 | 30 | #include <asm/arch_gicv3.h> |
3f61f409 | 31 | #include <asm/barrier.h> |
63a1e1c9 | 32 | #include <asm/cpufeature.h> |
4f5abad9 | 33 | #include <asm/daifflags.h> |
17eed27b | 34 | #include <asm/fpsimd.h> |
4f8d6632 | 35 | #include <asm/kvm.h> |
3a3604bc | 36 | #include <asm/kvm_asm.h> |
4f8d6632 | 37 | #include <asm/kvm_mmio.h> |
32f13955 | 38 | #include <asm/smp_plat.h> |
e6b673b7 | 39 | #include <asm/thread_info.h> |
4f8d6632 | 40 | |
c1426e4c EA |
41 | #define __KVM_HAVE_ARCH_INTC_INITIALIZED |
42 | ||
955a3fc6 | 43 | #define KVM_USER_MEM_SLOTS 512 |
920552b2 | 44 | #define KVM_HALT_POLL_NS_DEFAULT 500000 |
4f8d6632 MZ |
45 | |
46 | #include <kvm/arm_vgic.h> | |
47 | #include <kvm/arm_arch_timer.h> | |
04fe4726 | 48 | #include <kvm/arm_pmu.h> |
4f8d6632 | 49 | |
ef748917 ML |
50 | #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS |
51 | ||
9a3cdf26 | 52 | #define KVM_VCPU_MAX_FEATURES 5 |
4f8d6632 | 53 | |
7b244e2b | 54 | #define KVM_REQ_SLEEP \ |
2387149e | 55 | KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) |
325f9c64 | 56 | #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) |
358b28f0 | 57 | #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) |
b13216cf | 58 | |
61bbe380 CD |
59 | DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use); |
60 | ||
9033bba4 | 61 | extern unsigned int kvm_sve_max_vl; |
a3be836d | 62 | int kvm_arm_init_sve(void); |
0f062bfe | 63 | |
6951e48b | 64 | int __attribute_const__ kvm_target_cpu(void); |
4f8d6632 | 65 | int kvm_reset_vcpu(struct kvm_vcpu *vcpu); |
9033bba4 | 66 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu); |
375bdd3b | 67 | int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext); |
c612505f | 68 | void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start); |
4f8d6632 | 69 | |
e329fb75 | 70 | struct kvm_vmid { |
4f8d6632 MZ |
71 | /* The VMID generation used for the virt. memory system */ |
72 | u64 vmid_gen; | |
73 | u32 vmid; | |
e329fb75 CD |
74 | }; |
75 | ||
76 | struct kvm_arch { | |
77 | struct kvm_vmid vmid; | |
4f8d6632 | 78 | |
7665f3a8 | 79 | /* stage2 entry level table */ |
4f8d6632 | 80 | pgd_t *pgd; |
e329fb75 | 81 | phys_addr_t pgd_phys; |
4f8d6632 | 82 | |
7665f3a8 SP |
83 | /* VTCR_EL2 value for this VM */ |
84 | u64 vtcr; | |
4f8d6632 | 85 | |
94d0e598 MZ |
86 | /* The last vcpu id that ran on each physical CPU */ |
87 | int __percpu *last_vcpu_ran; | |
88 | ||
3caa2d8c AP |
89 | /* The maximum number of vCPUs depends on the used GIC model */ |
90 | int max_vcpus; | |
91 | ||
4f8d6632 MZ |
92 | /* Interrupt controller */ |
93 | struct vgic_dist vgic; | |
85bd0ba1 MZ |
94 | |
95 | /* Mandated version of PSCI */ | |
96 | u32 psci_version; | |
4f8d6632 MZ |
97 | }; |
98 | ||
99 | #define KVM_NR_MEM_OBJS 40 | |
100 | ||
101 | /* | |
102 | * We don't want allocation failures within the mmu code, so we preallocate | |
103 | * enough memory for a single page fault in a cache. | |
104 | */ | |
105 | struct kvm_mmu_memory_cache { | |
106 | int nobjs; | |
107 | void *objects[KVM_NR_MEM_OBJS]; | |
108 | }; | |
109 | ||
110 | struct kvm_vcpu_fault_info { | |
111 | u32 esr_el2; /* Hyp Syndrom Register */ | |
112 | u64 far_el2; /* Hyp Fault Address Register */ | |
113 | u64 hpfar_el2; /* Hyp IPA Fault Address Register */ | |
0067df41 | 114 | u64 disr_el1; /* Deferred [SError] Status Register */ |
4f8d6632 MZ |
115 | }; |
116 | ||
9d8415d6 MZ |
117 | /* |
118 | * 0 is reserved as an invalid value. | |
119 | * Order should be kept in sync with the save/restore code. | |
120 | */ | |
121 | enum vcpu_sysreg { | |
122 | __INVALID_SYSREG__, | |
123 | MPIDR_EL1, /* MultiProcessor Affinity Register */ | |
124 | CSSELR_EL1, /* Cache Size Selection Register */ | |
125 | SCTLR_EL1, /* System Control Register */ | |
126 | ACTLR_EL1, /* Auxiliary Control Register */ | |
127 | CPACR_EL1, /* Coprocessor Access Control */ | |
73433762 | 128 | ZCR_EL1, /* SVE Control */ |
9d8415d6 MZ |
129 | TTBR0_EL1, /* Translation Table Base Register 0 */ |
130 | TTBR1_EL1, /* Translation Table Base Register 1 */ | |
131 | TCR_EL1, /* Translation Control Register */ | |
132 | ESR_EL1, /* Exception Syndrome Register */ | |
ef769e32 AB |
133 | AFSR0_EL1, /* Auxiliary Fault Status Register 0 */ |
134 | AFSR1_EL1, /* Auxiliary Fault Status Register 1 */ | |
9d8415d6 MZ |
135 | FAR_EL1, /* Fault Address Register */ |
136 | MAIR_EL1, /* Memory Attribute Indirection Register */ | |
137 | VBAR_EL1, /* Vector Base Address Register */ | |
138 | CONTEXTIDR_EL1, /* Context ID Register */ | |
139 | TPIDR_EL0, /* Thread ID, User R/W */ | |
140 | TPIDRRO_EL0, /* Thread ID, User R/O */ | |
141 | TPIDR_EL1, /* Thread ID, Privileged */ | |
142 | AMAIR_EL1, /* Aux Memory Attribute Indirection Register */ | |
143 | CNTKCTL_EL1, /* Timer Control Register (EL1) */ | |
144 | PAR_EL1, /* Physical Address Register */ | |
145 | MDSCR_EL1, /* Monitor Debug System Control Register */ | |
146 | MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ | |
c773ae2b | 147 | DISR_EL1, /* Deferred Interrupt Status Register */ |
9d8415d6 | 148 | |
ab946834 SZ |
149 | /* Performance Monitors Registers */ |
150 | PMCR_EL0, /* Control Register */ | |
3965c3ce | 151 | PMSELR_EL0, /* Event Counter Selection Register */ |
051ff581 SZ |
152 | PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ |
153 | PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, | |
154 | PMCCNTR_EL0, /* Cycle Counter Register */ | |
9feb21ac SZ |
155 | PMEVTYPER0_EL0, /* Event Type Register (0-30) */ |
156 | PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, | |
157 | PMCCFILTR_EL0, /* Cycle Count Filter Register */ | |
96b0eebc | 158 | PMCNTENSET_EL0, /* Count Enable Set Register */ |
9db52c78 | 159 | PMINTENSET_EL1, /* Interrupt Enable Set Register */ |
76d883c4 | 160 | PMOVSSET_EL0, /* Overflow Flag Status Set Register */ |
7a0adc70 | 161 | PMSWINC_EL0, /* Software Increment Register */ |
d692b8ad | 162 | PMUSERENR_EL0, /* User Enable Register */ |
ab946834 | 163 | |
384b40ca MR |
164 | /* Pointer Authentication Registers in a strict increasing order. */ |
165 | APIAKEYLO_EL1, | |
166 | APIAKEYHI_EL1, | |
167 | APIBKEYLO_EL1, | |
168 | APIBKEYHI_EL1, | |
169 | APDAKEYLO_EL1, | |
170 | APDAKEYHI_EL1, | |
171 | APDBKEYLO_EL1, | |
172 | APDBKEYHI_EL1, | |
173 | APGAKEYLO_EL1, | |
174 | APGAKEYHI_EL1, | |
175 | ||
9d8415d6 MZ |
176 | /* 32bit specific registers. Keep them at the end of the range */ |
177 | DACR32_EL2, /* Domain Access Control Register */ | |
178 | IFSR32_EL2, /* Instruction Fault Status Register */ | |
179 | FPEXC32_EL2, /* Floating-Point Exception Control Register */ | |
180 | DBGVCR32_EL2, /* Debug Vector Catch Register */ | |
181 | ||
182 | NR_SYS_REGS /* Nothing after this line! */ | |
183 | }; | |
184 | ||
185 | /* 32bit mapping */ | |
186 | #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ | |
187 | #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */ | |
188 | #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */ | |
189 | #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */ | |
190 | #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */ | |
191 | #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */ | |
192 | #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */ | |
193 | #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */ | |
194 | #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */ | |
195 | #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */ | |
196 | #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */ | |
197 | #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */ | |
198 | #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */ | |
199 | #define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */ | |
200 | #define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */ | |
201 | #define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */ | |
202 | #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */ | |
203 | #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */ | |
204 | #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */ | |
205 | #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */ | |
206 | #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */ | |
207 | #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */ | |
208 | #define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */ | |
209 | #define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */ | |
210 | #define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */ | |
211 | #define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */ | |
212 | #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */ | |
213 | #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */ | |
214 | #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */ | |
215 | ||
216 | #define cp14_DBGDSCRext (MDSCR_EL1 * 2) | |
217 | #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2) | |
218 | #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2) | |
219 | #define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1) | |
220 | #define cp14_DBGWCR0 (DBGWCR0_EL1 * 2) | |
221 | #define cp14_DBGWVR0 (DBGWVR0_EL1 * 2) | |
222 | #define cp14_DBGDCCINT (MDCCINT_EL1 * 2) | |
223 | ||
224 | #define NR_COPRO_REGS (NR_SYS_REGS * 2) | |
225 | ||
4f8d6632 MZ |
226 | struct kvm_cpu_context { |
227 | struct kvm_regs gp_regs; | |
40033a61 MZ |
228 | union { |
229 | u64 sys_regs[NR_SYS_REGS]; | |
72564016 | 230 | u32 copro[NR_COPRO_REGS]; |
40033a61 | 231 | }; |
c97e166e JM |
232 | |
233 | struct kvm_vcpu *__hyp_running_vcpu; | |
4f8d6632 MZ |
234 | }; |
235 | ||
236 | typedef struct kvm_cpu_context kvm_cpu_context_t; | |
237 | ||
358b28f0 MZ |
238 | struct vcpu_reset_state { |
239 | unsigned long pc; | |
240 | unsigned long r0; | |
241 | bool be; | |
242 | bool reset; | |
243 | }; | |
244 | ||
4f8d6632 MZ |
245 | struct kvm_vcpu_arch { |
246 | struct kvm_cpu_context ctxt; | |
b43b5dd9 DM |
247 | void *sve_state; |
248 | unsigned int sve_max_vl; | |
4f8d6632 MZ |
249 | |
250 | /* HYP configuration */ | |
251 | u64 hcr_el2; | |
56c7f5e7 | 252 | u32 mdcr_el2; |
4f8d6632 MZ |
253 | |
254 | /* Exception Information */ | |
255 | struct kvm_vcpu_fault_info fault; | |
256 | ||
55e3748e MZ |
257 | /* State of various workarounds, see kvm_asm.h for bit assignment */ |
258 | u64 workaround_flags; | |
259 | ||
fa89d31c DM |
260 | /* Miscellaneous vcpu state flags */ |
261 | u64 flags; | |
0c557ed4 | 262 | |
84e690bf AB |
263 | /* |
264 | * We maintain more than a single set of debug registers to support | |
265 | * debugging the guest from the host and to maintain separate host and | |
266 | * guest state during world switches. vcpu_debug_state are the debug | |
267 | * registers of the vcpu as the guest sees them. host_debug_state are | |
834bf887 AB |
268 | * the host registers which are saved and restored during |
269 | * world switches. external_debug_state contains the debug | |
270 | * values we want to debug the guest. This is set via the | |
271 | * KVM_SET_GUEST_DEBUG ioctl. | |
84e690bf AB |
272 | * |
273 | * debug_ptr points to the set of debug registers that should be loaded | |
274 | * onto the hardware when running the guest. | |
275 | */ | |
276 | struct kvm_guest_debug_arch *debug_ptr; | |
277 | struct kvm_guest_debug_arch vcpu_debug_state; | |
834bf887 | 278 | struct kvm_guest_debug_arch external_debug_state; |
84e690bf | 279 | |
4f8d6632 MZ |
280 | /* Pointer to host CPU context */ |
281 | kvm_cpu_context_t *host_cpu_context; | |
e6b673b7 DM |
282 | |
283 | struct thread_info *host_thread_info; /* hyp VA */ | |
284 | struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */ | |
285 | ||
f85279b4 WD |
286 | struct { |
287 | /* {Break,watch}point registers */ | |
288 | struct kvm_guest_debug_arch regs; | |
289 | /* Statistical profiling extension */ | |
290 | u64 pmscr_el1; | |
291 | } host_debug_state; | |
4f8d6632 MZ |
292 | |
293 | /* VGIC state */ | |
294 | struct vgic_cpu vgic_cpu; | |
295 | struct arch_timer_cpu timer_cpu; | |
04fe4726 | 296 | struct kvm_pmu pmu; |
4f8d6632 MZ |
297 | |
298 | /* | |
299 | * Anything that is not used directly from assembly code goes | |
300 | * here. | |
301 | */ | |
4f8d6632 | 302 | |
337b99bf AB |
303 | /* |
304 | * Guest registers we preserve during guest debugging. | |
305 | * | |
306 | * These shadow registers are updated by the kvm_handle_sys_reg | |
307 | * trap handler if the guest accesses or updates them while we | |
308 | * are using guest debug. | |
309 | */ | |
310 | struct { | |
311 | u32 mdscr_el1; | |
312 | } guest_debug_preserved; | |
313 | ||
3781528e EA |
314 | /* vcpu power-off state */ |
315 | bool power_off; | |
4f8d6632 | 316 | |
3b92830a EA |
317 | /* Don't run the guest (internal implementation need) */ |
318 | bool pause; | |
319 | ||
4f8d6632 MZ |
320 | /* IO related fields */ |
321 | struct kvm_decode mmio_decode; | |
322 | ||
4f8d6632 MZ |
323 | /* Cache some mmu pages needed inside spinlock regions */ |
324 | struct kvm_mmu_memory_cache mmu_page_cache; | |
325 | ||
326 | /* Target CPU and feature flags */ | |
6c8c0c4d | 327 | int target; |
4f8d6632 MZ |
328 | DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES); |
329 | ||
330 | /* Detect first run of a vcpu */ | |
331 | bool has_run_once; | |
4715c14b JM |
332 | |
333 | /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ | |
334 | u64 vsesr_el2; | |
d47533da | 335 | |
358b28f0 MZ |
336 | /* Additional reset state */ |
337 | struct vcpu_reset_state reset_state; | |
338 | ||
d47533da CD |
339 | /* True when deferrable sysregs are loaded on the physical CPU, |
340 | * see kvm_vcpu_load_sysregs and kvm_vcpu_put_sysregs. */ | |
341 | bool sysregs_loaded_on_cpu; | |
4f8d6632 MZ |
342 | }; |
343 | ||
b43b5dd9 DM |
344 | /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ |
345 | #define vcpu_sve_pffr(vcpu) ((void *)((char *)((vcpu)->arch.sve_state) + \ | |
346 | sve_ffr_offset((vcpu)->arch.sve_max_vl))) | |
347 | ||
e1c9c983 DM |
348 | #define vcpu_sve_state_size(vcpu) ({ \ |
349 | size_t __size_ret; \ | |
350 | unsigned int __vcpu_vq; \ | |
351 | \ | |
352 | if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \ | |
353 | __size_ret = 0; \ | |
354 | } else { \ | |
355 | __vcpu_vq = sve_vq_from_vl((vcpu)->arch.sve_max_vl); \ | |
356 | __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \ | |
357 | } \ | |
358 | \ | |
359 | __size_ret; \ | |
360 | }) | |
361 | ||
fa89d31c DM |
362 | /* vcpu_arch flags field values: */ |
363 | #define KVM_ARM64_DEBUG_DIRTY (1 << 0) | |
e6b673b7 DM |
364 | #define KVM_ARM64_FP_ENABLED (1 << 1) /* guest FP regs loaded */ |
365 | #define KVM_ARM64_FP_HOST (1 << 2) /* host FP regs loaded */ | |
366 | #define KVM_ARM64_HOST_SVE_IN_USE (1 << 3) /* backup for host TIF_SVE */ | |
b3eb56b6 | 367 | #define KVM_ARM64_HOST_SVE_ENABLED (1 << 4) /* SVE enabled for EL0 */ |
1765edba | 368 | #define KVM_ARM64_GUEST_HAS_SVE (1 << 5) /* SVE exposed to guest */ |
9033bba4 | 369 | #define KVM_ARM64_VCPU_SVE_FINALIZED (1 << 6) /* SVE config completed */ |
b890d75c | 370 | #define KVM_ARM64_GUEST_HAS_PTRAUTH (1 << 7) /* PTRAUTH exposed to guest */ |
1765edba DM |
371 | |
372 | #define vcpu_has_sve(vcpu) (system_supports_sve() && \ | |
373 | ((vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_SVE)) | |
fa89d31c | 374 | |
b890d75c ADK |
375 | #define vcpu_has_ptrauth(vcpu) ((system_supports_address_auth() || \ |
376 | system_supports_generic_auth()) && \ | |
377 | ((vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_PTRAUTH)) | |
378 | ||
4f8d6632 | 379 | #define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs) |
8d404c4c CD |
380 | |
381 | /* | |
382 | * Only use __vcpu_sys_reg if you know you want the memory backed version of a | |
383 | * register, and not the one most recently accessed by a running VCPU. For | |
384 | * example, for userspace access or for system registers that are never context | |
385 | * switched, but only emulated. | |
386 | */ | |
387 | #define __vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)]) | |
388 | ||
da6f1666 | 389 | u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg); |
d47533da | 390 | void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg); |
8d404c4c | 391 | |
72564016 MZ |
392 | /* |
393 | * CP14 and CP15 live in the same array, as they are backed by the | |
394 | * same system registers. | |
395 | */ | |
396 | #define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)]) | |
397 | #define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)]) | |
4f8d6632 MZ |
398 | |
399 | struct kvm_vm_stat { | |
8a7e75d4 | 400 | ulong remote_tlb_flush; |
4f8d6632 MZ |
401 | }; |
402 | ||
403 | struct kvm_vcpu_stat { | |
8a7e75d4 SJS |
404 | u64 halt_successful_poll; |
405 | u64 halt_attempted_poll; | |
406 | u64 halt_poll_invalid; | |
407 | u64 halt_wakeup; | |
408 | u64 hvc_exit_stat; | |
b19e6892 AT |
409 | u64 wfe_exit_stat; |
410 | u64 wfi_exit_stat; | |
411 | u64 mmio_exit_user; | |
412 | u64 mmio_exit_kernel; | |
413 | u64 exits; | |
4f8d6632 MZ |
414 | }; |
415 | ||
473bdc0e | 416 | int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init); |
4f8d6632 MZ |
417 | unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); |
418 | int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); | |
4f8d6632 MZ |
419 | int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); |
420 | int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); | |
539aee0e JM |
421 | int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, |
422 | struct kvm_vcpu_events *events); | |
b7b27fac | 423 | |
539aee0e JM |
424 | int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, |
425 | struct kvm_vcpu_events *events); | |
4f8d6632 MZ |
426 | |
427 | #define KVM_ARCH_WANT_MMU_NOTIFIER | |
4f8d6632 MZ |
428 | int kvm_unmap_hva_range(struct kvm *kvm, |
429 | unsigned long start, unsigned long end); | |
748c0e31 | 430 | int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); |
35307b9a MZ |
431 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); |
432 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); | |
4f8d6632 | 433 | |
4f8d6632 | 434 | struct kvm_vcpu *kvm_arm_get_running_vcpu(void); |
4000be42 | 435 | struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void); |
b13216cf CD |
436 | void kvm_arm_halt_guest(struct kvm *kvm); |
437 | void kvm_arm_resume_guest(struct kvm *kvm); | |
4f8d6632 | 438 | |
a0bf9776 | 439 | u64 __kvm_call_hyp(void *hypfn, ...); |
18fc7bf8 MZ |
440 | |
441 | /* | |
442 | * The couple of isb() below are there to guarantee the same behaviour | |
443 | * on VHE as on !VHE, where the eret to EL1 acts as a context | |
444 | * synchronization event. | |
445 | */ | |
446 | #define kvm_call_hyp(f, ...) \ | |
447 | do { \ | |
448 | if (has_vhe()) { \ | |
449 | f(__VA_ARGS__); \ | |
450 | isb(); \ | |
451 | } else { \ | |
452 | __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__); \ | |
453 | } \ | |
454 | } while(0) | |
455 | ||
456 | #define kvm_call_hyp_ret(f, ...) \ | |
457 | ({ \ | |
458 | typeof(f(__VA_ARGS__)) ret; \ | |
459 | \ | |
460 | if (has_vhe()) { \ | |
461 | ret = f(__VA_ARGS__); \ | |
462 | isb(); \ | |
463 | } else { \ | |
464 | ret = __kvm_call_hyp(kvm_ksym_ref(f), \ | |
465 | ##__VA_ARGS__); \ | |
466 | } \ | |
467 | \ | |
468 | ret; \ | |
469 | }) | |
22b39ca3 | 470 | |
cf5d3188 | 471 | void force_vm_exit(const cpumask_t *mask); |
8199ed0e | 472 | void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot); |
4f8d6632 MZ |
473 | |
474 | int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, | |
475 | int exception_index); | |
3368bd80 JM |
476 | void handle_exit_early(struct kvm_vcpu *vcpu, struct kvm_run *run, |
477 | int exception_index); | |
4f8d6632 MZ |
478 | |
479 | int kvm_perf_init(void); | |
480 | int kvm_perf_teardown(void); | |
481 | ||
b7b27fac DG |
482 | void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome); |
483 | ||
4429fc64 AP |
484 | struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); |
485 | ||
4464e210 CD |
486 | DECLARE_PER_CPU(kvm_cpu_context_t, kvm_host_cpu_state); |
487 | ||
32f13955 MZ |
488 | static inline void kvm_init_host_cpu_context(kvm_cpu_context_t *cpu_ctxt, |
489 | int cpu) | |
490 | { | |
491 | /* The host's MPIDR is immutable, so let's set it up at boot time */ | |
492 | cpu_ctxt->sys_regs[MPIDR_EL1] = cpu_logical_map(cpu); | |
493 | } | |
494 | ||
7c36447a WD |
495 | void __kvm_enable_ssbs(void); |
496 | ||
12fda812 | 497 | static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr, |
092bd143 MZ |
498 | unsigned long hyp_stack_ptr, |
499 | unsigned long vector_ptr) | |
500 | { | |
9bc03f1d MZ |
501 | /* |
502 | * Calculate the raw per-cpu offset without a translation from the | |
503 | * kernel's mapping to the linear mapping, and store it in tpidr_el2 | |
504 | * so that we can use adr_l to access per-cpu variables in EL2. | |
505 | */ | |
506 | u64 tpidr_el2 = ((u64)this_cpu_ptr(&kvm_host_cpu_state) - | |
507 | (u64)kvm_ksym_ref(kvm_host_cpu_state)); | |
4464e210 | 508 | |
092bd143 | 509 | /* |
63a1e1c9 MR |
510 | * Call initialization code, and switch to the full blown HYP code. |
511 | * If the cpucaps haven't been finalized yet, something has gone very | |
512 | * wrong, and hyp will crash and burn when it uses any | |
513 | * cpus_have_const_cap() wrapper. | |
092bd143 | 514 | */ |
63a1e1c9 | 515 | BUG_ON(!static_branch_likely(&arm64_const_caps_ready)); |
9bc03f1d | 516 | __kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr, tpidr_el2); |
7c36447a WD |
517 | |
518 | /* | |
519 | * Disabling SSBD on a non-VHE system requires us to enable SSBS | |
520 | * at EL2. | |
521 | */ | |
522 | if (!has_vhe() && this_cpu_has_cap(ARM64_SSBS) && | |
523 | arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) { | |
524 | kvm_call_hyp(__kvm_enable_ssbs); | |
525 | } | |
092bd143 | 526 | } |
67f69197 | 527 | |
33e5f4e5 | 528 | static inline bool kvm_arch_requires_vhe(void) |
85acda3b DM |
529 | { |
530 | /* | |
531 | * The Arm architecture specifies that implementation of SVE | |
532 | * requires VHE also to be implemented. The KVM code for arm64 | |
533 | * relies on this when SVE is present: | |
534 | */ | |
535 | if (system_supports_sve()) | |
85acda3b | 536 | return true; |
33e5f4e5 | 537 | |
8b2cca9a MZ |
538 | /* Some implementations have defects that confine them to VHE */ |
539 | if (cpus_have_cap(ARM64_WORKAROUND_1165522)) | |
540 | return true; | |
541 | ||
33e5f4e5 | 542 | return false; |
85acda3b DM |
543 | } |
544 | ||
384b40ca MR |
545 | void kvm_arm_vcpu_ptrauth_trap(struct kvm_vcpu *vcpu); |
546 | ||
0865e636 RK |
547 | static inline void kvm_arch_hardware_unsetup(void) {} |
548 | static inline void kvm_arch_sync_events(struct kvm *kvm) {} | |
0865e636 | 549 | static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} |
3491caf2 | 550 | static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} |
0865e636 | 551 | |
56c7f5e7 AB |
552 | void kvm_arm_init_debug(void); |
553 | void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); | |
554 | void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); | |
84e690bf | 555 | void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); |
bb0c70bc SZ |
556 | int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, |
557 | struct kvm_device_attr *attr); | |
558 | int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, | |
559 | struct kvm_device_attr *attr); | |
560 | int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, | |
561 | struct kvm_device_attr *attr); | |
56c7f5e7 | 562 | |
0f62f0e9 | 563 | static inline void __cpu_init_stage2(void) {} |
21a4179c | 564 | |
e6b673b7 DM |
565 | /* Guest/host FPSIMD coordination helpers */ |
566 | int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); | |
567 | void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); | |
568 | void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); | |
569 | void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); | |
570 | ||
571 | #ifdef CONFIG_KVM /* Avoid conflicts with core headers if CONFIG_KVM=n */ | |
572 | static inline int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) | |
17eed27b | 573 | { |
e6b673b7 | 574 | return kvm_arch_vcpu_run_map_fp(vcpu); |
17eed27b | 575 | } |
e6b673b7 | 576 | #endif |
17eed27b | 577 | |
4f5abad9 JM |
578 | static inline void kvm_arm_vhe_guest_enter(void) |
579 | { | |
580 | local_daif_mask(); | |
85738e05 JT |
581 | |
582 | /* | |
583 | * Having IRQs masked via PMR when entering the guest means the GIC | |
584 | * will not signal the CPU of interrupts of lower priority, and the | |
585 | * only way to get out will be via guest exceptions. | |
586 | * Naturally, we want to avoid this. | |
587 | */ | |
588 | if (system_uses_irq_prio_masking()) { | |
589 | gic_write_pmr(GIC_PRIO_IRQON); | |
590 | dsb(sy); | |
591 | } | |
4f5abad9 JM |
592 | } |
593 | ||
594 | static inline void kvm_arm_vhe_guest_exit(void) | |
595 | { | |
85738e05 JT |
596 | /* |
597 | * local_daif_restore() takes care to properly restore PSTATE.DAIF | |
598 | * and the GIC PMR if the host is using IRQ priorities. | |
599 | */ | |
4f5abad9 | 600 | local_daif_restore(DAIF_PROCCTX_NOIRQ); |
3f5c90b8 CD |
601 | |
602 | /* | |
603 | * When we exit from the guest we change a number of CPU configuration | |
604 | * parameters, such as traps. Make sure these changes take effect | |
605 | * before running the host or additional guests. | |
606 | */ | |
607 | isb(); | |
4f5abad9 | 608 | } |
6167ec5c MZ |
609 | |
610 | static inline bool kvm_arm_harden_branch_predictor(void) | |
611 | { | |
612 | return cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR); | |
613 | } | |
614 | ||
5d81f7dc MZ |
615 | #define KVM_SSBD_UNKNOWN -1 |
616 | #define KVM_SSBD_FORCE_DISABLE 0 | |
617 | #define KVM_SSBD_KERNEL 1 | |
618 | #define KVM_SSBD_FORCE_ENABLE 2 | |
619 | #define KVM_SSBD_MITIGATED 3 | |
620 | ||
621 | static inline int kvm_arm_have_ssbd(void) | |
622 | { | |
623 | switch (arm64_get_ssbd_state()) { | |
624 | case ARM64_SSBD_FORCE_DISABLE: | |
625 | return KVM_SSBD_FORCE_DISABLE; | |
626 | case ARM64_SSBD_KERNEL: | |
627 | return KVM_SSBD_KERNEL; | |
628 | case ARM64_SSBD_FORCE_ENABLE: | |
629 | return KVM_SSBD_FORCE_ENABLE; | |
630 | case ARM64_SSBD_MITIGATED: | |
631 | return KVM_SSBD_MITIGATED; | |
632 | case ARM64_SSBD_UNKNOWN: | |
633 | default: | |
634 | return KVM_SSBD_UNKNOWN; | |
635 | } | |
636 | } | |
637 | ||
bc192cee CD |
638 | void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu); |
639 | void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu); | |
640 | ||
0f62f0e9 SP |
641 | void kvm_set_ipa_limit(void); |
642 | ||
d1e5b0e9 MO |
643 | #define __KVM_HAVE_ARCH_VM_ALLOC |
644 | struct kvm *kvm_arch_alloc_vm(void); | |
645 | void kvm_arch_free_vm(struct kvm *kvm); | |
646 | ||
bca607eb | 647 | int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type); |
5b6c6742 | 648 | |
92e68b2b | 649 | int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); |
9033bba4 DM |
650 | bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); |
651 | ||
652 | #define kvm_arm_vcpu_sve_finalized(vcpu) \ | |
653 | ((vcpu)->arch.flags & KVM_ARM64_VCPU_SVE_FINALIZED) | |
7dd32a0d | 654 | |
4f8d6632 | 655 | #endif /* __ARM64_KVM_HOST_H__ */ |