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caab277b | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
83a49794 MZ |
2 | /* |
3 | * Copyright (C) 2012,2013 - ARM Ltd | |
4 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
5 | * | |
6 | * Derived from arch/arm/include/kvm_emulate.h | |
7 | * Copyright (C) 2012 - Virtual Open Systems and Columbia University | |
8 | * Author: Christoffer Dall <c.dall@virtualopensystems.com> | |
83a49794 MZ |
9 | */ |
10 | ||
11 | #ifndef __ARM64_KVM_EMULATE_H__ | |
12 | #define __ARM64_KVM_EMULATE_H__ | |
13 | ||
14 | #include <linux/kvm_host.h> | |
c6d01a94 | 15 | |
bd7d95ca | 16 | #include <asm/debug-monitors.h> |
c6d01a94 | 17 | #include <asm/esr.h> |
83a49794 | 18 | #include <asm/kvm_arm.h> |
00536ec4 | 19 | #include <asm/kvm_hyp.h> |
111903d1 | 20 | #include <asm/kvm_nested.h> |
83a49794 | 21 | #include <asm/ptrace.h> |
4429fc64 | 22 | #include <asm/cputype.h> |
68908bf7 | 23 | #include <asm/virt.h> |
83a49794 | 24 | |
bb666c47 MZ |
25 | #define CURRENT_EL_SP_EL0_VECTOR 0x0 |
26 | #define CURRENT_EL_SP_ELx_VECTOR 0x200 | |
27 | #define LOWER_EL_AArch64_VECTOR 0x400 | |
28 | #define LOWER_EL_AArch32_VECTOR 0x600 | |
29 | ||
30 | enum exception_type { | |
31 | except_type_sync = 0, | |
32 | except_type_irq = 0x80, | |
33 | except_type_fiq = 0x100, | |
34 | except_type_serror = 0x180, | |
35 | }; | |
b547631f | 36 | |
47f3a2fc JL |
37 | #define kvm_exception_type_names \ |
38 | { except_type_sync, "SYNC" }, \ | |
39 | { except_type_irq, "IRQ" }, \ | |
40 | { except_type_fiq, "FIQ" }, \ | |
41 | { except_type_serror, "SERROR" } | |
42 | ||
27b190bd | 43 | bool kvm_condition_valid32(const struct kvm_vcpu *vcpu); |
6ddbc281 | 44 | void kvm_skip_instr32(struct kvm_vcpu *vcpu); |
27b190bd | 45 | |
83a49794 | 46 | void kvm_inject_undefined(struct kvm_vcpu *vcpu); |
10cf3390 | 47 | void kvm_inject_vabt(struct kvm_vcpu *vcpu); |
83a49794 MZ |
48 | void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr); |
49 | void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr); | |
85ea6b1e | 50 | void kvm_inject_size_fault(struct kvm_vcpu *vcpu); |
83a49794 | 51 | |
6109c5a6 SC |
52 | void kvm_vcpu_wfi(struct kvm_vcpu *vcpu); |
53 | ||
47f3a2fc JL |
54 | void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu); |
55 | int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2); | |
56 | int kvm_inject_nested_irq(struct kvm_vcpu *vcpu); | |
57 | ||
26bf74bd | 58 | #if defined(__KVM_VHE_HYPERVISOR__) || defined(__KVM_NVHE_HYPERVISOR__) |
5c37f1ae | 59 | static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu) |
e72341c5 CD |
60 | { |
61 | return !(vcpu->arch.hcr_el2 & HCR_RW); | |
62 | } | |
26bf74bd RW |
63 | #else |
64 | static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu) | |
65 | { | |
1de10b7d | 66 | return vcpu_has_feature(vcpu, KVM_ARM_VCPU_EL1_32BIT); |
26bf74bd RW |
67 | } |
68 | #endif | |
e72341c5 | 69 | |
b856a591 CD |
70 | static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) |
71 | { | |
72 | vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS; | |
38cba550 | 73 | if (has_vhe() || has_hvhe()) |
68908bf7 | 74 | vcpu->arch.hcr_el2 |= HCR_E2H; |
d8569fba | 75 | if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) { |
558daf69 DG |
76 | /* route synchronous external abort exceptions to EL2 */ |
77 | vcpu->arch.hcr_el2 |= HCR_TEA; | |
78 | /* trap error record accesses */ | |
79 | vcpu->arch.hcr_el2 |= HCR_TERR; | |
80 | } | |
5c401308 | 81 | |
d8569fba | 82 | if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) { |
e48d53a9 | 83 | vcpu->arch.hcr_el2 |= HCR_FWB; |
5c401308 CD |
84 | } else { |
85 | /* | |
86 | * For non-FWB CPUs, we trap VM ops (HCR_EL2.TVM) until M+C | |
87 | * get set in SCTLR_EL1 such that we can detect when the guest | |
88 | * MMU gets turned on and do the necessary cache maintenance | |
89 | * then. | |
90 | */ | |
91 | vcpu->arch.hcr_el2 |= HCR_TVM; | |
92 | } | |
558daf69 | 93 | |
c876c3f1 MZ |
94 | if (cpus_have_final_cap(ARM64_HAS_EVT) && |
95 | !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE)) | |
96 | vcpu->arch.hcr_el2 |= HCR_TID4; | |
97 | else | |
98 | vcpu->arch.hcr_el2 |= HCR_TID2; | |
99 | ||
26bf74bd | 100 | if (vcpu_el1_is_32bit(vcpu)) |
801f6772 | 101 | vcpu->arch.hcr_el2 &= ~HCR_RW; |
f7f2b15c | 102 | |
ea7fc1bb SP |
103 | if (kvm_has_mte(vcpu->kvm)) |
104 | vcpu->arch.hcr_el2 |= HCR_ATA; | |
b856a591 CD |
105 | } |
106 | ||
3df59d8d | 107 | static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu) |
3c1e7165 | 108 | { |
3df59d8d | 109 | return (unsigned long *)&vcpu->arch.hcr_el2; |
3c1e7165 MZ |
110 | } |
111 | ||
ef2e78dd | 112 | static inline void vcpu_clear_wfx_traps(struct kvm_vcpu *vcpu) |
de737089 MZ |
113 | { |
114 | vcpu->arch.hcr_el2 &= ~HCR_TWE; | |
7bdabad1 MZ |
115 | if (atomic_read(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe.vlpi_count) || |
116 | vcpu->kvm->arch.vgic.nassgireq) | |
ef2e78dd MZ |
117 | vcpu->arch.hcr_el2 &= ~HCR_TWI; |
118 | else | |
119 | vcpu->arch.hcr_el2 |= HCR_TWI; | |
de737089 MZ |
120 | } |
121 | ||
ef2e78dd | 122 | static inline void vcpu_set_wfx_traps(struct kvm_vcpu *vcpu) |
de737089 MZ |
123 | { |
124 | vcpu->arch.hcr_el2 |= HCR_TWE; | |
ef2e78dd | 125 | vcpu->arch.hcr_el2 |= HCR_TWI; |
de737089 MZ |
126 | } |
127 | ||
384b40ca MR |
128 | static inline void vcpu_ptrauth_enable(struct kvm_vcpu *vcpu) |
129 | { | |
130 | vcpu->arch.hcr_el2 |= (HCR_API | HCR_APK); | |
131 | } | |
132 | ||
133 | static inline void vcpu_ptrauth_disable(struct kvm_vcpu *vcpu) | |
134 | { | |
135 | vcpu->arch.hcr_el2 &= ~(HCR_API | HCR_APK); | |
136 | } | |
137 | ||
b7b27fac DG |
138 | static inline unsigned long vcpu_get_vsesr(struct kvm_vcpu *vcpu) |
139 | { | |
140 | return vcpu->arch.vsesr_el2; | |
141 | } | |
142 | ||
4715c14b JM |
143 | static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr) |
144 | { | |
145 | vcpu->arch.vsesr_el2 = vsesr; | |
146 | } | |
147 | ||
5c37f1ae | 148 | static __always_inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu) |
83a49794 | 149 | { |
e47c2055 | 150 | return (unsigned long *)&vcpu_gp_regs(vcpu)->pc; |
83a49794 MZ |
151 | } |
152 | ||
5c37f1ae | 153 | static __always_inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu) |
83a49794 | 154 | { |
e47c2055 | 155 | return (unsigned long *)&vcpu_gp_regs(vcpu)->pstate; |
83a49794 MZ |
156 | } |
157 | ||
5c37f1ae | 158 | static __always_inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu) |
83a49794 | 159 | { |
b547631f | 160 | return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT); |
83a49794 MZ |
161 | } |
162 | ||
5c37f1ae | 163 | static __always_inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu) |
83a49794 | 164 | { |
27b190bd MZ |
165 | if (vcpu_mode_is_32bit(vcpu)) |
166 | return kvm_condition_valid32(vcpu); | |
167 | ||
168 | return true; | |
83a49794 MZ |
169 | } |
170 | ||
83a49794 MZ |
171 | static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu) |
172 | { | |
256c0960 | 173 | *vcpu_cpsr(vcpu) |= PSR_AA32_T_BIT; |
83a49794 MZ |
174 | } |
175 | ||
c0f09634 | 176 | /* |
f6be563a PF |
177 | * vcpu_get_reg and vcpu_set_reg should always be passed a register number |
178 | * coming from a read of ESR_EL2. Otherwise, it may give the wrong result on | |
179 | * AArch32 with banked registers. | |
c0f09634 | 180 | */ |
5c37f1ae | 181 | static __always_inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu, |
bc45a516 PF |
182 | u8 reg_num) |
183 | { | |
e47c2055 | 184 | return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num]; |
bc45a516 PF |
185 | } |
186 | ||
5c37f1ae | 187 | static __always_inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num, |
bc45a516 PF |
188 | unsigned long val) |
189 | { | |
190 | if (reg_num != 31) | |
e47c2055 | 191 | vcpu_gp_regs(vcpu)->regs[reg_num] = val; |
bc45a516 PF |
192 | } |
193 | ||
0043b290 CD |
194 | static inline bool vcpu_is_el2_ctxt(const struct kvm_cpu_context *ctxt) |
195 | { | |
196 | switch (ctxt->regs.pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) { | |
197 | case PSR_MODE_EL2h: | |
198 | case PSR_MODE_EL2t: | |
199 | return true; | |
200 | default: | |
201 | return false; | |
202 | } | |
203 | } | |
204 | ||
205 | static inline bool vcpu_is_el2(const struct kvm_vcpu *vcpu) | |
206 | { | |
207 | return vcpu_is_el2_ctxt(&vcpu->arch.ctxt); | |
208 | } | |
209 | ||
210 | static inline bool __vcpu_el2_e2h_is_set(const struct kvm_cpu_context *ctxt) | |
211 | { | |
94f29ab2 MZ |
212 | return (!cpus_have_final_cap(ARM64_HAS_HCR_NV1) || |
213 | (ctxt_sys_reg(ctxt, HCR_EL2) & HCR_E2H)); | |
0043b290 CD |
214 | } |
215 | ||
216 | static inline bool vcpu_el2_e2h_is_set(const struct kvm_vcpu *vcpu) | |
217 | { | |
218 | return __vcpu_el2_e2h_is_set(&vcpu->arch.ctxt); | |
219 | } | |
220 | ||
221 | static inline bool __vcpu_el2_tge_is_set(const struct kvm_cpu_context *ctxt) | |
222 | { | |
223 | return ctxt_sys_reg(ctxt, HCR_EL2) & HCR_TGE; | |
224 | } | |
225 | ||
226 | static inline bool vcpu_el2_tge_is_set(const struct kvm_vcpu *vcpu) | |
227 | { | |
228 | return __vcpu_el2_tge_is_set(&vcpu->arch.ctxt); | |
229 | } | |
230 | ||
231 | static inline bool __is_hyp_ctxt(const struct kvm_cpu_context *ctxt) | |
232 | { | |
233 | /* | |
234 | * We are in a hypervisor context if the vcpu mode is EL2 or | |
235 | * E2H and TGE bits are set. The latter means we are in the user space | |
236 | * of the VHE kernel. ARMv8.1 ARM describes this as 'InHost' | |
237 | * | |
238 | * Note that the HCR_EL2.{E2H,TGE}={0,1} isn't really handled in the | |
239 | * rest of the KVM code, and will result in a misbehaving guest. | |
240 | */ | |
241 | return vcpu_is_el2_ctxt(ctxt) || | |
242 | (__vcpu_el2_e2h_is_set(ctxt) && __vcpu_el2_tge_is_set(ctxt)) || | |
243 | __vcpu_el2_tge_is_set(ctxt); | |
244 | } | |
245 | ||
246 | static inline bool is_hyp_ctxt(const struct kvm_vcpu *vcpu) | |
247 | { | |
111903d1 | 248 | return vcpu_has_nv(vcpu) && __is_hyp_ctxt(&vcpu->arch.ctxt); |
0043b290 CD |
249 | } |
250 | ||
1cfbb484 MR |
251 | /* |
252 | * The layout of SPSR for an AArch32 state is different when observed from an | |
253 | * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32 | |
254 | * view given an AArch64 view. | |
255 | * | |
256 | * In ARM DDI 0487E.a see: | |
257 | * | |
258 | * - The AArch64 view (SPSR_EL2) in section C5.2.18, page C5-426 | |
259 | * - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256 | |
260 | * - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280 | |
261 | * | |
262 | * Which show the following differences: | |
263 | * | |
264 | * | Bit | AA64 | AA32 | Notes | | |
265 | * +-----+------+------+-----------------------------| | |
266 | * | 24 | DIT | J | J is RES0 in ARMv8 | | |
267 | * | 21 | SS | DIT | SS doesn't exist in AArch32 | | |
268 | * | |
269 | * ... and all other bits are (currently) common. | |
270 | */ | |
271 | static inline unsigned long host_spsr_to_spsr32(unsigned long spsr) | |
272 | { | |
273 | const unsigned long overlap = BIT(24) | BIT(21); | |
274 | unsigned long dit = !!(spsr & PSR_AA32_DIT_BIT); | |
275 | ||
276 | spsr &= ~overlap; | |
277 | ||
278 | spsr |= dit << 21; | |
279 | ||
280 | return spsr; | |
281 | } | |
282 | ||
83a49794 MZ |
283 | static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu) |
284 | { | |
9586a2ea | 285 | u32 mode; |
83a49794 | 286 | |
9586a2ea | 287 | if (vcpu_mode_is_32bit(vcpu)) { |
256c0960 MR |
288 | mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK; |
289 | return mode > PSR_AA32_MODE_USR; | |
9586a2ea SZ |
290 | } |
291 | ||
292 | mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK; | |
b547631f | 293 | |
83a49794 MZ |
294 | return mode != PSR_MODE_EL0t; |
295 | } | |
296 | ||
0b12620f | 297 | static __always_inline u64 kvm_vcpu_get_esr(const struct kvm_vcpu *vcpu) |
83a49794 MZ |
298 | { |
299 | return vcpu->arch.fault.esr_el2; | |
300 | } | |
301 | ||
5c37f1ae | 302 | static __always_inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu) |
3e51d435 | 303 | { |
0b12620f | 304 | u64 esr = kvm_vcpu_get_esr(vcpu); |
3e51d435 MZ |
305 | |
306 | if (esr & ESR_ELx_CV) | |
307 | return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT; | |
308 | ||
309 | return -1; | |
310 | } | |
311 | ||
5c37f1ae | 312 | static __always_inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu) |
83a49794 MZ |
313 | { |
314 | return vcpu->arch.fault.far_el2; | |
315 | } | |
316 | ||
5c37f1ae | 317 | static __always_inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu) |
83a49794 MZ |
318 | { |
319 | return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8; | |
320 | } | |
321 | ||
0067df41 JM |
322 | static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu) |
323 | { | |
324 | return vcpu->arch.fault.disr_el1; | |
325 | } | |
326 | ||
0d97f884 WH |
327 | static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu) |
328 | { | |
3a949f4c | 329 | return kvm_vcpu_get_esr(vcpu) & ESR_ELx_xVC_IMM_MASK; |
0d97f884 WH |
330 | } |
331 | ||
5c37f1ae | 332 | static __always_inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu) |
83a49794 | 333 | { |
3a949f4c | 334 | return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_ISV); |
83a49794 MZ |
335 | } |
336 | ||
c726200d CD |
337 | static inline unsigned long kvm_vcpu_dabt_iss_nisv_sanitized(const struct kvm_vcpu *vcpu) |
338 | { | |
3a949f4c | 339 | return kvm_vcpu_get_esr(vcpu) & (ESR_ELx_CM | ESR_ELx_WNR | ESR_ELx_FSC); |
c726200d CD |
340 | } |
341 | ||
83a49794 MZ |
342 | static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu) |
343 | { | |
3a949f4c | 344 | return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SSE); |
83a49794 MZ |
345 | } |
346 | ||
b6ae256a CD |
347 | static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu) |
348 | { | |
3a949f4c | 349 | return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SF); |
b6ae256a CD |
350 | } |
351 | ||
5c37f1ae | 352 | static __always_inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu) |
83a49794 | 353 | { |
3a949f4c | 354 | return (kvm_vcpu_get_esr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT; |
83a49794 MZ |
355 | } |
356 | ||
c4ad98e4 | 357 | static __always_inline bool kvm_vcpu_abt_iss1tw(const struct kvm_vcpu *vcpu) |
83a49794 | 358 | { |
3a949f4c | 359 | return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_S1PTW); |
83a49794 MZ |
360 | } |
361 | ||
620cf45f | 362 | /* Always check for S1PTW *before* using this. */ |
5c37f1ae | 363 | static __always_inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu) |
60e21a0e | 364 | { |
620cf45f | 365 | return kvm_vcpu_get_esr(vcpu) & ESR_ELx_WNR; |
60e21a0e WD |
366 | } |
367 | ||
57c841f1 MZ |
368 | static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu) |
369 | { | |
3a949f4c | 370 | return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_CM); |
57c841f1 MZ |
371 | } |
372 | ||
5c37f1ae | 373 | static __always_inline unsigned int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu) |
83a49794 | 374 | { |
3a949f4c | 375 | return 1 << ((kvm_vcpu_get_esr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT); |
83a49794 MZ |
376 | } |
377 | ||
378 | /* This one is not specific to Data Abort */ | |
5c37f1ae | 379 | static __always_inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu) |
83a49794 | 380 | { |
3a949f4c | 381 | return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_IL); |
83a49794 MZ |
382 | } |
383 | ||
5c37f1ae | 384 | static __always_inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu) |
83a49794 | 385 | { |
3a949f4c | 386 | return ESR_ELx_EC(kvm_vcpu_get_esr(vcpu)); |
83a49794 MZ |
387 | } |
388 | ||
389 | static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu) | |
390 | { | |
c6d01a94 | 391 | return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW; |
83a49794 MZ |
392 | } |
393 | ||
c4ad98e4 MZ |
394 | static inline bool kvm_vcpu_trap_is_exec_fault(const struct kvm_vcpu *vcpu) |
395 | { | |
396 | return kvm_vcpu_trap_is_iabt(vcpu) && !kvm_vcpu_abt_iss1tw(vcpu); | |
397 | } | |
398 | ||
5c37f1ae | 399 | static __always_inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu) |
0496daa5 | 400 | { |
3a949f4c | 401 | return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC; |
0496daa5 CD |
402 | } |
403 | ||
11e5ea52 AB |
404 | static inline |
405 | bool kvm_vcpu_trap_is_permission_fault(const struct kvm_vcpu *vcpu) | |
83a49794 | 406 | { |
11e5ea52 | 407 | return esr_fsc_is_permission_fault(kvm_vcpu_get_esr(vcpu)); |
83a49794 MZ |
408 | } |
409 | ||
11e5ea52 AB |
410 | static inline |
411 | bool kvm_vcpu_trap_is_translation_fault(const struct kvm_vcpu *vcpu) | |
7d894834 | 412 | { |
11e5ea52 AB |
413 | return esr_fsc_is_translation_fault(kvm_vcpu_get_esr(vcpu)); |
414 | } | |
415 | ||
416 | static inline | |
417 | u64 kvm_vcpu_trap_get_perm_fault_granule(const struct kvm_vcpu *vcpu) | |
418 | { | |
419 | unsigned long esr = kvm_vcpu_get_esr(vcpu); | |
420 | ||
421 | BUG_ON(!esr_fsc_is_permission_fault(esr)); | |
422 | return BIT(ARM64_HW_PGTABLE_LEVEL_SHIFT(esr & ESR_ELx_FSC_LEVEL)); | |
7d894834 YW |
423 | } |
424 | ||
c9a636f2 | 425 | static __always_inline bool kvm_vcpu_abt_issea(const struct kvm_vcpu *vcpu) |
bb428921 | 426 | { |
a2b83133 | 427 | switch (kvm_vcpu_trap_get_fault(vcpu)) { |
b0803ba7 MZ |
428 | case ESR_ELx_FSC_EXTABT: |
429 | case ESR_ELx_FSC_SEA_TTW0: | |
430 | case ESR_ELx_FSC_SEA_TTW1: | |
431 | case ESR_ELx_FSC_SEA_TTW2: | |
432 | case ESR_ELx_FSC_SEA_TTW3: | |
433 | case ESR_ELx_FSC_SECC: | |
434 | case ESR_ELx_FSC_SECC_TTW0: | |
435 | case ESR_ELx_FSC_SECC_TTW1: | |
436 | case ESR_ELx_FSC_SECC_TTW2: | |
437 | case ESR_ELx_FSC_SECC_TTW3: | |
bb428921 JM |
438 | return true; |
439 | default: | |
440 | return false; | |
441 | } | |
442 | } | |
443 | ||
5c37f1ae | 444 | static __always_inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu) |
c667186f | 445 | { |
0b12620f | 446 | u64 esr = kvm_vcpu_get_esr(vcpu); |
1c839141 | 447 | return ESR_ELx_SYS64_ISS_RT(esr); |
c667186f MZ |
448 | } |
449 | ||
64cf98fa CD |
450 | static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu) |
451 | { | |
406504c7 MZ |
452 | if (kvm_vcpu_abt_iss1tw(vcpu)) { |
453 | /* | |
454 | * Only a permission fault on a S1PTW should be | |
455 | * considered as a write. Otherwise, page tables baked | |
456 | * in a read-only memslot will result in an exception | |
457 | * being delivered in the guest. | |
458 | * | |
459 | * The drawback is that we end-up faulting twice if the | |
460 | * guest is using any of HW AF/DB: a translation fault | |
461 | * to map the page containing the PT (read only at | |
462 | * first), then a permission fault to allow the flags | |
463 | * to be set. | |
464 | */ | |
11e5ea52 | 465 | return kvm_vcpu_trap_is_permission_fault(vcpu); |
406504c7 | 466 | } |
c4ad98e4 | 467 | |
64cf98fa CD |
468 | if (kvm_vcpu_trap_is_iabt(vcpu)) |
469 | return false; | |
470 | ||
471 | return kvm_vcpu_dabt_iswrite(vcpu); | |
472 | } | |
473 | ||
4429fc64 | 474 | static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu) |
79c64880 | 475 | { |
0a2acd38 | 476 | return __vcpu_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK; |
79c64880 MZ |
477 | } |
478 | ||
ce94fe93 MZ |
479 | static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu) |
480 | { | |
8d404c4c | 481 | if (vcpu_mode_is_32bit(vcpu)) { |
256c0960 | 482 | *vcpu_cpsr(vcpu) |= PSR_AA32_E_BIT; |
8d404c4c CD |
483 | } else { |
484 | u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1); | |
500ca524 | 485 | sctlr |= SCTLR_ELx_EE; |
1975fa56 | 486 | vcpu_write_sys_reg(vcpu, sctlr, SCTLR_EL1); |
8d404c4c | 487 | } |
ce94fe93 MZ |
488 | } |
489 | ||
6d89d2d9 MZ |
490 | static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu) |
491 | { | |
492 | if (vcpu_mode_is_32bit(vcpu)) | |
256c0960 | 493 | return !!(*vcpu_cpsr(vcpu) & PSR_AA32_E_BIT); |
6d89d2d9 | 494 | |
69adec18 MZ |
495 | if (vcpu_mode_priv(vcpu)) |
496 | return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_ELx_EE); | |
497 | else | |
498 | return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_EL1_E0E); | |
6d89d2d9 MZ |
499 | } |
500 | ||
501 | static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu, | |
502 | unsigned long data, | |
503 | unsigned int len) | |
504 | { | |
505 | if (kvm_vcpu_is_be(vcpu)) { | |
506 | switch (len) { | |
507 | case 1: | |
508 | return data & 0xff; | |
509 | case 2: | |
510 | return be16_to_cpu(data & 0xffff); | |
511 | case 4: | |
512 | return be32_to_cpu(data & 0xffffffff); | |
513 | default: | |
514 | return be64_to_cpu(data); | |
515 | } | |
b3007086 VK |
516 | } else { |
517 | switch (len) { | |
518 | case 1: | |
519 | return data & 0xff; | |
520 | case 2: | |
521 | return le16_to_cpu(data & 0xffff); | |
522 | case 4: | |
523 | return le32_to_cpu(data & 0xffffffff); | |
524 | default: | |
525 | return le64_to_cpu(data); | |
526 | } | |
6d89d2d9 MZ |
527 | } |
528 | ||
529 | return data; /* Leave LE untouched */ | |
530 | } | |
531 | ||
532 | static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu, | |
533 | unsigned long data, | |
534 | unsigned int len) | |
535 | { | |
536 | if (kvm_vcpu_is_be(vcpu)) { | |
537 | switch (len) { | |
538 | case 1: | |
539 | return data & 0xff; | |
540 | case 2: | |
541 | return cpu_to_be16(data & 0xffff); | |
542 | case 4: | |
543 | return cpu_to_be32(data & 0xffffffff); | |
544 | default: | |
545 | return cpu_to_be64(data); | |
546 | } | |
b3007086 VK |
547 | } else { |
548 | switch (len) { | |
549 | case 1: | |
550 | return data & 0xff; | |
551 | case 2: | |
552 | return cpu_to_le16(data & 0xffff); | |
553 | case 4: | |
554 | return cpu_to_le32(data & 0xffffffff); | |
555 | default: | |
556 | return cpu_to_le64(data); | |
557 | } | |
6d89d2d9 MZ |
558 | } |
559 | ||
560 | return data; /* Leave LE untouched */ | |
561 | } | |
562 | ||
cdb5e02e | 563 | static __always_inline void kvm_incr_pc(struct kvm_vcpu *vcpu) |
bd7d95ca | 564 | { |
e19f2c6c | 565 | WARN_ON(vcpu_get_flag(vcpu, PENDING_EXCEPTION)); |
699bb2e0 | 566 | vcpu_set_flag(vcpu, INCREMENT_PC); |
bd7d95ca MR |
567 | } |
568 | ||
699bb2e0 MZ |
569 | #define kvm_pend_exception(v, e) \ |
570 | do { \ | |
e19f2c6c | 571 | WARN_ON(vcpu_get_flag((v), INCREMENT_PC)); \ |
699bb2e0 MZ |
572 | vcpu_set_flag((v), PENDING_EXCEPTION); \ |
573 | vcpu_set_flag((v), e); \ | |
574 | } while (0) | |
575 | ||
90ae31c6 FT |
576 | static __always_inline void kvm_write_cptr_el2(u64 val) |
577 | { | |
578 | if (has_vhe() || has_hvhe()) | |
579 | write_sysreg(val, cpacr_el1); | |
580 | else | |
581 | write_sysreg(val, cptr_el2); | |
582 | } | |
583 | ||
75c76ab5 MZ |
584 | static __always_inline u64 kvm_get_reset_cptr_el2(struct kvm_vcpu *vcpu) |
585 | { | |
586 | u64 val; | |
587 | ||
588 | if (has_vhe()) { | |
589 | val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN | | |
590 | CPACR_EL1_ZEN_EL1EN); | |
375110ab FT |
591 | if (cpus_have_final_cap(ARM64_SME)) |
592 | val |= CPACR_EL1_SMEN_EL1EN; | |
75c76ab5 MZ |
593 | } else if (has_hvhe()) { |
594 | val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN); | |
7af0d5e5 FT |
595 | |
596 | if (!vcpu_has_sve(vcpu) || | |
597 | (vcpu->arch.fp_state != FP_STATE_GUEST_OWNED)) | |
598 | val |= CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN; | |
375110ab FT |
599 | if (cpus_have_final_cap(ARM64_SME)) |
600 | val |= CPACR_EL1_SMEN_EL1EN | CPACR_EL1_SMEN_EL0EN; | |
75c76ab5 MZ |
601 | } else { |
602 | val = CPTR_NVHE_EL2_RES1; | |
603 | ||
604 | if (vcpu_has_sve(vcpu) && | |
605 | (vcpu->arch.fp_state == FP_STATE_GUEST_OWNED)) | |
606 | val |= CPTR_EL2_TZ; | |
607 | if (cpus_have_final_cap(ARM64_SME)) | |
608 | val &= ~CPTR_EL2_TSM; | |
609 | } | |
610 | ||
611 | return val; | |
612 | } | |
613 | ||
614 | static __always_inline void kvm_reset_cptr_el2(struct kvm_vcpu *vcpu) | |
615 | { | |
616 | u64 val = kvm_get_reset_cptr_el2(vcpu); | |
617 | ||
90ae31c6 | 618 | kvm_write_cptr_el2(val); |
75c76ab5 | 619 | } |
83a49794 | 620 | #endif /* __ARM64_KVM_EMULATE_H__ */ |