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KVM: arm/arm64: Add kvm_vcpu_load_sysregs and kvm_vcpu_put_sysregs
[linux-2.6-block.git] / arch / arm64 / include / asm / kvm_emulate.h
CommitLineData
83a49794
MZ		 1/*
2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * Derived from arch/arm/include/kvm_emulate.h
6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
7 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#ifndef __ARM64_KVM_EMULATE_H__
23#define __ARM64_KVM_EMULATE_H__
24
25#include <linux/kvm_host.h>
c6d01a94
MR		 26
27#include <asm/esr.h>
83a49794
MZ		 28#include <asm/kvm_arm.h>
29#include <asm/kvm_mmio.h>
30#include <asm/ptrace.h>
4429fc64 31#include <asm/cputype.h>
68908bf7 32#include <asm/virt.h>
83a49794 33
b547631f
MZ		 34unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num);
35unsigned long *vcpu_spsr32(const struct kvm_vcpu *vcpu);
36
27b190bd
MZ		 37bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
38void kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr);
39
83a49794 40void kvm_inject_undefined(struct kvm_vcpu *vcpu);
10cf3390 41void kvm_inject_vabt(struct kvm_vcpu *vcpu);
83a49794
MZ		 42void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
43void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
74a64a98
MZ		 44void kvm_inject_undef32(struct kvm_vcpu *vcpu);
45void kvm_inject_dabt32(struct kvm_vcpu *vcpu, unsigned long addr);
46void kvm_inject_pabt32(struct kvm_vcpu *vcpu, unsigned long addr);
83a49794 47
b856a591
CD		 48static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
49{
50 vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS;
68908bf7
MZ		 51 if (is_kernel_in_hyp_mode())
52 vcpu->arch.hcr_el2 |= HCR_E2H;
558daf69
DG		 53 if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN)) {
54 /* route synchronous external abort exceptions to EL2 */
55 vcpu->arch.hcr_el2 |= HCR_TEA;
56 /* trap error record accesses */
57 vcpu->arch.hcr_el2 |= HCR_TERR;
58 }
59
801f6772
MZ		 60 if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features))
61 vcpu->arch.hcr_el2 &= ~HCR_RW;
005781be
DM		 62
63 /*
64 * TID3: trap feature register accesses that we virtualise.
65 * For now this is conditional, since no AArch32 feature regs
66 * are currently virtualised.
67 */
68 if (vcpu->arch.hcr_el2 & HCR_RW)
69 vcpu->arch.hcr_el2 |= HCR_TID3;
b856a591
CD		 70}
71
3df59d8d 72static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu)
3c1e7165 73{
3df59d8d 74 return (unsigned long *)&vcpu->arch.hcr_el2;
3c1e7165
MZ		 75}
76
4715c14b
JM		 77static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr)
78{
79 vcpu->arch.vsesr_el2 = vsesr;
80}
81
83a49794
MZ		 82static inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu)
83{
84 return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pc;
85}
86
87static inline unsigned long *vcpu_elr_el1(const struct kvm_vcpu *vcpu)
88{
89 return (unsigned long *)&vcpu_gp_regs(vcpu)->elr_el1;
90}
91
92static inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu)
93{
94 return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pstate;
95}
96
97static inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
98{
b547631f 99 return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT);
83a49794
MZ		 100}
101
102static inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
103{
27b190bd
MZ		 104 if (vcpu_mode_is_32bit(vcpu))
105 return kvm_condition_valid32(vcpu);
106
107 return true;
83a49794
MZ		 108}
109
110static inline void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr)
111{
27b190bd
MZ		 112 if (vcpu_mode_is_32bit(vcpu))
113 kvm_skip_instr32(vcpu, is_wide_instr);
114 else
115 *vcpu_pc(vcpu) += 4;
83a49794
MZ		 116}
117
118static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
119{
b547631f 120 *vcpu_cpsr(vcpu) |= COMPAT_PSR_T_BIT;
83a49794
MZ		 121}
122
c0f09634 123/*
f6be563a
PF		 124 * vcpu_get_reg and vcpu_set_reg should always be passed a register number
125 * coming from a read of ESR_EL2. Otherwise, it may give the wrong result on
126 * AArch32 with banked registers.
c0f09634 127 */
bc45a516
PF		 128static inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu,
129 u8 reg_num)
130{
131 return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs.regs[reg_num];
132}
133
134static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
135 unsigned long val)
136{
137 if (reg_num != 31)
138 vcpu_gp_regs(vcpu)->regs.regs[reg_num] = val;
139}
140
83a49794
MZ		 141/* Get vcpu SPSR for current mode */
142static inline unsigned long *vcpu_spsr(const struct kvm_vcpu *vcpu)
143{
b547631f
MZ		 144 if (vcpu_mode_is_32bit(vcpu))
145 return vcpu_spsr32(vcpu);
146
83a49794
MZ		 147 return (unsigned long *)&vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1];
148}
149
150static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu)
151{
9586a2ea 152 u32 mode;
83a49794 153
9586a2ea
SZ		 154 if (vcpu_mode_is_32bit(vcpu)) {
155 mode = *vcpu_cpsr(vcpu) & COMPAT_PSR_MODE_MASK;
b547631f 156 return mode > COMPAT_PSR_MODE_USR;
9586a2ea
SZ		 157 }
158
159 mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK;
b547631f 160
83a49794
MZ		 161 return mode != PSR_MODE_EL0t;
162}
163
164static inline u32 kvm_vcpu_get_hsr(const struct kvm_vcpu *vcpu)
165{
166 return vcpu->arch.fault.esr_el2;
167}
168
3e51d435
MZ		 169static inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu)
170{
171 u32 esr = kvm_vcpu_get_hsr(vcpu);
172
173 if (esr & ESR_ELx_CV)
174 return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
175
176 return -1;
177}
178
83a49794
MZ		 179static inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu)
180{
181 return vcpu->arch.fault.far_el2;
182}
183
184static inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu)
185{
186 return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8;
187}
188
0067df41
JM		 189static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu)
190{
191 return vcpu->arch.fault.disr_el1;
192}
193
0d97f884
WH		 194static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu)
195{
1c6007d5 196 return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_xVC_IMM_MASK;
0d97f884
WH		 197}
198
83a49794
MZ		 199static inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)
200{
c6d01a94 201 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_ISV);
83a49794
MZ		 202}
203
83a49794
MZ		 204static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)
205{
c6d01a94 206 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SSE);
83a49794
MZ		 207}
208
209static inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)
210{
c6d01a94 211 return (kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;
83a49794
MZ		 212}
213
83a49794
MZ		 214static inline bool kvm_vcpu_dabt_iss1tw(const struct kvm_vcpu *vcpu)
215{
c6d01a94 216 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_S1PTW);
83a49794
MZ		 217}
218
60e21a0e
WD		 219static inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)
220{
221 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_WNR) ||
222 kvm_vcpu_dabt_iss1tw(vcpu); /* AF/DBM update */
223}
224
57c841f1
MZ		 225static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu)
226{
227 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_CM);
228}
229
83a49794
MZ		 230static inline int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)
231{
c6d01a94 232 return 1 << ((kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);
83a49794
MZ		 233}
234
235/* This one is not specific to Data Abort */
236static inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)
237{
c6d01a94 238 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_IL);
83a49794
MZ		 239}
240
241static inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)
242{
561454e2 243 return ESR_ELx_EC(kvm_vcpu_get_hsr(vcpu));
83a49794
MZ		 244}
245
246static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)
247{
c6d01a94 248 return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW;
83a49794
MZ		 249}
250
251static inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)
0496daa5 252{
c6d01a94 253 return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC;
0496daa5
CD		 254}
255
256static inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)
83a49794 257{
c6d01a94 258 return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC_TYPE;
83a49794
MZ		 259}
260
bb428921
JM		 261static inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu)
262{
a2b83133 263 switch (kvm_vcpu_trap_get_fault(vcpu)) {
bb428921
JM		 264 case FSC_SEA:
265 case FSC_SEA_TTW0:
266 case FSC_SEA_TTW1:
267 case FSC_SEA_TTW2:
268 case FSC_SEA_TTW3:
269 case FSC_SECC:
270 case FSC_SECC_TTW0:
271 case FSC_SECC_TTW1:
272 case FSC_SECC_TTW2:
273 case FSC_SECC_TTW3:
274 return true;
275 default:
276 return false;
277 }
278}
279
c667186f
MZ		 280static inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)
281{
282 u32 esr = kvm_vcpu_get_hsr(vcpu);
283 return (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
284}
285
4429fc64 286static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
79c64880 287{
4429fc64 288 return vcpu_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;
79c64880
MZ		 289}
290
ce94fe93
MZ		 291static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
292{
293 if (vcpu_mode_is_32bit(vcpu))
294 *vcpu_cpsr(vcpu) |= COMPAT_PSR_E_BIT;
295 else
296 vcpu_sys_reg(vcpu, SCTLR_EL1) |= (1 << 25);
297}
298
6d89d2d9
MZ		 299static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu)
300{
301 if (vcpu_mode_is_32bit(vcpu))
302 return !!(*vcpu_cpsr(vcpu) & COMPAT_PSR_E_BIT);
303
304 return !!(vcpu_sys_reg(vcpu, SCTLR_EL1) & (1 << 25));
305}
306
307static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu,
308 unsigned long data,
309 unsigned int len)
310{
311 if (kvm_vcpu_is_be(vcpu)) {
312 switch (len) {
313 case 1:
314 return data & 0xff;
315 case 2:
316 return be16_to_cpu(data & 0xffff);
317 case 4:
318 return be32_to_cpu(data & 0xffffffff);
319 default:
320 return be64_to_cpu(data);
321 }
b3007086
VK		 322 } else {
323 switch (len) {
324 case 1:
325 return data & 0xff;
326 case 2:
327 return le16_to_cpu(data & 0xffff);
328 case 4:
329 return le32_to_cpu(data & 0xffffffff);
330 default:
331 return le64_to_cpu(data);
332 }
6d89d2d9
MZ		 333 }
334
335 return data; /* Leave LE untouched */
336}
337
338static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu,
339 unsigned long data,
340 unsigned int len)
341{
342 if (kvm_vcpu_is_be(vcpu)) {
343 switch (len) {
344 case 1:
345 return data & 0xff;
346 case 2:
347 return cpu_to_be16(data & 0xffff);
348 case 4:
349 return cpu_to_be32(data & 0xffffffff);
350 default:
351 return cpu_to_be64(data);
352 }
b3007086
VK		 353 } else {
354 switch (len) {
355 case 1:
356 return data & 0xff;
357 case 2:
358 return cpu_to_le16(data & 0xffff);
359 case 4:
360 return cpu_to_le32(data & 0xffffffff);
361 default:
362 return cpu_to_le64(data);
363 }
6d89d2d9
MZ		 364 }
365
366 return data; /* Leave LE untouched */
367}
368
83a49794 369#endif /* __ARM64_KVM_EMULATE_H__ */
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