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KVM: arm64: debug: Drop useless vpcu parameter
[linux-2.6-block.git] / arch / arm64 / include / asm / kvm_emulate.h
CommitLineData
caab277b 1/* SPDX-License-Identifier: GPL-2.0-only */
83a49794
MZ		 2/*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/include/kvm_emulate.h
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
83a49794
MZ		 9 */
10
11#ifndef __ARM64_KVM_EMULATE_H__
12#define __ARM64_KVM_EMULATE_H__
13
14#include <linux/kvm_host.h>
c6d01a94 15
bd7d95ca 16#include <asm/debug-monitors.h>
c6d01a94 17#include <asm/esr.h>
83a49794 18#include <asm/kvm_arm.h>
00536ec4 19#include <asm/kvm_hyp.h>
83a49794 20#include <asm/ptrace.h>
4429fc64 21#include <asm/cputype.h>
68908bf7 22#include <asm/virt.h>
83a49794 23
b547631f 24unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num);
a8928195
CD		 25unsigned long vcpu_read_spsr32(const struct kvm_vcpu *vcpu);
26void vcpu_write_spsr32(struct kvm_vcpu *vcpu, unsigned long v);
b547631f 27
27b190bd
MZ		 28bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
29void kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr);
30
83a49794 31void kvm_inject_undefined(struct kvm_vcpu *vcpu);
10cf3390 32void kvm_inject_vabt(struct kvm_vcpu *vcpu);
83a49794
MZ		 33void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
34void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
74a64a98
MZ		 35void kvm_inject_undef32(struct kvm_vcpu *vcpu);
36void kvm_inject_dabt32(struct kvm_vcpu *vcpu, unsigned long addr);
37void kvm_inject_pabt32(struct kvm_vcpu *vcpu, unsigned long addr);
83a49794 38
5c37f1ae 39static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
e72341c5
CD		 40{
41 return !(vcpu->arch.hcr_el2 & HCR_RW);
42}
43
b856a591
CD		 44static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
45{
46 vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS;
68908bf7
MZ		 47 if (is_kernel_in_hyp_mode())
48 vcpu->arch.hcr_el2 |= HCR_E2H;
558daf69
DG		 49 if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN)) {
50 /* route synchronous external abort exceptions to EL2 */
51 vcpu->arch.hcr_el2 |= HCR_TEA;
52 /* trap error record accesses */
53 vcpu->arch.hcr_el2 |= HCR_TERR;
54 }
5c401308
CD		 55
56 if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) {
e48d53a9 57 vcpu->arch.hcr_el2 |= HCR_FWB;
5c401308
CD		 58 } else {
59 /*
60 * For non-FWB CPUs, we trap VM ops (HCR_EL2.TVM) until M+C
61 * get set in SCTLR_EL1 such that we can detect when the guest
62 * MMU gets turned on and do the necessary cache maintenance
63 * then.
64 */
65 vcpu->arch.hcr_el2 |= HCR_TVM;
66 }
558daf69 67
801f6772
MZ		 68 if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features))
69 vcpu->arch.hcr_el2 &= ~HCR_RW;
005781be
DM		 70
71 /*
72 * TID3: trap feature register accesses that we virtualise.
73 * For now this is conditional, since no AArch32 feature regs
74 * are currently virtualised.
75 */
e72341c5 76 if (!vcpu_el1_is_32bit(vcpu))
005781be 77 vcpu->arch.hcr_el2 |= HCR_TID3;
f7f2b15c 78
793acf87
AB		 79 if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE) ||
80 vcpu_el1_is_32bit(vcpu))
f7f2b15c 81 vcpu->arch.hcr_el2 |= HCR_TID2;
b856a591
CD		 82}
83
3df59d8d 84static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu)
3c1e7165 85{
3df59d8d 86 return (unsigned long *)&vcpu->arch.hcr_el2;
3c1e7165
MZ		 87}
88
ef2e78dd 89static inline void vcpu_clear_wfx_traps(struct kvm_vcpu *vcpu)
de737089
MZ		 90{
91 vcpu->arch.hcr_el2 &= ~HCR_TWE;
7bdabad1
MZ		 92 if (atomic_read(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe.vlpi_count) ||
93 vcpu->kvm->arch.vgic.nassgireq)
ef2e78dd
MZ		 94 vcpu->arch.hcr_el2 &= ~HCR_TWI;
95 else
96 vcpu->arch.hcr_el2 |= HCR_TWI;
de737089
MZ		 97}
98
ef2e78dd 99static inline void vcpu_set_wfx_traps(struct kvm_vcpu *vcpu)
de737089
MZ		 100{
101 vcpu->arch.hcr_el2 |= HCR_TWE;
ef2e78dd 102 vcpu->arch.hcr_el2 |= HCR_TWI;
de737089
MZ		 103}
104
384b40ca
MR		 105static inline void vcpu_ptrauth_enable(struct kvm_vcpu *vcpu)
106{
107 vcpu->arch.hcr_el2 |= (HCR_API | HCR_APK);
108}
109
110static inline void vcpu_ptrauth_disable(struct kvm_vcpu *vcpu)
111{
112 vcpu->arch.hcr_el2 &= ~(HCR_API | HCR_APK);
113}
114
b7b27fac
DG		 115static inline unsigned long vcpu_get_vsesr(struct kvm_vcpu *vcpu)
116{
117 return vcpu->arch.vsesr_el2;
118}
119
4715c14b
JM		 120static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr)
121{
122 vcpu->arch.vsesr_el2 = vsesr;
123}
124
5c37f1ae 125static __always_inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu)
83a49794
MZ		 126{
127 return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pc;
128}
129
6d4bd909 130static inline unsigned long *__vcpu_elr_el1(const struct kvm_vcpu *vcpu)
83a49794
MZ		 131{
132 return (unsigned long *)&vcpu_gp_regs(vcpu)->elr_el1;
133}
134
6d4bd909
CD		 135static inline unsigned long vcpu_read_elr_el1(const struct kvm_vcpu *vcpu)
136{
137 if (vcpu->arch.sysregs_loaded_on_cpu)
fdec2a9e 138 return read_sysreg_el1(SYS_ELR);
6d4bd909
CD		 139 else
140 return *__vcpu_elr_el1(vcpu);
141}
142
143static inline void vcpu_write_elr_el1(const struct kvm_vcpu *vcpu, unsigned long v)
144{
145 if (vcpu->arch.sysregs_loaded_on_cpu)
fdec2a9e 146 write_sysreg_el1(v, SYS_ELR);
6d4bd909
CD		 147 else
148 *__vcpu_elr_el1(vcpu) = v;
149}
150
5c37f1ae 151static __always_inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu)
83a49794
MZ		 152{
153 return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pstate;
154}
155
5c37f1ae 156static __always_inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
83a49794 157{
b547631f 158 return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT);
83a49794
MZ		 159}
160
5c37f1ae 161static __always_inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
83a49794 162{
27b190bd
MZ		 163 if (vcpu_mode_is_32bit(vcpu))
164 return kvm_condition_valid32(vcpu);
165
166 return true;
83a49794
MZ		 167}
168
83a49794
MZ		 169static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
170{
256c0960 171 *vcpu_cpsr(vcpu) |= PSR_AA32_T_BIT;
83a49794
MZ		 172}
173
c0f09634 174/*
f6be563a
PF		 175 * vcpu_get_reg and vcpu_set_reg should always be passed a register number
176 * coming from a read of ESR_EL2. Otherwise, it may give the wrong result on
177 * AArch32 with banked registers.
c0f09634 178 */
5c37f1ae 179static __always_inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu,
bc45a516
PF		 180 u8 reg_num)
181{
182 return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs.regs[reg_num];
183}
184
5c37f1ae 185static __always_inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
bc45a516
PF		 186 unsigned long val)
187{
188 if (reg_num != 31)
189 vcpu_gp_regs(vcpu)->regs.regs[reg_num] = val;
190}
191
00536ec4 192static inline unsigned long vcpu_read_spsr(const struct kvm_vcpu *vcpu)
83a49794 193{
a8928195
CD		 194 if (vcpu_mode_is_32bit(vcpu))
195 return vcpu_read_spsr32(vcpu);
00536ec4
CD		 196
197 if (vcpu->arch.sysregs_loaded_on_cpu)
fdec2a9e 198 return read_sysreg_el1(SYS_SPSR);
00536ec4 199 else
a8928195 200 return vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1];
00536ec4 201}
b547631f 202
a8928195 203static inline void vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long v)
00536ec4 204{
00536ec4 205 if (vcpu_mode_is_32bit(vcpu)) {
a8928195
CD		 206 vcpu_write_spsr32(vcpu, v);
207 return;
00536ec4
CD		 208 }
209
210 if (vcpu->arch.sysregs_loaded_on_cpu)
fdec2a9e 211 write_sysreg_el1(v, SYS_SPSR);
00536ec4 212 else
a8928195 213 vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1] = v;
83a49794
MZ		 214}
215
1cfbb484
MR		 216/*
217 * The layout of SPSR for an AArch32 state is different when observed from an
218 * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32
219 * view given an AArch64 view.
220 *
221 * In ARM DDI 0487E.a see:
222 *
223 * - The AArch64 view (SPSR_EL2) in section C5.2.18, page C5-426
224 * - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256
225 * - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280
226 *
227 * Which show the following differences:
228 *
229 * | Bit | AA64 | AA32 | Notes |
230 * +-----+------+------+-----------------------------|
231 * | 24 | DIT | J | J is RES0 in ARMv8 |
232 * | 21 | SS | DIT | SS doesn't exist in AArch32 |
233 *
234 * ... and all other bits are (currently) common.
235 */
236static inline unsigned long host_spsr_to_spsr32(unsigned long spsr)
237{
238 const unsigned long overlap = BIT(24) | BIT(21);
239 unsigned long dit = !!(spsr & PSR_AA32_DIT_BIT);
240
241 spsr &= ~overlap;
242
243 spsr |= dit << 21;
244
245 return spsr;
246}
247
83a49794
MZ		 248static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu)
249{
9586a2ea 250 u32 mode;
83a49794 251
9586a2ea 252 if (vcpu_mode_is_32bit(vcpu)) {
256c0960
MR		 253 mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK;
254 return mode > PSR_AA32_MODE_USR;
9586a2ea
SZ		 255 }
256
257 mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK;
b547631f 258
83a49794
MZ		 259 return mode != PSR_MODE_EL0t;
260}
261
5c37f1ae 262static __always_inline u32 kvm_vcpu_get_hsr(const struct kvm_vcpu *vcpu)
83a49794
MZ		 263{
264 return vcpu->arch.fault.esr_el2;
265}
266
5c37f1ae 267static __always_inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu)
3e51d435
MZ		 268{
269 u32 esr = kvm_vcpu_get_hsr(vcpu);
270
271 if (esr & ESR_ELx_CV)
272 return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
273
274 return -1;
275}
276
5c37f1ae 277static __always_inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu)
83a49794
MZ		 278{
279 return vcpu->arch.fault.far_el2;
280}
281
5c37f1ae 282static __always_inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu)
83a49794
MZ		 283{
284 return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8;
285}
286
0067df41
JM		 287static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu)
288{
289 return vcpu->arch.fault.disr_el1;
290}
291
0d97f884
WH		 292static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu)
293{
1c6007d5 294 return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_xVC_IMM_MASK;
0d97f884
WH		 295}
296
5c37f1ae 297static __always_inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)
83a49794 298{
c6d01a94 299 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_ISV);
83a49794
MZ		 300}
301
c726200d
CD		 302static inline unsigned long kvm_vcpu_dabt_iss_nisv_sanitized(const struct kvm_vcpu *vcpu)
303{
304 return kvm_vcpu_get_hsr(vcpu) & (ESR_ELx_CM | ESR_ELx_WNR | ESR_ELx_FSC);
305}
306
83a49794
MZ		 307static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)
308{
c6d01a94 309 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SSE);
83a49794
MZ		 310}
311
b6ae256a
CD		 312static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu)
313{
314 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SF);
315}
316
5c37f1ae 317static __always_inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)
83a49794 318{
c6d01a94 319 return (kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;
83a49794
MZ		 320}
321
5c37f1ae 322static __always_inline bool kvm_vcpu_dabt_iss1tw(const struct kvm_vcpu *vcpu)
83a49794 323{
c6d01a94 324 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_S1PTW);
83a49794
MZ		 325}
326
5c37f1ae 327static __always_inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)
60e21a0e
WD		 328{
329 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_WNR) ||
330 kvm_vcpu_dabt_iss1tw(vcpu); /* AF/DBM update */
331}
332
57c841f1
MZ		 333static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu)
334{
335 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_CM);
336}
337
5c37f1ae 338static __always_inline unsigned int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)
83a49794 339{
c6d01a94 340 return 1 << ((kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);
83a49794
MZ		 341}
342
343/* This one is not specific to Data Abort */
5c37f1ae 344static __always_inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)
83a49794 345{
c6d01a94 346 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_IL);
83a49794
MZ		 347}
348
5c37f1ae 349static __always_inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)
83a49794 350{
561454e2 351 return ESR_ELx_EC(kvm_vcpu_get_hsr(vcpu));
83a49794
MZ		 352}
353
354static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)
355{
c6d01a94 356 return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW;
83a49794
MZ		 357}
358
5c37f1ae 359static __always_inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)
0496daa5 360{
c6d01a94 361 return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC;
0496daa5
CD		 362}
363
5c37f1ae 364static __always_inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)
83a49794 365{
c6d01a94 366 return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC_TYPE;
83a49794
MZ		 367}
368
5c37f1ae 369static __always_inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu)
bb428921 370{
a2b83133 371 switch (kvm_vcpu_trap_get_fault(vcpu)) {
bb428921
JM		 372 case FSC_SEA:
373 case FSC_SEA_TTW0:
374 case FSC_SEA_TTW1:
375 case FSC_SEA_TTW2:
376 case FSC_SEA_TTW3:
377 case FSC_SECC:
378 case FSC_SECC_TTW0:
379 case FSC_SECC_TTW1:
380 case FSC_SECC_TTW2:
381 case FSC_SECC_TTW3:
382 return true;
383 default:
384 return false;
385 }
386}
387
5c37f1ae 388static __always_inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)
c667186f
MZ		 389{
390 u32 esr = kvm_vcpu_get_hsr(vcpu);
1c839141 391 return ESR_ELx_SYS64_ISS_RT(esr);
c667186f
MZ		 392}
393
64cf98fa
CD		 394static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu)
395{
396 if (kvm_vcpu_trap_is_iabt(vcpu))
397 return false;
398
399 return kvm_vcpu_dabt_iswrite(vcpu);
400}
401
4429fc64 402static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
79c64880 403{
8d404c4c 404 return vcpu_read_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;
79c64880
MZ		 405}
406
99adb567
AP		 407static inline bool kvm_arm_get_vcpu_workaround_2_flag(struct kvm_vcpu *vcpu)
408{
409 return vcpu->arch.workaround_flags & VCPU_WORKAROUND_2_FLAG;
410}
411
412static inline void kvm_arm_set_vcpu_workaround_2_flag(struct kvm_vcpu *vcpu,
413 bool flag)
414{
415 if (flag)
416 vcpu->arch.workaround_flags |= VCPU_WORKAROUND_2_FLAG;
417 else
418 vcpu->arch.workaround_flags &= ~VCPU_WORKAROUND_2_FLAG;
419}
420
ce94fe93
MZ		 421static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
422{
8d404c4c 423 if (vcpu_mode_is_32bit(vcpu)) {
256c0960 424 *vcpu_cpsr(vcpu) |= PSR_AA32_E_BIT;
8d404c4c
CD		 425 } else {
426 u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1);
427 sctlr |= (1 << 25);
1975fa56 428 vcpu_write_sys_reg(vcpu, sctlr, SCTLR_EL1);
8d404c4c 429 }
ce94fe93
MZ		 430}
431
6d89d2d9
MZ		 432static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu)
433{
434 if (vcpu_mode_is_32bit(vcpu))
256c0960 435 return !!(*vcpu_cpsr(vcpu) & PSR_AA32_E_BIT);
6d89d2d9 436
8d404c4c 437 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & (1 << 25));
6d89d2d9
MZ		 438}
439
440static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu,
441 unsigned long data,
442 unsigned int len)
443{
444 if (kvm_vcpu_is_be(vcpu)) {
445 switch (len) {
446 case 1:
447 return data & 0xff;
448 case 2:
449 return be16_to_cpu(data & 0xffff);
450 case 4:
451 return be32_to_cpu(data & 0xffffffff);
452 default:
453 return be64_to_cpu(data);
454 }
b3007086
VK		 455 } else {
456 switch (len) {
457 case 1:
458 return data & 0xff;
459 case 2:
460 return le16_to_cpu(data & 0xffff);
461 case 4:
462 return le32_to_cpu(data & 0xffffffff);
463 default:
464 return le64_to_cpu(data);
465 }
6d89d2d9
MZ		 466 }
467
468 return data; /* Leave LE untouched */
469}
470
471static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu,
472 unsigned long data,
473 unsigned int len)
474{
475 if (kvm_vcpu_is_be(vcpu)) {
476 switch (len) {
477 case 1:
478 return data & 0xff;
479 case 2:
480 return cpu_to_be16(data & 0xffff);
481 case 4:
482 return cpu_to_be32(data & 0xffffffff);
483 default:
484 return cpu_to_be64(data);
485 }
b3007086
VK		 486 } else {
487 switch (len) {
488 case 1:
489 return data & 0xff;
490 case 2:
491 return cpu_to_le16(data & 0xffff);
492 case 4:
493 return cpu_to_le32(data & 0xffffffff);
494 default:
495 return cpu_to_le64(data);
496 }
6d89d2d9
MZ		 497 }
498
499 return data; /* Leave LE untouched */
500}
501
5c37f1ae 502static __always_inline void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr)
bd7d95ca 503{
30685d78 504 if (vcpu_mode_is_32bit(vcpu)) {
bd7d95ca 505 kvm_skip_instr32(vcpu, is_wide_instr);
30685d78 506 } else {
bd7d95ca 507 *vcpu_pc(vcpu) += 4;
30685d78
DM		 508 *vcpu_cpsr(vcpu) &= ~PSR_BTYPE_MASK;
509 }
bd7d95ca
MR		 510
511 /* advance the singlestep state machine */
512 *vcpu_cpsr(vcpu) &= ~DBG_SPSR_SS;
513}
514
515/*
516 * Skip an instruction which has been emulated at hyp while most guest sysregs
517 * are live.
518 */
c50cb043 519static __always_inline void __kvm_skip_instr(struct kvm_vcpu *vcpu)
bd7d95ca 520{
fdec2a9e
DM		 521 *vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR);
522 vcpu->arch.ctxt.gp_regs.regs.pstate = read_sysreg_el2(SYS_SPSR);
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MR		 523
524 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
525
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DM		 526 write_sysreg_el2(vcpu->arch.ctxt.gp_regs.regs.pstate, SYS_SPSR);
527 write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR);
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MR		 528}
529
83a49794 530#endif /* __ARM64_KVM_EMULATE_H__ */
Linux 6.x block layer and io_uring tree(s)