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KVM: arm64: Handle RAS SErrors from EL2 on guest exit
[linux-2.6-block.git] / arch / arm64 / include / asm / kvm_emulate.h
CommitLineData
83a49794
MZ		 1/*
2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * Derived from arch/arm/include/kvm_emulate.h
6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
7 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#ifndef __ARM64_KVM_EMULATE_H__
23#define __ARM64_KVM_EMULATE_H__
24
25#include <linux/kvm_host.h>
c6d01a94
MR		 26
27#include <asm/esr.h>
83a49794
MZ		 28#include <asm/kvm_arm.h>
29#include <asm/kvm_mmio.h>
30#include <asm/ptrace.h>
4429fc64 31#include <asm/cputype.h>
68908bf7 32#include <asm/virt.h>
83a49794 33
b547631f
MZ		 34unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num);
35unsigned long *vcpu_spsr32(const struct kvm_vcpu *vcpu);
36
27b190bd
MZ		 37bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
38void kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr);
39
83a49794 40void kvm_inject_undefined(struct kvm_vcpu *vcpu);
10cf3390 41void kvm_inject_vabt(struct kvm_vcpu *vcpu);
83a49794
MZ		 42void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
43void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
74a64a98
MZ		 44void kvm_inject_undef32(struct kvm_vcpu *vcpu);
45void kvm_inject_dabt32(struct kvm_vcpu *vcpu, unsigned long addr);
46void kvm_inject_pabt32(struct kvm_vcpu *vcpu, unsigned long addr);
83a49794 47
b856a591
CD		 48static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
49{
50 vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS;
68908bf7
MZ		 51 if (is_kernel_in_hyp_mode())
52 vcpu->arch.hcr_el2 |= HCR_E2H;
801f6772
MZ		 53 if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features))
54 vcpu->arch.hcr_el2 &= ~HCR_RW;
b856a591
CD		 55}
56
3c1e7165
MZ		 57static inline unsigned long vcpu_get_hcr(struct kvm_vcpu *vcpu)
58{
59 return vcpu->arch.hcr_el2;
60}
61
62static inline void vcpu_set_hcr(struct kvm_vcpu *vcpu, unsigned long hcr)
63{
64 vcpu->arch.hcr_el2 = hcr;
65}
66
4715c14b
JM		 67static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr)
68{
69 vcpu->arch.vsesr_el2 = vsesr;
70}
71
83a49794
MZ		 72static inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu)
73{
74 return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pc;
75}
76
77static inline unsigned long *vcpu_elr_el1(const struct kvm_vcpu *vcpu)
78{
79 return (unsigned long *)&vcpu_gp_regs(vcpu)->elr_el1;
80}
81
82static inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu)
83{
84 return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pstate;
85}
86
87static inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
88{
b547631f 89 return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT);
83a49794
MZ		 90}
91
92static inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
93{
27b190bd
MZ		 94 if (vcpu_mode_is_32bit(vcpu))
95 return kvm_condition_valid32(vcpu);
96
97 return true;
83a49794
MZ		 98}
99
100static inline void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr)
101{
27b190bd
MZ		 102 if (vcpu_mode_is_32bit(vcpu))
103 kvm_skip_instr32(vcpu, is_wide_instr);
104 else
105 *vcpu_pc(vcpu) += 4;
83a49794
MZ		 106}
107
108static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
109{
b547631f 110 *vcpu_cpsr(vcpu) |= COMPAT_PSR_T_BIT;
83a49794
MZ		 111}
112
c0f09634 113/*
f6be563a
PF		 114 * vcpu_get_reg and vcpu_set_reg should always be passed a register number
115 * coming from a read of ESR_EL2. Otherwise, it may give the wrong result on
116 * AArch32 with banked registers.
c0f09634 117 */
bc45a516
PF		 118static inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu,
119 u8 reg_num)
120{
121 return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs.regs[reg_num];
122}
123
124static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
125 unsigned long val)
126{
127 if (reg_num != 31)
128 vcpu_gp_regs(vcpu)->regs.regs[reg_num] = val;
129}
130
83a49794
MZ		 131/* Get vcpu SPSR for current mode */
132static inline unsigned long *vcpu_spsr(const struct kvm_vcpu *vcpu)
133{
b547631f
MZ		 134 if (vcpu_mode_is_32bit(vcpu))
135 return vcpu_spsr32(vcpu);
136
83a49794
MZ		 137 return (unsigned long *)&vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1];
138}
139
140static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu)
141{
9586a2ea 142 u32 mode;
83a49794 143
9586a2ea
SZ		 144 if (vcpu_mode_is_32bit(vcpu)) {
145 mode = *vcpu_cpsr(vcpu) & COMPAT_PSR_MODE_MASK;
b547631f 146 return mode > COMPAT_PSR_MODE_USR;
9586a2ea
SZ		 147 }
148
149 mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK;
b547631f 150
83a49794
MZ		 151 return mode != PSR_MODE_EL0t;
152}
153
154static inline u32 kvm_vcpu_get_hsr(const struct kvm_vcpu *vcpu)
155{
156 return vcpu->arch.fault.esr_el2;
157}
158
3e51d435
MZ		 159static inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu)
160{
161 u32 esr = kvm_vcpu_get_hsr(vcpu);
162
163 if (esr & ESR_ELx_CV)
164 return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
165
166 return -1;
167}
168
83a49794
MZ		 169static inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu)
170{
171 return vcpu->arch.fault.far_el2;
172}
173
174static inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu)
175{
176 return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8;
177}
178
0067df41
JM		 179static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu)
180{
181 return vcpu->arch.fault.disr_el1;
182}
183
0d97f884
WH		 184static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu)
185{
1c6007d5 186 return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_xVC_IMM_MASK;
0d97f884
WH		 187}
188
83a49794
MZ		 189static inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)
190{
c6d01a94 191 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_ISV);
83a49794
MZ		 192}
193
83a49794
MZ		 194static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)
195{
c6d01a94 196 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SSE);
83a49794
MZ		 197}
198
199static inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)
200{
c6d01a94 201 return (kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;
83a49794
MZ		 202}
203
83a49794
MZ		 204static inline bool kvm_vcpu_dabt_iss1tw(const struct kvm_vcpu *vcpu)
205{
c6d01a94 206 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_S1PTW);
83a49794
MZ		 207}
208
60e21a0e
WD		 209static inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)
210{
211 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_WNR) ||
212 kvm_vcpu_dabt_iss1tw(vcpu); /* AF/DBM update */
213}
214
57c841f1
MZ		 215static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu)
216{
217 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_CM);
218}
219
83a49794
MZ		 220static inline int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)
221{
c6d01a94 222 return 1 << ((kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);
83a49794
MZ		 223}
224
225/* This one is not specific to Data Abort */
226static inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)
227{
c6d01a94 228 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_IL);
83a49794
MZ		 229}
230
231static inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)
232{
561454e2 233 return ESR_ELx_EC(kvm_vcpu_get_hsr(vcpu));
83a49794
MZ		 234}
235
236static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)
237{
c6d01a94 238 return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW;
83a49794
MZ		 239}
240
241static inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)
0496daa5 242{
c6d01a94 243 return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC;
0496daa5
CD		 244}
245
246static inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)
83a49794 247{
c6d01a94 248 return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC_TYPE;
83a49794
MZ		 249}
250
bb428921
JM		 251static inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu)
252{
a2b83133 253 switch (kvm_vcpu_trap_get_fault(vcpu)) {
bb428921
JM		 254 case FSC_SEA:
255 case FSC_SEA_TTW0:
256 case FSC_SEA_TTW1:
257 case FSC_SEA_TTW2:
258 case FSC_SEA_TTW3:
259 case FSC_SECC:
260 case FSC_SECC_TTW0:
261 case FSC_SECC_TTW1:
262 case FSC_SECC_TTW2:
263 case FSC_SECC_TTW3:
264 return true;
265 default:
266 return false;
267 }
268}
269
c667186f
MZ		 270static inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)
271{
272 u32 esr = kvm_vcpu_get_hsr(vcpu);
273 return (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
274}
275
4429fc64 276static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
79c64880 277{
4429fc64 278 return vcpu_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;
79c64880
MZ		 279}
280
ce94fe93
MZ		 281static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
282{
283 if (vcpu_mode_is_32bit(vcpu))
284 *vcpu_cpsr(vcpu) |= COMPAT_PSR_E_BIT;
285 else
286 vcpu_sys_reg(vcpu, SCTLR_EL1) |= (1 << 25);
287}
288
6d89d2d9
MZ		 289static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu)
290{
291 if (vcpu_mode_is_32bit(vcpu))
292 return !!(*vcpu_cpsr(vcpu) & COMPAT_PSR_E_BIT);
293
294 return !!(vcpu_sys_reg(vcpu, SCTLR_EL1) & (1 << 25));
295}
296
297static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu,
298 unsigned long data,
299 unsigned int len)
300{
301 if (kvm_vcpu_is_be(vcpu)) {
302 switch (len) {
303 case 1:
304 return data & 0xff;
305 case 2:
306 return be16_to_cpu(data & 0xffff);
307 case 4:
308 return be32_to_cpu(data & 0xffffffff);
309 default:
310 return be64_to_cpu(data);
311 }
b3007086
VK		 312 } else {
313 switch (len) {
314 case 1:
315 return data & 0xff;
316 case 2:
317 return le16_to_cpu(data & 0xffff);
318 case 4:
319 return le32_to_cpu(data & 0xffffffff);
320 default:
321 return le64_to_cpu(data);
322 }
6d89d2d9
MZ		 323 }
324
325 return data; /* Leave LE untouched */
326}
327
328static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu,
329 unsigned long data,
330 unsigned int len)
331{
332 if (kvm_vcpu_is_be(vcpu)) {
333 switch (len) {
334 case 1:
335 return data & 0xff;
336 case 2:
337 return cpu_to_be16(data & 0xffff);
338 case 4:
339 return cpu_to_be32(data & 0xffffffff);
340 default:
341 return cpu_to_be64(data);
342 }
b3007086
VK		 343 } else {
344 switch (len) {
345 case 1:
346 return data & 0xff;
347 case 2:
348 return cpu_to_le16(data & 0xffff);
349 case 4:
350 return cpu_to_le32(data & 0xffffffff);
351 default:
352 return cpu_to_le64(data);
353 }
6d89d2d9
MZ		 354 }
355
356 return data; /* Leave LE untouched */
357}
358
83a49794 359#endif /* __ARM64_KVM_EMULATE_H__ */
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