[linux-2.6-block.git] / arch / arm64 / include / asm / kvm_arm.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2012,2013 - ARM Ltd
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 */

#ifndef __ARM64_KVM_ARM_H__
#define __ARM64_KVM_ARM_H__

#include <asm/esr.h>
#include <asm/memory.h>
#include <asm/sysreg.h>
#include <asm/types.h>

/* Hyp Configuration Register (HCR) bits */

#define HCR_TID5	(UL(1) << 58)
#define HCR_DCT		(UL(1) << 57)
#define HCR_ATA_SHIFT	56
#define HCR_ATA		(UL(1) << HCR_ATA_SHIFT)
#define HCR_TTLBOS	(UL(1) << 55)
#define HCR_TTLBIS	(UL(1) << 54)
#define HCR_ENSCXT	(UL(1) << 53)
#define HCR_TOCU	(UL(1) << 52)
#define HCR_AMVOFFEN	(UL(1) << 51)
#define HCR_TICAB	(UL(1) << 50)
#define HCR_TID4	(UL(1) << 49)
#define HCR_FIEN	(UL(1) << 47)
#define HCR_FWB		(UL(1) << 46)
#define HCR_NV2		(UL(1) << 45)
#define HCR_AT		(UL(1) << 44)
#define HCR_NV1		(UL(1) << 43)
#define HCR_NV		(UL(1) << 42)
#define HCR_API		(UL(1) << 41)
#define HCR_APK		(UL(1) << 40)
#define HCR_TEA		(UL(1) << 37)
#define HCR_TERR	(UL(1) << 36)
#define HCR_TLOR	(UL(1) << 35)
#define HCR_E2H		(UL(1) << 34)
#define HCR_ID		(UL(1) << 33)
#define HCR_CD		(UL(1) << 32)
#define HCR_RW_SHIFT	31
#define HCR_RW		(UL(1) << HCR_RW_SHIFT)
#define HCR_TRVM	(UL(1) << 30)
#define HCR_HCD		(UL(1) << 29)
#define HCR_TDZ		(UL(1) << 28)
#define HCR_TGE		(UL(1) << 27)
#define HCR_TVM		(UL(1) << 26)
#define HCR_TTLB	(UL(1) << 25)
#define HCR_TPU		(UL(1) << 24)
#define HCR_TPC		(UL(1) << 23) /* HCR_TPCP if FEAT_DPB */
#define HCR_TSW		(UL(1) << 22)
#define HCR_TACR	(UL(1) << 21)
#define HCR_TIDCP	(UL(1) << 20)
#define HCR_TSC		(UL(1) << 19)
#define HCR_TID3	(UL(1) << 18)
#define HCR_TID2	(UL(1) << 17)
#define HCR_TID1	(UL(1) << 16)
#define HCR_TID0	(UL(1) << 15)
#define HCR_TWE		(UL(1) << 14)
#define HCR_TWI		(UL(1) << 13)
#define HCR_DC		(UL(1) << 12)
#define HCR_BSU		(3 << 10)
#define HCR_BSU_IS	(UL(1) << 10)
#define HCR_FB		(UL(1) << 9)
#define HCR_VSE		(UL(1) << 8)
#define HCR_VI		(UL(1) << 7)
#define HCR_VF		(UL(1) << 6)
#define HCR_AMO		(UL(1) << 5)
#define HCR_IMO		(UL(1) << 4)
#define HCR_FMO		(UL(1) << 3)
#define HCR_PTW		(UL(1) << 2)
#define HCR_SWIO	(UL(1) << 1)
#define HCR_VM		(UL(1) << 0)
#define HCR_RES0	((UL(1) << 48) | (UL(1) << 39))

/*
 * The bits we set in HCR:
 * TLOR:	Trap LORegion register accesses
 * RW:		64bit by default, can be overridden for 32bit VMs
 * TACR:	Trap ACTLR
 * TSC:		Trap SMC
 * TSW:		Trap cache operations by set/way
 * TWE:		Trap WFE
 * TWI:		Trap WFI
 * TIDCP:	Trap L2CTLR/L2ECTLR
 * BSU_IS:	Upgrade barriers to the inner shareable domain
 * FB:		Force broadcast of all maintenance operations
 * AMO:		Override CPSR.A and enable signaling with VA
 * IMO:		Override CPSR.I and enable signaling with VI
 * FMO:		Override CPSR.F and enable signaling with VF
 * SWIO:	Turn set/way invalidates into set/way clean+invalidate
 * PTW:		Take a stage2 fault if a stage1 walk steps in device memory
 * TID3:	Trap EL1 reads of group 3 ID registers
 * TID2:	Trap CTR_EL0, CCSIDR2_EL1, CLIDR_EL1, and CSSELR_EL1
 */
#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
			 HCR_BSU_IS | HCR_FB | HCR_TACR | \
			 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \
			 HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3)
#define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA)
#define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC)
#define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)

#define HCRX_GUEST_FLAGS \
	(HCRX_EL2_SMPME | HCRX_EL2_TCR2En | \
	 (cpus_have_final_cap(ARM64_HAS_MOPS) ? (HCRX_EL2_MSCEn | HCRX_EL2_MCE2) : 0))
#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En)

/* TCR_EL2 Registers bits */
#define TCR_EL2_DS		(1UL << 32)
#define TCR_EL2_RES1		((1U << 31) | (1 << 23))
#define TCR_EL2_TBI		(1 << 20)
#define TCR_EL2_PS_SHIFT	16
#define TCR_EL2_PS_MASK		(7 << TCR_EL2_PS_SHIFT)
#define TCR_EL2_PS_40B		(2 << TCR_EL2_PS_SHIFT)
#define TCR_EL2_TG0_MASK	TCR_TG0_MASK
#define TCR_EL2_SH0_MASK	TCR_SH0_MASK
#define TCR_EL2_ORGN0_MASK	TCR_ORGN0_MASK
#define TCR_EL2_IRGN0_MASK	TCR_IRGN0_MASK
#define TCR_EL2_T0SZ_MASK	0x3f
#define TCR_EL2_MASK	(TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \
			 TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK)

/* VTCR_EL2 Registers bits */
#define VTCR_EL2_DS		TCR_EL2_DS
#define VTCR_EL2_RES1		(1U << 31)
#define VTCR_EL2_HD		(1 << 22)
#define VTCR_EL2_HA		(1 << 21)
#define VTCR_EL2_PS_SHIFT	TCR_EL2_PS_SHIFT
#define VTCR_EL2_PS_MASK	TCR_EL2_PS_MASK
#define VTCR_EL2_TG0_MASK	TCR_TG0_MASK
#define VTCR_EL2_TG0_4K		TCR_TG0_4K
#define VTCR_EL2_TG0_16K	TCR_TG0_16K
#define VTCR_EL2_TG0_64K	TCR_TG0_64K
#define VTCR_EL2_SH0_MASK	TCR_SH0_MASK
#define VTCR_EL2_SH0_INNER	TCR_SH0_INNER
#define VTCR_EL2_ORGN0_MASK	TCR_ORGN0_MASK
#define VTCR_EL2_ORGN0_WBWA	TCR_ORGN0_WBWA
#define VTCR_EL2_IRGN0_MASK	TCR_IRGN0_MASK
#define VTCR_EL2_IRGN0_WBWA	TCR_IRGN0_WBWA
#define VTCR_EL2_SL0_SHIFT	6
#define VTCR_EL2_SL0_MASK	(3 << VTCR_EL2_SL0_SHIFT)
#define VTCR_EL2_T0SZ_MASK	0x3f
#define VTCR_EL2_VS_SHIFT	19
#define VTCR_EL2_VS_8BIT	(0 << VTCR_EL2_VS_SHIFT)
#define VTCR_EL2_VS_16BIT	(1 << VTCR_EL2_VS_SHIFT)

#define VTCR_EL2_T0SZ(x)	TCR_T0SZ(x)

/*
 * We configure the Stage-2 page tables to always restrict the IPA space to be
 * 40 bits wide (T0SZ = 24).  Systems with a PARange smaller than 40 bits are
 * not known to exist and will break with this configuration.
 *
 * The VTCR_EL2 is configured per VM and is initialised in kvm_init_stage2_mmu.
 *
 * Note that when using 4K pages, we concatenate two first level page tables
 * together. With 16K pages, we concatenate 16 first level page tables.
 *
 */

#define VTCR_EL2_COMMON_BITS	(VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
				 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1)

/*
 * VTCR_EL2:SL0 indicates the entry level for Stage2 translation.
 * Interestingly, it depends on the page size.
 * See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a
 *
 *	-----------------------------------------
 *	| Entry level		|  4K  | 16K/64K |
 *	------------------------------------------
 *	| Level: 0		|  2   |   -     |
 *	------------------------------------------
 *	| Level: 1		|  1   |   2     |
 *	------------------------------------------
 *	| Level: 2		|  0   |   1     |
 *	------------------------------------------
 *	| Level: 3		|  -   |   0     |
 *	------------------------------------------
 *
 * The table roughly translates to :
 *
 *	SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level
 *
 * Where TGRAN_SL0_BASE is a magic number depending on the page size:
 * 	TGRAN_SL0_BASE(4K) = 2
 *	TGRAN_SL0_BASE(16K) = 3
 *	TGRAN_SL0_BASE(64K) = 3
 * provided we take care of ruling out the unsupported cases and
 * Entry_Level = 4 - Number_of_levels.
 *
 */
#ifdef CONFIG_ARM64_64K_PAGES

#define VTCR_EL2_TGRAN			VTCR_EL2_TG0_64K
#define VTCR_EL2_TGRAN_SL0_BASE		3UL

#elif defined(CONFIG_ARM64_16K_PAGES)

#define VTCR_EL2_TGRAN			VTCR_EL2_TG0_16K
#define VTCR_EL2_TGRAN_SL0_BASE		3UL

#else	/* 4K */

#define VTCR_EL2_TGRAN			VTCR_EL2_TG0_4K
#define VTCR_EL2_TGRAN_SL0_BASE		2UL

#endif

#define VTCR_EL2_LVLS_TO_SL0(levels)	\
	((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT)
#define VTCR_EL2_SL0_TO_LVLS(sl0)	\
	((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE)
#define VTCR_EL2_LVLS(vtcr)		\
	VTCR_EL2_SL0_TO_LVLS(((vtcr) & VTCR_EL2_SL0_MASK) >> VTCR_EL2_SL0_SHIFT)

#define VTCR_EL2_FLAGS			(VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN)
#define VTCR_EL2_IPA(vtcr)		(64 - ((vtcr) & VTCR_EL2_T0SZ_MASK))

/*
 * ARM VMSAv8-64 defines an algorithm for finding the translation table
 * descriptors in section D4.2.8 in ARM DDI 0487C.a.
 *
 * The algorithm defines the expectations on the translation table
 * addresses for each level, based on PAGE_SIZE, entry level
 * and the translation table size (T0SZ). The variable "x" in the
 * algorithm determines the alignment of a table base address at a given
 * level and thus determines the alignment of VTTBR:BADDR for stage2
 * page table entry level.
 * Since the number of bits resolved at the entry level could vary
 * depending on the T0SZ, the value of "x" is defined based on a
 * Magic constant for a given PAGE_SIZE and Entry Level. The
 * intermediate levels must be always aligned to the PAGE_SIZE (i.e,
 * x = PAGE_SHIFT).
 *
 * The value of "x" for entry level is calculated as :
 *    x = Magic_N - T0SZ
 *
 * where Magic_N is an integer depending on the page size and the entry
 * level of the page table as below:
 *
 *	--------------------------------------------
 *	| Entry level		|  4K    16K   64K |
 *	--------------------------------------------
 *	| Level: 0 (4 levels)	| 28   |  -  |  -  |
 *	--------------------------------------------
 *	| Level: 1 (3 levels)	| 37   | 31  | 25  |
 *	--------------------------------------------
 *	| Level: 2 (2 levels)	| 46   | 42  | 38  |
 *	--------------------------------------------
 *	| Level: 3 (1 level)	| -    | 53  | 51  |
 *	--------------------------------------------
 *
 * We have a magic formula for the Magic_N below:
 *
 *  Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels)
 *
 * where Number_of_levels = (4 - Level). We are only interested in the
 * value for Entry_Level for the stage2 page table.
 *
 * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows:
 *
 *	x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT)
 *	  = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels)
 *
 * Here is one way to explain the Magic Formula:
 *
 *  x = log2(Size_of_Entry_Level_Table)
 *
 * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another
 * PAGE_SHIFT bits in the PTE, we have :
 *
 *  Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT)
 *		     = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3
 *  where n = number of levels, and since each pointer is 8bytes, we have:
 *
 *  x = Bits_Entry_Level + 3
 *    = IPA_SHIFT - (PAGE_SHIFT - 3) * n
 *
 * The only constraint here is that, we have to find the number of page table
 * levels for a given IPA size (which we do, see stage2_pt_levels())
 */
#define ARM64_VTTBR_X(ipa, levels)	((ipa) - ((levels) * (PAGE_SHIFT - 3)))

#define VTTBR_CNP_BIT     (UL(1))
#define VTTBR_VMID_SHIFT  (UL(48))
#define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)

/* Hyp System Trap Register */
#define HSTR_EL2_T(x)	(1 << x)

/* Hyp Coprocessor Trap Register Shifts */
#define CPTR_EL2_TFP_SHIFT 10

/* Hyp Coprocessor Trap Register */
#define CPTR_EL2_TCPAC	(1U << 31)
#define CPTR_EL2_TAM	(1 << 30)
#define CPTR_EL2_TTA	(1 << 20)
#define CPTR_EL2_TSM	(1 << 12)
#define CPTR_EL2_TFP	(1 << CPTR_EL2_TFP_SHIFT)
#define CPTR_EL2_TZ	(1 << 8)
#define CPTR_NVHE_EL2_RES1	0x000032ff /* known RES1 bits in CPTR_EL2 (nVHE) */
#define CPTR_NVHE_EL2_RES0	(GENMASK(63, 32) |	\
				 GENMASK(29, 21) |	\
				 GENMASK(19, 14) |	\
				 BIT(11))

/* Hyp Debug Configuration Register bits */
#define MDCR_EL2_E2TB_MASK	(UL(0x3))
#define MDCR_EL2_E2TB_SHIFT	(UL(24))
#define MDCR_EL2_HPMFZS		(UL(1) << 36)
#define MDCR_EL2_HPMFZO		(UL(1) << 29)
#define MDCR_EL2_MTPME		(UL(1) << 28)
#define MDCR_EL2_TDCC		(UL(1) << 27)
#define MDCR_EL2_HLP		(UL(1) << 26)
#define MDCR_EL2_HCCD		(UL(1) << 23)
#define MDCR_EL2_TTRF		(UL(1) << 19)
#define MDCR_EL2_HPMD		(UL(1) << 17)
#define MDCR_EL2_TPMS		(UL(1) << 14)
#define MDCR_EL2_E2PB_MASK	(UL(0x3))
#define MDCR_EL2_E2PB_SHIFT	(UL(12))
#define MDCR_EL2_TDRA		(UL(1) << 11)
#define MDCR_EL2_TDOSA		(UL(1) << 10)
#define MDCR_EL2_TDA		(UL(1) << 9)
#define MDCR_EL2_TDE		(UL(1) << 8)
#define MDCR_EL2_HPME		(UL(1) << 7)
#define MDCR_EL2_TPM		(UL(1) << 6)
#define MDCR_EL2_TPMCR		(UL(1) << 5)
#define MDCR_EL2_HPMN_MASK	(UL(0x1F))
#define MDCR_EL2_RES0		(GENMASK(63, 37) |	\
				 GENMASK(35, 30) |	\
				 GENMASK(25, 24) |	\
				 GENMASK(22, 20) |	\
				 BIT(18) |		\
				 GENMASK(16, 15))

/*
 * FGT register definitions
 *
 * RES0 and polarity masks as of DDI0487J.a, to be updated as needed.
 * We're not using the generated masks as they are usually ahead of
 * the published ARM ARM, which we use as a reference.
 *
 * Once we get to a point where the two describe the same thing, we'll
 * merge the definitions. One day.
 */
#define __HFGRTR_EL2_RES0	HFGxTR_EL2_RES0
#define __HFGRTR_EL2_MASK	GENMASK(49, 0)
#define __HFGRTR_EL2_nMASK	~(__HFGRTR_EL2_RES0 | __HFGRTR_EL2_MASK)

/*
 * The HFGWTR bits are a subset of HFGRTR bits. To ensure we don't miss any
 * future additions, define __HFGWTR* macros relative to __HFGRTR* ones.
 */
#define __HFGRTR_ONLY_MASK	(BIT(46) | BIT(42) | BIT(40) | BIT(28) | \
				 GENMASK(26, 25) | BIT(21) | BIT(18) | \
				 GENMASK(15, 14) | GENMASK(10, 9) | BIT(2))
#define __HFGWTR_EL2_RES0	(__HFGRTR_EL2_RES0 | __HFGRTR_ONLY_MASK)
#define __HFGWTR_EL2_MASK	(__HFGRTR_EL2_MASK & ~__HFGRTR_ONLY_MASK)
#define __HFGWTR_EL2_nMASK	~(__HFGWTR_EL2_RES0 | __HFGWTR_EL2_MASK)

#define __HFGITR_EL2_RES0	HFGITR_EL2_RES0
#define __HFGITR_EL2_MASK	(BIT(62) | BIT(60) | GENMASK(54, 0))
#define __HFGITR_EL2_nMASK	~(__HFGITR_EL2_RES0 | __HFGITR_EL2_MASK)

#define __HDFGRTR_EL2_RES0	HDFGRTR_EL2_RES0
#define __HDFGRTR_EL2_MASK	(BIT(63) | GENMASK(58, 50) | GENMASK(48, 43) | \
				 GENMASK(41, 40) | GENMASK(37, 22) | \
				 GENMASK(19, 9) | GENMASK(7, 0))
#define __HDFGRTR_EL2_nMASK	~(__HDFGRTR_EL2_RES0 | __HDFGRTR_EL2_MASK)

#define __HDFGWTR_EL2_RES0	HDFGWTR_EL2_RES0
#define __HDFGWTR_EL2_MASK	(GENMASK(57, 52) | GENMASK(50, 48) | \
				 GENMASK(46, 44) | GENMASK(42, 41) | \
				 GENMASK(37, 35) | GENMASK(33, 31) | \
				 GENMASK(29, 23) | GENMASK(21, 10) | \
				 GENMASK(8, 7) | GENMASK(5, 0))
#define __HDFGWTR_EL2_nMASK	~(__HDFGWTR_EL2_RES0 | __HDFGWTR_EL2_MASK)

#define __HAFGRTR_EL2_RES0	HAFGRTR_EL2_RES0
#define __HAFGRTR_EL2_MASK	(GENMASK(49, 17) | GENMASK(4, 0))
#define __HAFGRTR_EL2_nMASK	~(__HAFGRTR_EL2_RES0 | __HAFGRTR_EL2_MASK)

/* Similar definitions for HCRX_EL2 */
#define __HCRX_EL2_RES0         HCRX_EL2_RES0
#define __HCRX_EL2_MASK		(BIT(6))
#define __HCRX_EL2_nMASK	~(__HCRX_EL2_RES0 | __HCRX_EL2_MASK)

/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
#define HPFAR_MASK	(~UL(0xf))
/*
 * We have
 *	PAR	[PA_Shift - 1	: 12] = PA	[PA_Shift - 1 : 12]
 *	HPFAR	[PA_Shift - 9	: 4]  = FIPA	[PA_Shift - 1 : 12]
 *
 * Always assume 52 bit PA since at this point, we don't know how many PA bits
 * the page table has been set up for. This should be safe since unused address
 * bits in PAR are res0.
 */
#define PAR_TO_HPFAR(par)		\
	(((par) & GENMASK_ULL(52 - 1, 12)) >> 8)

#define ECN(x) { ESR_ELx_EC_##x, #x }

#define kvm_arm_exception_class \
	ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \
	ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(PAC), ECN(CP14_64), \
	ECN(SVC64), ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(SVE), \
	ECN(IMP_DEF), ECN(IABT_LOW), ECN(IABT_CUR), \
	ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
	ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \
	ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \
	ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \
	ECN(BKPT32), ECN(VECTOR32), ECN(BRK64), ECN(ERET)

#define CPACR_EL1_TTA		(1 << 28)

#define kvm_mode_names				\
	{ PSR_MODE_EL0t,	"EL0t" },	\
	{ PSR_MODE_EL1t,	"EL1t" },	\
	{ PSR_MODE_EL1h,	"EL1h" },	\
	{ PSR_MODE_EL2t,	"EL2t" },	\
	{ PSR_MODE_EL2h,	"EL2h" },	\
	{ PSR_MODE_EL3t,	"EL3t" },	\
	{ PSR_MODE_EL3h,	"EL3h" },	\
	{ PSR_AA32_MODE_USR,	"32-bit USR" },	\
	{ PSR_AA32_MODE_FIQ,	"32-bit FIQ" },	\
	{ PSR_AA32_MODE_IRQ,	"32-bit IRQ" },	\
	{ PSR_AA32_MODE_SVC,	"32-bit SVC" },	\
	{ PSR_AA32_MODE_ABT,	"32-bit ABT" },	\
	{ PSR_AA32_MODE_HYP,	"32-bit HYP" },	\
	{ PSR_AA32_MODE_UND,	"32-bit UND" },	\
	{ PSR_AA32_MODE_SYS,	"32-bit SYS" }

#endif /* __ARM64_KVM_ARM_H__ */
Commit	Line	Data
caab277b	1	/* SPDX-License-Identifier: GPL-2.0-only */
0369f6a3 MZ	2	/*
	3	* Copyright (C) 2012,2013 - ARM Ltd
	4	* Author: Marc Zyngier <marc.zyngier@arm.com>
0369f6a3 MZ	5	*/
	6
	7	#ifndef __ARM64_KVM_ARM_H__
	8	#define __ARM64_KVM_ARM_H__
	9
6e53031e	10	#include <asm/esr.h>
286fb1cc	11	#include <asm/memory.h>
af94aad4	12	#include <asm/sysreg.h>
0369f6a3 MZ	13	#include <asm/types.h>
	14
	15	/* Hyp Configuration Register (HCR) bits */
2d701243 FT	16
	17	#define HCR_TID5 (UL(1) << 58)
	18	#define HCR_DCT (UL(1) << 57)
e1f358b5 SP	19	#define HCR_ATA_SHIFT 56
e1f358b5 SP	20	#define HCR_ATA (UL(1) << HCR_ATA_SHIFT)
3ea84b4f MZ	21	#define HCR_TTLBOS (UL(1) << 55)
	22	#define HCR_TTLBIS (UL(1) << 54)
	23	#define HCR_ENSCXT (UL(1) << 53)
	24	#define HCR_TOCU (UL(1) << 52)
2d701243	25	#define HCR_AMVOFFEN (UL(1) << 51)
3ea84b4f	26	#define HCR_TICAB (UL(1) << 50)
c876c3f1	27	#define HCR_TID4 (UL(1) << 49)
2d701243	28	#define HCR_FIEN (UL(1) << 47)
e48d53a9	29	#define HCR_FWB (UL(1) << 46)
3ea84b4f MZ	30	#define HCR_NV2 (UL(1) << 45)
	31	#define HCR_AT (UL(1) << 44)
	32	#define HCR_NV1 (UL(1) << 43)
	33	#define HCR_NV (UL(1) << 42)
b3669b1e MR	34	#define HCR_API (UL(1) << 41)
b3669b1e MR	35	#define HCR_APK (UL(1) << 40)
558daf69 DG	36	#define HCR_TEA (UL(1) << 37)
558daf69 DG	37	#define HCR_TERR (UL(1) << 36)
cc33c4e2	38	#define HCR_TLOR (UL(1) << 35)
68908bf7	39	#define HCR_E2H (UL(1) << 34)
0369f6a3 MZ	40	#define HCR_ID (UL(1) << 33)
	41	#define HCR_CD (UL(1) << 32)
	42	#define HCR_RW_SHIFT 31
	43	#define HCR_RW (UL(1) << HCR_RW_SHIFT)
	44	#define HCR_TRVM (UL(1) << 30)
	45	#define HCR_HCD (UL(1) << 29)
	46	#define HCR_TDZ (UL(1) << 28)
	47	#define HCR_TGE (UL(1) << 27)
	48	#define HCR_TVM (UL(1) << 26)
	49	#define HCR_TTLB (UL(1) << 25)
	50	#define HCR_TPU (UL(1) << 24)
dabb1667	51	#define HCR_TPC (UL(1) << 23) /* HCR_TPCP if FEAT_DPB */
0369f6a3	52	#define HCR_TSW (UL(1) << 22)
dabb1667	53	#define HCR_TACR (UL(1) << 21)
0369f6a3 MZ	54	#define HCR_TIDCP (UL(1) << 20)
	55	#define HCR_TSC (UL(1) << 19)
	56	#define HCR_TID3 (UL(1) << 18)
	57	#define HCR_TID2 (UL(1) << 17)
	58	#define HCR_TID1 (UL(1) << 16)
	59	#define HCR_TID0 (UL(1) << 15)
	60	#define HCR_TWE (UL(1) << 14)
	61	#define HCR_TWI (UL(1) << 13)
	62	#define HCR_DC (UL(1) << 12)
	63	#define HCR_BSU (3 << 10)
	64	#define HCR_BSU_IS (UL(1) << 10)
	65	#define HCR_FB (UL(1) << 9)
7b17145e	66	#define HCR_VSE (UL(1) << 8)
0369f6a3 MZ	67	#define HCR_VI (UL(1) << 7)
	68	#define HCR_VF (UL(1) << 6)
	69	#define HCR_AMO (UL(1) << 5)
	70	#define HCR_IMO (UL(1) << 4)
	71	#define HCR_FMO (UL(1) << 3)
	72	#define HCR_PTW (UL(1) << 2)
	73	#define HCR_SWIO (UL(1) << 1)
	74	#define HCR_VM (UL(1) << 0)
2d701243	75	#define HCR_RES0 ((UL(1) << 48) \| (UL(1) << 39))
0369f6a3 MZ	76
	77	/*
	78	* The bits we set in HCR:
cc33c4e2	79	* TLOR: Trap LORegion register accesses
ef769e32	80	* RW: 64bit by default, can be overridden for 32bit VMs
dabb1667	81	* TACR: Trap ACTLR
0369f6a3 MZ	82	* TSC: Trap SMC
0369f6a3 MZ	83	* TSW: Trap cache operations by set/way
d241aac7	84	* TWE: Trap WFE
0369f6a3 MZ	85	* TWI: Trap WFI
	86	* TIDCP: Trap L2CTLR/L2ECTLR
	87	* BSU_IS: Upgrade barriers to the inner shareable domain
ad14c192	88	* FB: Force broadcast of all maintenance operations
0369f6a3 MZ	89	* AMO: Override CPSR.A and enable signaling with VA
	90	* IMO: Override CPSR.I and enable signaling with VI
	91	* FMO: Override CPSR.F and enable signaling with VF
	92	* SWIO: Turn set/way invalidates into set/way clean+invalidate
71a7f8cb	93	* PTW: Take a stage2 fault if a stage1 walk steps in device memory
fd1264c4	94	* TID3: Trap EL1 reads of group 3 ID registers
8cc6deda	95	* TID2: Trap CTR_EL0, CCSIDR2_EL1, CLIDR_EL1, and CSSELR_EL1
0369f6a3	96	*/
d241aac7	97	#define HCR_GUEST_FLAGS (HCR_TSC \| HCR_TSW \| HCR_TWE \| HCR_TWI \| HCR_VM \| \
dabb1667	98	HCR_BSU_IS \| HCR_FB \| HCR_TACR \| \
35a84dec	99	HCR_AMO \| HCR_SWIO \| HCR_TIDCP \| HCR_RW \| HCR_TLOR \| \
c876c3f1	100	HCR_FMO \| HCR_IMO \| HCR_PTW \| HCR_TID3)
3b714d24	101	#define HCR_HOST_NVHE_FLAGS (HCR_RW \| HCR_API \| HCR_APK \| HCR_ATA)
b93c17c4	102	#define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS \| HCR_TSC)
68908bf7	103	#define HCR_HOST_VHE_FLAGS (HCR_RW \| HCR_TGE \| HCR_E2H)
0369f6a3	104
e0bb80c6 KM	105	#define HCRX_GUEST_FLAGS \
	106	(HCRX_EL2_SMPME \| HCRX_EL2_TCR2En \| \
	107	(cpus_have_final_cap(ARM64_HAS_MOPS) ? (HCRX_EL2_MSCEn \| HCRX_EL2_MCE2) : 0))
7df71709	108	#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn \| HCRX_EL2_TCR2En)
af94aad4	109
0369f6a3	110	/* TCR_EL2 Registers bits */
d4fbbb26	111	#define TCR_EL2_DS (1UL << 32)
1f80d150	112	#define TCR_EL2_RES1 ((1U << 31) \| (1 << 23))
a563f759 SP	113	#define TCR_EL2_TBI (1 << 20)
	114	#define TCR_EL2_PS_SHIFT 16
	115	#define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT)
	116	#define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT)
	117	#define TCR_EL2_TG0_MASK TCR_TG0_MASK
	118	#define TCR_EL2_SH0_MASK TCR_SH0_MASK
	119	#define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
	120	#define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
	121	#define TCR_EL2_T0SZ_MASK 0x3f
	122	#define TCR_EL2_MASK (TCR_EL2_TG0_MASK \| TCR_EL2_SH0_MASK \| \
	123	TCR_EL2_ORGN0_MASK \| TCR_EL2_IRGN0_MASK \| TCR_EL2_T0SZ_MASK)
0369f6a3	124
0369f6a3	125	/* VTCR_EL2 Registers bits */
d4fbbb26	126	#define VTCR_EL2_DS TCR_EL2_DS
df655b75	127	#define VTCR_EL2_RES1 (1U << 31)
06485053 CM	128	#define VTCR_EL2_HD (1 << 22)
06485053 CM	129	#define VTCR_EL2_HA (1 << 21)
b2df44ff	130	#define VTCR_EL2_PS_SHIFT TCR_EL2_PS_SHIFT
a563f759 SP	131	#define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK
	132	#define VTCR_EL2_TG0_MASK TCR_TG0_MASK
	133	#define VTCR_EL2_TG0_4K TCR_TG0_4K
02e0b760	134	#define VTCR_EL2_TG0_16K TCR_TG0_16K
a563f759 SP	135	#define VTCR_EL2_TG0_64K TCR_TG0_64K
	136	#define VTCR_EL2_SH0_MASK TCR_SH0_MASK
	137	#define VTCR_EL2_SH0_INNER TCR_SH0_INNER
	138	#define VTCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
	139	#define VTCR_EL2_ORGN0_WBWA TCR_ORGN0_WBWA
	140	#define VTCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
	141	#define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA
	142	#define VTCR_EL2_SL0_SHIFT 6
	143	#define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT)
0369f6a3	144	#define VTCR_EL2_T0SZ_MASK 0x3f
cb678d60 SP	145	#define VTCR_EL2_VS_SHIFT 19
	146	#define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT)
	147	#define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT)
0369f6a3	148
b2df44ff SP	149	#define VTCR_EL2_T0SZ(x) TCR_T0SZ(x)
b2df44ff SP	150
dbff124e JS	151	/*
	152	* We configure the Stage-2 page tables to always restrict the IPA space to be
	153	* 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are
	154	* not known to exist and will break with this configuration.
	155	*
315775ff	156	* The VTCR_EL2 is configured per VM and is initialised in kvm_init_stage2_mmu.
84ed7412	157	*
dbff124e	158	* Note that when using 4K pages, we concatenate two first level page tables
02e0b760	159	* together. With 16K pages, we concatenate 16 first level page tables.
dbff124e	160	*
dbff124e	161	*/
acd05010	162
acd05010 SP	163	#define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER \| VTCR_EL2_ORGN0_WBWA \| \
	164	VTCR_EL2_IRGN0_WBWA \| VTCR_EL2_RES1)
	165
0369f6a3	166	/*
7e813045 SP	167	* VTCR_EL2:SL0 indicates the entry level for Stage2 translation.
	168	* Interestingly, it depends on the page size.
	169	* See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a
	170	*
	171	* -----------------------------------------
	172	* \| Entry level \| 4K \| 16K/64K \|
	173	* ------------------------------------------
	174	* \| Level: 0 \| 2 \| - \|
	175	* ------------------------------------------
	176	* \| Level: 1 \| 1 \| 2 \|
	177	* ------------------------------------------
	178	* \| Level: 2 \| 0 \| 1 \|
	179	* ------------------------------------------
	180	* \| Level: 3 \| - \| 0 \|
	181	* ------------------------------------------
	182	*
	183	* The table roughly translates to :
	184	*
	185	* SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level
	186	*
	187	* Where TGRAN_SL0_BASE is a magic number depending on the page size:
	188	* TGRAN_SL0_BASE(4K) = 2
	189	* TGRAN_SL0_BASE(16K) = 3
	190	* TGRAN_SL0_BASE(64K) = 3
	191	* provided we take care of ruling out the unsupported cases and
	192	* Entry_Level = 4 - Number_of_levels.
	193	*
0369f6a3	194	*/
7e813045 SP	195	#ifdef CONFIG_ARM64_64K_PAGES
	196
	197	#define VTCR_EL2_TGRAN VTCR_EL2_TG0_64K
	198	#define VTCR_EL2_TGRAN_SL0_BASE 3UL
	199
02e0b760	200	#elif defined(CONFIG_ARM64_16K_PAGES)
7e813045 SP	201
	202	#define VTCR_EL2_TGRAN VTCR_EL2_TG0_16K
	203	#define VTCR_EL2_TGRAN_SL0_BASE 3UL
	204
02e0b760	205	#else /* 4K */
7e813045 SP	206
	207	#define VTCR_EL2_TGRAN VTCR_EL2_TG0_4K
	208	#define VTCR_EL2_TGRAN_SL0_BASE 2UL
	209
0369f6a3 MZ	210	#endif
0369f6a3 MZ	211
7e813045 SP	212	#define VTCR_EL2_LVLS_TO_SL0(levels) \
	213	((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT)
	214	#define VTCR_EL2_SL0_TO_LVLS(sl0) \
	215	((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE)
	216	#define VTCR_EL2_LVLS(vtcr) \
	217	VTCR_EL2_SL0_TO_LVLS(((vtcr) & VTCR_EL2_SL0_MASK) >> VTCR_EL2_SL0_SHIFT)
	218
	219	#define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS \| VTCR_EL2_TGRAN)
13ac4bbc SP	220	#define VTCR_EL2_IPA(vtcr) (64 - ((vtcr) & VTCR_EL2_T0SZ_MASK))
13ac4bbc SP	221
59558330 SP	222	/*
	223	* ARM VMSAv8-64 defines an algorithm for finding the translation table
	224	* descriptors in section D4.2.8 in ARM DDI 0487C.a.
	225	*
	226	* The algorithm defines the expectations on the translation table
	227	* addresses for each level, based on PAGE_SIZE, entry level
	228	* and the translation table size (T0SZ). The variable "x" in the
	229	* algorithm determines the alignment of a table base address at a given
	230	* level and thus determines the alignment of VTTBR:BADDR for stage2
	231	* page table entry level.
	232	* Since the number of bits resolved at the entry level could vary
	233	* depending on the T0SZ, the value of "x" is defined based on a
	234	* Magic constant for a given PAGE_SIZE and Entry Level. The
	235	* intermediate levels must be always aligned to the PAGE_SIZE (i.e,
	236	* x = PAGE_SHIFT).
	237	*
	238	* The value of "x" for entry level is calculated as :
	239	* x = Magic_N - T0SZ
	240	*
	241	* where Magic_N is an integer depending on the page size and the entry
	242	* level of the page table as below:
	243	*
	244	* --------------------------------------------
	245	* \| Entry level \| 4K 16K 64K \|
	246	* --------------------------------------------
	247	* \| Level: 0 (4 levels) \| 28 \| - \| - \|
	248	* --------------------------------------------
	249	* \| Level: 1 (3 levels) \| 37 \| 31 \| 25 \|
	250	* --------------------------------------------
	251	* \| Level: 2 (2 levels) \| 46 \| 42 \| 38 \|
	252	* --------------------------------------------
	253	* \| Level: 3 (1 level) \| - \| 53 \| 51 \|
	254	* --------------------------------------------
	255	*
	256	* We have a magic formula for the Magic_N below:
	257	*
	258	* Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels)
	259	*
	260	* where Number_of_levels = (4 - Level). We are only interested in the
	261	* value for Entry_Level for the stage2 page table.
	262	*
	263	* So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows:
	264	*
	265	* x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT)
	266	* = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels)
	267	*
	268	* Here is one way to explain the Magic Formula:
	269	*
	270	* x = log2(Size_of_Entry_Level_Table)
	271	*
	272	* Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another
	273	* PAGE_SHIFT bits in the PTE, we have :
	274	*
	275	* Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT)
	276	* = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3
	277	* where n = number of levels, and since each pointer is 8bytes, we have:
	278	*
	279	* x = Bits_Entry_Level + 3
	280	* = IPA_SHIFT - (PAGE_SHIFT - 3) * n
	281	*
	282	* The only constraint here is that, we have to find the number of page table
	283	* levels for a given IPA size (which we do, see stage2_pt_levels())
	284	*/
	285	#define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3)))
acd05010	286
ab510027	287	#define VTTBR_CNP_BIT (UL(1))
286fb1cc	288	#define VTTBR_VMID_SHIFT (UL(48))
20475f78	289	#define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
0369f6a3 MZ	290
0369f6a3 MZ	291	/* Hyp System Trap Register */
0369f6a3 MZ	292	#define HSTR_EL2_T(x) (1 << x)
0369f6a3 MZ	293
edce2292	294	/* Hyp Coprocessor Trap Register Shifts */
33c76a0b MS	295	#define CPTR_EL2_TFP_SHIFT 10
33c76a0b MS	296
0369f6a3	297	/* Hyp Coprocessor Trap Register */
1f80d150	298	#define CPTR_EL2_TCPAC (1U << 31)
4fcdf106	299	#define CPTR_EL2_TAM (1 << 30)
0369f6a3	300	#define CPTR_EL2_TTA (1 << 20)
b4adc83b	301	#define CPTR_EL2_TSM (1 << 12)
33c76a0b	302	#define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT)
67236564	303	#define CPTR_EL2_TZ (1 << 8)
dabb1667	304	#define CPTR_NVHE_EL2_RES1 0x000032ff /* known RES1 bits in CPTR_EL2 (nVHE) */
2d701243 FT	305	#define CPTR_NVHE_EL2_RES0 (GENMASK(63, 32) \| \
	306	GENMASK(29, 21) \| \
	307	GENMASK(19, 14) \| \
	308	BIT(11))
0369f6a3 MZ	309
0369f6a3 MZ	310	/* Hyp Debug Configuration Register bits */
a1319260 SP	311	#define MDCR_EL2_E2TB_MASK (UL(0x3))
a1319260 SP	312	#define MDCR_EL2_E2TB_SHIFT (UL(24))
2d701243 FT	313	#define MDCR_EL2_HPMFZS (UL(1) << 36)
	314	#define MDCR_EL2_HPMFZO (UL(1) << 29)
	315	#define MDCR_EL2_MTPME (UL(1) << 28)
	316	#define MDCR_EL2_TDCC (UL(1) << 27)
53868390	317	#define MDCR_EL2_HLP (UL(1) << 26)
2d701243	318	#define MDCR_EL2_HCCD (UL(1) << 23)
d6c850dd	319	#define MDCR_EL2_TTRF (UL(1) << 19)
2d701243	320	#define MDCR_EL2_HPMD (UL(1) << 17)
d6c850dd	321	#define MDCR_EL2_TPMS (UL(1) << 14)
f85279b4 WD	322	#define MDCR_EL2_E2PB_MASK (UL(0x3))
f85279b4 WD	323	#define MDCR_EL2_E2PB_SHIFT (UL(12))
d6c850dd FT	324	#define MDCR_EL2_TDRA (UL(1) << 11)
	325	#define MDCR_EL2_TDOSA (UL(1) << 10)
	326	#define MDCR_EL2_TDA (UL(1) << 9)
	327	#define MDCR_EL2_TDE (UL(1) << 8)
	328	#define MDCR_EL2_HPME (UL(1) << 7)
	329	#define MDCR_EL2_TPM (UL(1) << 6)
	330	#define MDCR_EL2_TPMCR (UL(1) << 5)
	331	#define MDCR_EL2_HPMN_MASK (UL(0x1F))
2d701243 FT	332	#define MDCR_EL2_RES0 (GENMASK(63, 37) \| \
	333	GENMASK(35, 30) \| \
	334	GENMASK(25, 24) \| \
	335	GENMASK(22, 20) \| \
	336	BIT(18) \| \
	337	GENMASK(16, 15))
0369f6a3	338
e930694e MZ	339	/*
	340	* FGT register definitions
	341	*
	342	* RES0 and polarity masks as of DDI0487J.a, to be updated as needed.
	343	* We're not using the generated masks as they are usually ahead of
	344	* the published ARM ARM, which we use as a reference.
	345	*
	346	* Once we get to a point where the two describe the same thing, we'll
	347	* merge the definitions. One day.
	348	*/
9ff67dd2	349	#define __HFGRTR_EL2_RES0 HFGxTR_EL2_RES0
e930694e	350	#define __HFGRTR_EL2_MASK GENMASK(49, 0)
5f6bd3f3	351	#define __HFGRTR_EL2_nMASK ~(__HFGRTR_EL2_RES0 \| __HFGRTR_EL2_MASK)
e930694e	352
9ff67dd2 FT	353	/*
	354	* The HFGWTR bits are a subset of HFGRTR bits. To ensure we don't miss any
	355	* future additions, define __HFGWTR* macros relative to __HFGRTR* ones.
	356	*/
	357	#define __HFGRTR_ONLY_MASK (BIT(46) \| BIT(42) \| BIT(40) \| BIT(28) \| \
	358	GENMASK(26, 25) \| BIT(21) \| BIT(18) \| \
e930694e	359	GENMASK(15, 14) \| GENMASK(10, 9) \| BIT(2))
9ff67dd2 FT	360	#define __HFGWTR_EL2_RES0 (__HFGRTR_EL2_RES0 \| __HFGRTR_ONLY_MASK)
9ff67dd2 FT	361	#define __HFGWTR_EL2_MASK (__HFGRTR_EL2_MASK & ~__HFGRTR_ONLY_MASK)
5f6bd3f3	362	#define __HFGWTR_EL2_nMASK ~(__HFGWTR_EL2_RES0 \| __HFGWTR_EL2_MASK)
9ff67dd2 FT	363
9ff67dd2 FT	364	#define __HFGITR_EL2_RES0 HFGITR_EL2_RES0
fc04838f	365	#define __HFGITR_EL2_MASK (BIT(62) \| BIT(60) \| GENMASK(54, 0))
5f6bd3f3	366	#define __HFGITR_EL2_nMASK ~(__HFGITR_EL2_RES0 \| __HFGITR_EL2_MASK)
039f9f12	367
9ff67dd2	368	#define __HDFGRTR_EL2_RES0 HDFGRTR_EL2_RES0
fc04838f FT	369	#define __HDFGRTR_EL2_MASK (BIT(63) \| GENMASK(58, 50) \| GENMASK(48, 43) \| \
	370	GENMASK(41, 40) \| GENMASK(37, 22) \| \
	371	GENMASK(19, 9) \| GENMASK(7, 0))
5f6bd3f3	372	#define __HDFGRTR_EL2_nMASK ~(__HDFGRTR_EL2_RES0 \| __HDFGRTR_EL2_MASK)
d0be0b2e	373
9ff67dd2	374	#define __HDFGWTR_EL2_RES0 HDFGWTR_EL2_RES0
fc04838f FT	375	#define __HDFGWTR_EL2_MASK (GENMASK(57, 52) \| GENMASK(50, 48) \| \
	376	GENMASK(46, 44) \| GENMASK(42, 41) \| \
	377	GENMASK(37, 35) \| GENMASK(33, 31) \| \
	378	GENMASK(29, 23) \| GENMASK(21, 10) \| \
	379	GENMASK(8, 7) \| GENMASK(5, 0))
5f6bd3f3	380	#define __HDFGWTR_EL2_nMASK ~(__HDFGWTR_EL2_RES0 \| __HDFGWTR_EL2_MASK)
d0be0b2e	381
9ff67dd2	382	#define __HAFGRTR_EL2_RES0 HAFGRTR_EL2_RES0
f9d6ed02	383	#define __HAFGRTR_EL2_MASK (GENMASK(49, 17) \| GENMASK(4, 0))
5f6bd3f3	384	#define __HAFGRTR_EL2_nMASK ~(__HAFGRTR_EL2_RES0 \| __HAFGRTR_EL2_MASK)
d0be0b2e	385
03fb54d0	386	/* Similar definitions for HCRX_EL2 */
9ff67dd2	387	#define __HCRX_EL2_RES0 HCRX_EL2_RES0
fc04838f	388	#define __HCRX_EL2_MASK (BIT(6))
5f6bd3f3	389	#define __HCRX_EL2_nMASK ~(__HCRX_EL2_RES0 \| __HCRX_EL2_MASK)
03fb54d0	390
0369f6a3	391	/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
286fb1cc	392	#define HPFAR_MASK (~UL(0xf))
bc1d7de8 SP	393	/*
	394	* We have
	395	* PAR [PA_Shift - 1 : 12] = PA [PA_Shift - 1 : 12]
	396	* HPFAR [PA_Shift - 9 : 4] = FIPA [PA_Shift - 1 : 12]
a0d37784 RR	397	*
	398	* Always assume 52 bit PA since at this point, we don't know how many PA bits
	399	* the page table has been set up for. This should be safe since unused address
	400	* bits in PAR are res0.
bc1d7de8 SP	401	*/
bc1d7de8 SP	402	#define PAR_TO_HPFAR(par) \
a0d37784	403	(((par) & GENMASK_ULL(52 - 1, 12)) >> 8)
0369f6a3	404
b5905dc1 CD	405	#define ECN(x) { ESR_ELx_EC_##x, #x }
	406
	407	#define kvm_arm_exception_class \
	408	ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \
6701c619 ZY	409	ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(PAC), ECN(CP14_64), \
	410	ECN(SVC64), ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(SVE), \
	411	ECN(IMP_DEF), ECN(IABT_LOW), ECN(IABT_CUR), \
	412	ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
b5905dc1 CD	413	ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \
	414	ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \
	415	ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \
6898a55c	416	ECN(BKPT32), ECN(VECTOR32), ECN(BRK64), ECN(ERET)
b5905dc1	417
75c76ab5	418	#define CPACR_EL1_TTA (1 << 28)
32876224	419
47f3a2fc JL	420	#define kvm_mode_names \
	421	{ PSR_MODE_EL0t, "EL0t" }, \
	422	{ PSR_MODE_EL1t, "EL1t" }, \
	423	{ PSR_MODE_EL1h, "EL1h" }, \
	424	{ PSR_MODE_EL2t, "EL2t" }, \
	425	{ PSR_MODE_EL2h, "EL2h" }, \
	426	{ PSR_MODE_EL3t, "EL3t" }, \
	427	{ PSR_MODE_EL3h, "EL3h" }, \
	428	{ PSR_AA32_MODE_USR, "32-bit USR" }, \
	429	{ PSR_AA32_MODE_FIQ, "32-bit FIQ" }, \
	430	{ PSR_AA32_MODE_IRQ, "32-bit IRQ" }, \
	431	{ PSR_AA32_MODE_SVC, "32-bit SVC" }, \
	432	{ PSR_AA32_MODE_ABT, "32-bit ABT" }, \
	433	{ PSR_AA32_MODE_HYP, "32-bit HYP" }, \
	434	{ PSR_AA32_MODE_UND, "32-bit UND" }, \
	435	{ PSR_AA32_MODE_SYS, "32-bit SYS" }
	436
0369f6a3	437	#endif /* __ARM64_KVM_ARM_H__ */