[linux-2.6-block.git] / arch / arm64 / include / asm / io.h

/*
 * Based on arch/arm/include/asm/io.h
 *
 * Copyright (C) 1996-2000 Russell King
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __ASM_IO_H
#define __ASM_IO_H

#ifdef __KERNEL__

#include <linux/types.h>
#include <linux/blk_types.h>

#include <asm/byteorder.h>
#include <asm/barrier.h>
#include <asm/pgtable.h>
#include <asm/early_ioremap.h>

#include <xen/xen.h>

/*
 * Generic IO read/write.  These perform native-endian accesses.
 */
static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
{
	asm volatile("strb %w0, [%1]" : : "r" (val), "r" (addr));
}

static inline void __raw_writew(u16 val, volatile void __iomem *addr)
{
	asm volatile("strh %w0, [%1]" : : "r" (val), "r" (addr));
}

static inline void __raw_writel(u32 val, volatile void __iomem *addr)
{
	asm volatile("str %w0, [%1]" : : "r" (val), "r" (addr));
}

static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
{
	asm volatile("str %0, [%1]" : : "r" (val), "r" (addr));
}

static inline u8 __raw_readb(const volatile void __iomem *addr)
{
	u8 val;
	asm volatile("ldrb %w0, [%1]" : "=r" (val) : "r" (addr));
	return val;
}

static inline u16 __raw_readw(const volatile void __iomem *addr)
{
	u16 val;
	asm volatile("ldrh %w0, [%1]" : "=r" (val) : "r" (addr));
	return val;
}

static inline u32 __raw_readl(const volatile void __iomem *addr)
{
	u32 val;
	asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr));
	return val;
}

static inline u64 __raw_readq(const volatile void __iomem *addr)
{
	u64 val;
	asm volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr));
	return val;
}

/* IO barriers */
#define __iormb()		rmb()
#define __iowmb()		wmb()

#define mmiowb()		do { } while (0)

/*
 * Relaxed I/O memory access primitives. These follow the Device memory
 * ordering rules but do not guarantee any ordering relative to Normal memory
 * accesses.
 */
#define readb_relaxed(c)	({ u8  __v = __raw_readb(c); __v; })
#define readw_relaxed(c)	({ u16 __v = le16_to_cpu((__force __le16)__raw_readw(c)); __v; })
#define readl_relaxed(c)	({ u32 __v = le32_to_cpu((__force __le32)__raw_readl(c)); __v; })
#define readq_relaxed(c)	({ u64 __v = le64_to_cpu((__force __le64)__raw_readq(c)); __v; })

#define writeb_relaxed(v,c)	((void)__raw_writeb((v),(c)))
#define writew_relaxed(v,c)	((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
#define writel_relaxed(v,c)	((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
#define writeq_relaxed(v,c)	((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))

/*
 * I/O memory access primitives. Reads are ordered relative to any
 * following Normal memory access. Writes are ordered relative to any prior
 * Normal memory access.
 */
#define readb(c)		({ u8  __v = readb_relaxed(c); __iormb(); __v; })
#define readw(c)		({ u16 __v = readw_relaxed(c); __iormb(); __v; })
#define readl(c)		({ u32 __v = readl_relaxed(c); __iormb(); __v; })
#define readq(c)		({ u64 __v = readq_relaxed(c); __iormb(); __v; })

#define writeb(v,c)		({ __iowmb(); writeb_relaxed((v),(c)); })
#define writew(v,c)		({ __iowmb(); writew_relaxed((v),(c)); })
#define writel(v,c)		({ __iowmb(); writel_relaxed((v),(c)); })
#define writeq(v,c)		({ __iowmb(); writeq_relaxed((v),(c)); })

/*
 *  I/O port access primitives.
 */
#define arch_has_dev_port()	(1)
#define IO_SPACE_LIMIT		(SZ_32M - 1)
#define PCI_IOBASE		((void __iomem *)(MODULES_VADDR - SZ_32M))

static inline u8 inb(unsigned long addr)
{
	return readb(addr + PCI_IOBASE);
}

static inline u16 inw(unsigned long addr)
{
	return readw(addr + PCI_IOBASE);
}

static inline u32 inl(unsigned long addr)
{
	return readl(addr + PCI_IOBASE);
}

static inline void outb(u8 b, unsigned long addr)
{
	writeb(b, addr + PCI_IOBASE);
}

static inline void outw(u16 b, unsigned long addr)
{
	writew(b, addr + PCI_IOBASE);
}

static inline void outl(u32 b, unsigned long addr)
{
	writel(b, addr + PCI_IOBASE);
}

#define inb_p(addr)	inb(addr)
#define inw_p(addr)	inw(addr)
#define inl_p(addr)	inl(addr)

#define outb_p(x, addr)	outb((x), (addr))
#define outw_p(x, addr)	outw((x), (addr))
#define outl_p(x, addr)	outl((x), (addr))

static inline void insb(unsigned long addr, void *buffer, int count)
{
	u8 *buf = buffer;
	while (count--)
		*buf++ = __raw_readb(addr + PCI_IOBASE);
}

static inline void insw(unsigned long addr, void *buffer, int count)
{
	u16 *buf = buffer;
	while (count--)
		*buf++ = __raw_readw(addr + PCI_IOBASE);
}

static inline void insl(unsigned long addr, void *buffer, int count)
{
	u32 *buf = buffer;
	while (count--)
		*buf++ = __raw_readl(addr + PCI_IOBASE);
}

static inline void outsb(unsigned long addr, const void *buffer, int count)
{
	const u8 *buf = buffer;
	while (count--)
		__raw_writeb(*buf++, addr + PCI_IOBASE);
}

static inline void outsw(unsigned long addr, const void *buffer, int count)
{
	const u16 *buf = buffer;
	while (count--)
		__raw_writew(*buf++, addr + PCI_IOBASE);
}

static inline void outsl(unsigned long addr, const void *buffer, int count)
{
	const u32 *buf = buffer;
	while (count--)
		__raw_writel(*buf++, addr + PCI_IOBASE);
}

#define insb_p(port,to,len)	insb(port,to,len)
#define insw_p(port,to,len)	insw(port,to,len)
#define insl_p(port,to,len)	insl(port,to,len)

#define outsb_p(port,from,len)	outsb(port,from,len)
#define outsw_p(port,from,len)	outsw(port,from,len)
#define outsl_p(port,from,len)	outsl(port,from,len)

/*
 * String version of I/O memory access operations.
 */
extern void __memcpy_fromio(void *, const volatile void __iomem *, size_t);
extern void __memcpy_toio(volatile void __iomem *, const void *, size_t);
extern void __memset_io(volatile void __iomem *, int, size_t);

#define memset_io(c,v,l)	__memset_io((c),(v),(l))
#define memcpy_fromio(a,c,l)	__memcpy_fromio((a),(c),(l))
#define memcpy_toio(c,a,l)	__memcpy_toio((c),(a),(l))

/*
 * I/O memory mapping functions.
 */
extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot);
extern void __iounmap(volatile void __iomem *addr);
extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);

#define ioremap(addr, size)		__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
#define ioremap_nocache(addr, size)	__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
#define ioremap_wc(addr, size)		__ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
#define iounmap				__iounmap

#define ARCH_HAS_IOREMAP_WC
#include <asm-generic/iomap.h>

/*
 * More restrictive address range checking than the default implementation
 * (PHYS_OFFSET and PHYS_MASK taken into account).
 */
#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
extern int valid_phys_addr_range(unsigned long addr, size_t size);
extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);

extern int devmem_is_allowed(unsigned long pfn);

/*
 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 * access
 */
#define xlate_dev_mem_ptr(p)	__va(p)

/*
 * Convert a virtual cached pointer to an uncached pointer
 */
#define xlate_dev_kmem_ptr(p)	p

struct bio_vec;
extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
				      const struct bio_vec *vec2);
#define BIOVEC_PHYS_MERGEABLE(vec1, vec2)				\
	(__BIOVEC_PHYS_MERGEABLE(vec1, vec2) &&				\
	 (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))

#endif	/* __KERNEL__ */
#endif	/* __ASM_IO_H */
Commit	Line	Data
fc47897d CM	1	/*
	2	* Based on arch/arm/include/asm/io.h
	3	*
	4	* Copyright (C) 1996-2000 Russell King
	5	* Copyright (C) 2012 ARM Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19	#ifndef __ASM_IO_H
	20	#define __ASM_IO_H
	21
	22	#ifdef __KERNEL__
	23
	24	#include <linux/types.h>
3d1975b5	25	#include <linux/blk_types.h>
fc47897d CM	26
	27	#include <asm/byteorder.h>
	28	#include <asm/barrier.h>
	29	#include <asm/pgtable.h>
bf4b558e	30	#include <asm/early_ioremap.h>
fc47897d	31
3d1975b5 SS	32	#include <xen/xen.h>
3d1975b5 SS	33
fc47897d CM	34	/*
	35	* Generic IO read/write. These perform native-endian accesses.
	36	*/
	37	static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
	38	{
	39	asm volatile("strb %w0, [%1]" : : "r" (val), "r" (addr));
	40	}
	41
	42	static inline void __raw_writew(u16 val, volatile void __iomem *addr)
	43	{
	44	asm volatile("strh %w0, [%1]" : : "r" (val), "r" (addr));
	45	}
	46
	47	static inline void __raw_writel(u32 val, volatile void __iomem *addr)
	48	{
	49	asm volatile("str %w0, [%1]" : : "r" (val), "r" (addr));
	50	}
	51
	52	static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
	53	{
	54	asm volatile("str %0, [%1]" : : "r" (val), "r" (addr));
	55	}
	56
	57	static inline u8 __raw_readb(const volatile void __iomem *addr)
	58	{
	59	u8 val;
	60	asm volatile("ldrb %w0, [%1]" : "=r" (val) : "r" (addr));
	61	return val;
	62	}
	63
	64	static inline u16 __raw_readw(const volatile void __iomem *addr)
	65	{
	66	u16 val;
	67	asm volatile("ldrh %w0, [%1]" : "=r" (val) : "r" (addr));
	68	return val;
	69	}
	70
	71	static inline u32 __raw_readl(const volatile void __iomem *addr)
	72	{
	73	u32 val;
	74	asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr));
	75	return val;
	76	}
	77
	78	static inline u64 __raw_readq(const volatile void __iomem *addr)
	79	{
	80	u64 val;
	81	asm volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr));
	82	return val;
	83	}
	84
	85	/* IO barriers */
	86	#define __iormb() rmb()
	87	#define __iowmb() wmb()
	88
	89	#define mmiowb() do { } while (0)
	90
	91	/*
	92	* Relaxed I/O memory access primitives. These follow the Device memory
	93	* ordering rules but do not guarantee any ordering relative to Normal memory
	94	* accesses.
	95	*/
	96	#define readb_relaxed(c) ({ u8 __v = __raw_readb(c); __v; })
	97	#define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16)__raw_readw(c)); __v; })
98	#define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl(c)); __v; })
12f88398	99	#define readq_relaxed(c) ({ u64 __v = le64_to_cpu((__force __le64)__raw_readq(c)); __v; })
fc47897d CM	100
	101	#define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c)))
	102	#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
	103	#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
12f88398	104	#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
fc47897d CM	105
	106	/*
	107	* I/O memory access primitives. Reads are ordered relative to any
	108	* following Normal memory access. Writes are ordered relative to any prior
	109	* Normal memory access.
	110	*/
	111	#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
	112	#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
	113	#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
12f88398	114	#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
fc47897d CM	115
	116	#define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); })
	117	#define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); })
	118	#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); })
12f88398	119	#define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c)); })
fc47897d CM	120
	121	/*
	122	* I/O port access primitives.
	123	*/
d1e6dc91 LD	124	#define arch_has_dev_port() (1)
d1e6dc91 LD	125	#define IO_SPACE_LIMIT (SZ_32M - 1)
22bd1c91	126	#define PCI_IOBASE ((void __iomem *)(MODULES_VADDR - SZ_32M))
fc47897d CM	127
	128	static inline u8 inb(unsigned long addr)
	129	{
	130	return readb(addr + PCI_IOBASE);
	131	}
	132
	133	static inline u16 inw(unsigned long addr)
	134	{
	135	return readw(addr + PCI_IOBASE);
	136	}
	137
	138	static inline u32 inl(unsigned long addr)
	139	{
	140	return readl(addr + PCI_IOBASE);
	141	}
	142
	143	static inline void outb(u8 b, unsigned long addr)
	144	{
	145	writeb(b, addr + PCI_IOBASE);
	146	}
	147
	148	static inline void outw(u16 b, unsigned long addr)
	149	{
	150	writew(b, addr + PCI_IOBASE);
	151	}
	152
	153	static inline void outl(u32 b, unsigned long addr)
	154	{
	155	writel(b, addr + PCI_IOBASE);
	156	}
	157
	158	#define inb_p(addr) inb(addr)
	159	#define inw_p(addr) inw(addr)
	160	#define inl_p(addr) inl(addr)
	161
	162	#define outb_p(x, addr) outb((x), (addr))
	163	#define outw_p(x, addr) outw((x), (addr))
	164	#define outl_p(x, addr) outl((x), (addr))
	165
	166	static inline void insb(unsigned long addr, void *buffer, int count)
	167	{
	168	u8 *buf = buffer;
	169	while (count--)
	170	*buf++ = __raw_readb(addr + PCI_IOBASE);
	171	}
	172
	173	static inline void insw(unsigned long addr, void *buffer, int count)
	174	{
	175	u16 *buf = buffer;
	176	while (count--)
	177	*buf++ = __raw_readw(addr + PCI_IOBASE);
	178	}
	179
	180	static inline void insl(unsigned long addr, void *buffer, int count)
	181	{
	182	u32 *buf = buffer;
	183	while (count--)
	184	*buf++ = __raw_readl(addr + PCI_IOBASE);
	185	}
	186
	187	static inline void outsb(unsigned long addr, const void *buffer, int count)
	188	{
	189	const u8 *buf = buffer;
	190	while (count--)
191	__raw_writeb(*buf++, addr + PCI_IOBASE);
192	}
193
194	static inline void outsw(unsigned long addr, const void *buffer, int count)
195	{
196	const u16 *buf = buffer;
197	while (count--)
198	__raw_writew(*buf++, addr + PCI_IOBASE);
199	}
200
201	static inline void outsl(unsigned long addr, const void *buffer, int count)
202	{
203	const u32 *buf = buffer;
204	while (count--)
205	__raw_writel(*buf++, addr + PCI_IOBASE);
206	}
207
208	#define insb_p(port,to,len) insb(port,to,len)
209	#define insw_p(port,to,len) insw(port,to,len)
210	#define insl_p(port,to,len) insl(port,to,len)
211
212	#define outsb_p(port,from,len) outsb(port,from,len)
213	#define outsw_p(port,from,len) outsw(port,from,len)
214	#define outsl_p(port,from,len) outsl(port,from,len)
215
216	/*
217	* String version of I/O memory access operations.
218	*/
219	extern void __memcpy_fromio(void , const volatile void __iomem , size_t);
220	extern void __memcpy_toio(volatile void __iomem , const void , size_t);
221	extern void __memset_io(volatile void __iomem *, int, size_t);
222
223	#define memset_io(c,v,l) __memset_io((c),(v),(l))
224	#define memcpy_fromio(a,c,l) __memcpy_fromio((a),(c),(l))
225	#define memcpy_toio(c,a,l) __memcpy_toio((c),(a),(l))
226
227	/*
228	* I/O memory mapping functions.
229	*/
230	extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot);
231	extern void __iounmap(volatile void __iomem *addr);
c04e8e2f	232	extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);
fc47897d	233
489f781a CM	234	#define ioremap(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
	235	#define ioremap_nocache(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
	236	#define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
fc47897d CM	237	#define iounmap __iounmap
	238
	239	#define ARCH_HAS_IOREMAP_WC
	240	#include <asm-generic/iomap.h>
	241
	242	/*
	243	* More restrictive address range checking than the default implementation
	244	* (PHYS_OFFSET and PHYS_MASK taken into account).
	245	*/
	246	#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
	247	extern int valid_phys_addr_range(unsigned long addr, size_t size);
	248	extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
	249
	250	extern int devmem_is_allowed(unsigned long pfn);
	251
	252	/*
	253	* Convert a physical pointer to a virtual kernel pointer for /dev/mem
	254	* access
	255	*/
	256	#define xlate_dev_mem_ptr(p) __va(p)
	257
	258	/*
	259	* Convert a virtual cached pointer to an uncached pointer
	260	*/
	261	#define xlate_dev_kmem_ptr(p) p
	262
ffc555be	263	struct bio_vec;
3d1975b5 SS	264	extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
	265	const struct bio_vec *vec2);
	266	#define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \
	267	(__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \
	268	(!xen_domain() \|\| xen_biovec_phys_mergeable(vec1, vec2)))
	269
fc47897d CM	270	#endif /* __KERNEL__ */
fc47897d CM	271	#endif /* __ASM_IO_H */