projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| b11a64a4 JL |
1 | /* |
| 2 | * Copyright (C) 2013 Huawei Ltd. | |
| 3 | * Author: Jiang Liu <liuj97@gmail.com> | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License version 2 as | |
| 7 | * published by the Free Software Foundation. | |
| 8 | * | |
| 9 | * This program is distributed in the hope that it will be useful, | |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | * GNU General Public License for more details. | |
| 13 | * | |
| 14 | * You should have received a copy of the GNU General Public License | |
| 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
| 16 | */ | |
| 17 | #ifndef __ASM_INSN_H | |
| 18 | #define __ASM_INSN_H | |
| 19 | #include <linux/types.h> | |
| 20 | ||
| 21 | /* | |
| 22 | * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a | |
| 23 | * Section C3.1 "A64 instruction index by encoding": | |
| 24 | * AArch64 main encoding table | |
| 25 | * Bit position | |
| 26 | * 28 27 26 25 Encoding Group | |
| 27 | * 0 0 - - Unallocated | |
| 28 | * 1 0 0 - Data processing, immediate | |
| 29 | * 1 0 1 - Branch, exception generation and system instructions | |
| 30 | * - 1 - 0 Loads and stores | |
| 31 | * - 1 0 1 Data processing - register | |
| 32 | * 0 1 1 1 Data processing - SIMD and floating point | |
| 33 | * 1 1 1 1 Data processing - SIMD and floating point | |
| 34 | * "-" means "don't care" | |
| 35 | */ | |
| 36 | enum aarch64_insn_encoding_class { | |
| 37 | AARCH64_INSN_CLS_UNKNOWN, /* UNALLOCATED */ | |
| 38 | AARCH64_INSN_CLS_DP_IMM, /* Data processing - immediate */ | |
| 39 | AARCH64_INSN_CLS_DP_REG, /* Data processing - register */ | |
| 40 | AARCH64_INSN_CLS_DP_FPSIMD, /* Data processing - SIMD and FP */ | |
| 41 | AARCH64_INSN_CLS_LDST, /* Loads and stores */ | |
| 42 | AARCH64_INSN_CLS_BR_SYS, /* Branch, exception generation and | |
| 43 | * system instructions */ | |
| 44 | }; | |
| 45 | ||
| 46 | enum aarch64_insn_hint_op { | |
| 47 | AARCH64_INSN_HINT_NOP = 0x0 << 5, | |
| 48 | AARCH64_INSN_HINT_YIELD = 0x1 << 5, | |
| 49 | AARCH64_INSN_HINT_WFE = 0x2 << 5, | |
| 50 | AARCH64_INSN_HINT_WFI = 0x3 << 5, | |
| 51 | AARCH64_INSN_HINT_SEV = 0x4 << 5, | |
| 52 | AARCH64_INSN_HINT_SEVL = 0x5 << 5, | |
| 53 | }; | |
| 54 | ||
| 55 | #define __AARCH64_INSN_FUNCS(abbr, mask, val) \ | |
| 56 | static __always_inline bool aarch64_insn_is_##abbr(u32 code) \ | |
| 57 | { return (code & (mask)) == (val); } \ | |
| 58 | static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \ | |
| 59 | { return (val); } | |
| 60 | ||
| 61 | __AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000) | |
| 62 | __AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000) | |
| 63 | __AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001) | |
| 64 | __AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002) | |
| 65 | __AARCH64_INSN_FUNCS(smc, 0xFFE0001F, 0xD4000003) | |
| 66 | __AARCH64_INSN_FUNCS(brk, 0xFFE0001F, 0xD4200000) | |
| 67 | __AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F) | |
| 68 | ||
| 69 | #undef __AARCH64_INSN_FUNCS | |
| 70 | ||
| 71 | bool aarch64_insn_is_nop(u32 insn); | |
| 72 | ||
| 73 | enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn); | |
| 74 | ||
| 75 | bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn); | |
| 76 | ||
| 77 | #endif /* __ASM_INSN_H */ |