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caab277b | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
5c1ce6f7 MZ |
2 | /* |
3 | * Copyright (C) 2013 - ARM Ltd | |
4 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
5c1ce6f7 MZ |
5 | */ |
6 | ||
7 | #ifndef __ASM_ESR_H | |
8 | #define __ASM_ESR_H | |
9 | ||
d7a33f4f | 10 | #include <asm/memory.h> |
d251f67a | 11 | #include <asm/sysreg.h> |
d7a33f4f | 12 | |
cf99a48d MR |
13 | #define ESR_ELx_EC_UNKNOWN (0x00) |
14 | #define ESR_ELx_EC_WFx (0x01) | |
15 | /* Unallocated EC: 0x02 */ | |
16 | #define ESR_ELx_EC_CP15_32 (0x03) | |
17 | #define ESR_ELx_EC_CP15_64 (0x04) | |
18 | #define ESR_ELx_EC_CP14_MR (0x05) | |
19 | #define ESR_ELx_EC_CP14_LS (0x06) | |
20 | #define ESR_ELx_EC_FP_ASIMD (0x07) | |
15560657 | 21 | #define ESR_ELx_EC_CP10_ID (0x08) /* EL2 only */ |
aa6eece8 MR |
22 | #define ESR_ELx_EC_PAC (0x09) /* EL2 and above */ |
23 | /* Unallocated EC: 0x0A - 0x0B */ | |
cf99a48d | 24 | #define ESR_ELx_EC_CP14_64 (0x0C) |
8ef8f360 | 25 | #define ESR_ELx_EC_BTI (0x0D) |
cf99a48d MR |
26 | #define ESR_ELx_EC_ILL (0x0E) |
27 | /* Unallocated EC: 0x0F - 0x10 */ | |
28 | #define ESR_ELx_EC_SVC32 (0x11) | |
15560657 KM |
29 | #define ESR_ELx_EC_HVC32 (0x12) /* EL2 only */ |
30 | #define ESR_ELx_EC_SMC32 (0x13) /* EL2 and above */ | |
cf99a48d MR |
31 | /* Unallocated EC: 0x14 */ |
32 | #define ESR_ELx_EC_SVC64 (0x15) | |
15560657 KM |
33 | #define ESR_ELx_EC_HVC64 (0x16) /* EL2 and above */ |
34 | #define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */ | |
cf99a48d | 35 | #define ESR_ELx_EC_SYS64 (0x18) |
67236564 | 36 | #define ESR_ELx_EC_SVE (0x19) |
332e5281 | 37 | #define ESR_ELx_EC_ERET (0x1a) /* EL2 only */ |
e16aeb07 ADK |
38 | /* Unallocated EC: 0x1B */ |
39 | #define ESR_ELx_EC_FPAC (0x1C) /* EL1 and above */ | |
40 | /* Unallocated EC: 0x1D - 0x1E */ | |
15560657 | 41 | #define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */ |
cf99a48d MR |
42 | #define ESR_ELx_EC_IABT_LOW (0x20) |
43 | #define ESR_ELx_EC_IABT_CUR (0x21) | |
44 | #define ESR_ELx_EC_PC_ALIGN (0x22) | |
45 | /* Unallocated EC: 0x23 */ | |
46 | #define ESR_ELx_EC_DABT_LOW (0x24) | |
47 | #define ESR_ELx_EC_DABT_CUR (0x25) | |
48 | #define ESR_ELx_EC_SP_ALIGN (0x26) | |
49 | /* Unallocated EC: 0x27 */ | |
50 | #define ESR_ELx_EC_FP_EXC32 (0x28) | |
51 | /* Unallocated EC: 0x29 - 0x2B */ | |
52 | #define ESR_ELx_EC_FP_EXC64 (0x2C) | |
53 | /* Unallocated EC: 0x2D - 0x2E */ | |
54 | #define ESR_ELx_EC_SERROR (0x2F) | |
55 | #define ESR_ELx_EC_BREAKPT_LOW (0x30) | |
56 | #define ESR_ELx_EC_BREAKPT_CUR (0x31) | |
57 | #define ESR_ELx_EC_SOFTSTP_LOW (0x32) | |
58 | #define ESR_ELx_EC_SOFTSTP_CUR (0x33) | |
59 | #define ESR_ELx_EC_WATCHPT_LOW (0x34) | |
60 | #define ESR_ELx_EC_WATCHPT_CUR (0x35) | |
61 | /* Unallocated EC: 0x36 - 0x37 */ | |
62 | #define ESR_ELx_EC_BKPT32 (0x38) | |
63 | /* Unallocated EC: 0x39 */ | |
15560657 | 64 | #define ESR_ELx_EC_VECTOR32 (0x3A) /* EL2 only */ |
27afb236 | 65 | /* Unallocated EC: 0x3B */ |
cf99a48d MR |
66 | #define ESR_ELx_EC_BRK64 (0x3C) |
67 | /* Unallocated EC: 0x3D - 0x3F */ | |
68 | #define ESR_ELx_EC_MAX (0x3F) | |
69 | ||
70 | #define ESR_ELx_EC_SHIFT (26) | |
71 | #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT) | |
275f344b | 72 | #define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) |
cf99a48d | 73 | |
1f9b8936 JT |
74 | #define ESR_ELx_IL_SHIFT (25) |
75 | #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT) | |
cf99a48d | 76 | #define ESR_ELx_ISS_MASK (ESR_ELx_IL - 1) |
9dbd5bb2 SP |
77 | |
78 | /* ISS field definitions shared by different classes */ | |
1f9b8936 JT |
79 | #define ESR_ELx_WNR_SHIFT (6) |
80 | #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT) | |
9dbd5bb2 | 81 | |
6bf0dcfd JM |
82 | /* Asynchronous Error Type */ |
83 | #define ESR_ELx_IDS_SHIFT (24) | |
84 | #define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT) | |
85 | #define ESR_ELx_AET_SHIFT (10) | |
86 | #define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT) | |
87 | ||
88 | #define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT) | |
89 | #define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT) | |
90 | #define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT) | |
91 | #define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT) | |
92 | #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT) | |
93 | ||
9dbd5bb2 | 94 | /* Shared ISS field definitions for Data/Instruction aborts */ |
1f9b8936 JT |
95 | #define ESR_ELx_SET_SHIFT (11) |
96 | #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT) | |
97 | #define ESR_ELx_FnV_SHIFT (10) | |
98 | #define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT) | |
99 | #define ESR_ELx_EA_SHIFT (9) | |
100 | #define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT) | |
101 | #define ESR_ELx_S1PTW_SHIFT (7) | |
102 | #define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT) | |
9dbd5bb2 SP |
103 | |
104 | /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */ | |
105 | #define ESR_ELx_FSC (0x3F) | |
106 | #define ESR_ELx_FSC_TYPE (0x3C) | |
7d894834 | 107 | #define ESR_ELx_FSC_LEVEL (0x03) |
9dbd5bb2 | 108 | #define ESR_ELx_FSC_EXTABT (0x10) |
6bf0dcfd | 109 | #define ESR_ELx_FSC_SERROR (0x11) |
9dbd5bb2 SP |
110 | #define ESR_ELx_FSC_ACCESS (0x08) |
111 | #define ESR_ELx_FSC_FAULT (0x04) | |
112 | #define ESR_ELx_FSC_PERM (0x0C) | |
113 | ||
114 | /* ISS field definitions for Data Aborts */ | |
1f9b8936 JT |
115 | #define ESR_ELx_ISV_SHIFT (24) |
116 | #define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT) | |
cf99a48d MR |
117 | #define ESR_ELx_SAS_SHIFT (22) |
118 | #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT) | |
1f9b8936 JT |
119 | #define ESR_ELx_SSE_SHIFT (21) |
120 | #define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT) | |
cf99a48d MR |
121 | #define ESR_ELx_SRT_SHIFT (16) |
122 | #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT) | |
1f9b8936 JT |
123 | #define ESR_ELx_SF_SHIFT (15) |
124 | #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT) | |
125 | #define ESR_ELx_AR_SHIFT (14) | |
126 | #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT) | |
127 | #define ESR_ELx_CM_SHIFT (8) | |
128 | #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) | |
9dbd5bb2 SP |
129 | |
130 | /* ISS field definitions for exceptions taken in to Hyp */ | |
cf99a48d MR |
131 | #define ESR_ELx_CV (UL(1) << 24) |
132 | #define ESR_ELx_COND_SHIFT (20) | |
133 | #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT) | |
c219bc4e MZ |
134 | #define ESR_ELx_WFx_ISS_TI (UL(1) << 0) |
135 | #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0) | |
cf99a48d | 136 | #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) |
1c6007d5 | 137 | #define ESR_ELx_xVC_IMM_MASK ((1UL << 16) - 1) |
cf99a48d | 138 | |
68ddbf09 JM |
139 | #define DISR_EL1_IDS (UL(1) << 24) |
140 | /* | |
141 | * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean | |
142 | * different things in the future... | |
143 | */ | |
144 | #define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC) | |
145 | ||
72d033e8 | 146 | /* ESR value templates for specific events */ |
c219bc4e MZ |
147 | #define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI) |
148 | #define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \ | |
149 | ESR_ELx_WFx_ISS_WFI) | |
72d033e8 DM |
150 | |
151 | /* BRK instruction trap from AArch64 state */ | |
453b7740 | 152 | #define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff |
72d033e8 | 153 | |
9dbd5bb2 SP |
154 | /* ISS field definitions for System instruction traps */ |
155 | #define ESR_ELx_SYS64_ISS_RES0_SHIFT 22 | |
156 | #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT) | |
157 | #define ESR_ELx_SYS64_ISS_DIR_MASK 0x1 | |
158 | #define ESR_ELx_SYS64_ISS_DIR_READ 0x1 | |
159 | #define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0 | |
160 | ||
161 | #define ESR_ELx_SYS64_ISS_RT_SHIFT 5 | |
162 | #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT) | |
163 | #define ESR_ELx_SYS64_ISS_CRM_SHIFT 1 | |
164 | #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT) | |
165 | #define ESR_ELx_SYS64_ISS_CRN_SHIFT 10 | |
166 | #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | |
167 | #define ESR_ELx_SYS64_ISS_OP1_SHIFT 14 | |
168 | #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | |
169 | #define ESR_ELx_SYS64_ISS_OP2_SHIFT 17 | |
170 | #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | |
171 | #define ESR_ELx_SYS64_ISS_OP0_SHIFT 20 | |
172 | #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | |
173 | #define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ | |
174 | ESR_ELx_SYS64_ISS_OP1_MASK | \ | |
175 | ESR_ELx_SYS64_ISS_OP2_MASK | \ | |
176 | ESR_ELx_SYS64_ISS_CRN_MASK | \ | |
177 | ESR_ELx_SYS64_ISS_CRM_MASK) | |
178 | #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ | |
179 | (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \ | |
180 | ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \ | |
181 | ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \ | |
182 | ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \ | |
183 | ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT)) | |
116c81f4 SP |
184 | |
185 | #define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \ | |
186 | ESR_ELx_SYS64_ISS_DIR_MASK) | |
1c839141 AK |
187 | #define ESR_ELx_SYS64_ISS_RT(esr) \ |
188 | (((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT) | |
9dbd5bb2 SP |
189 | /* |
190 | * User space cache operations have the following sysreg encoding | |
191 | * in System instructions. | |
d16ed410 | 192 | * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0) |
9dbd5bb2 SP |
193 | */ |
194 | #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14 | |
d16ed410 | 195 | #define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13 |
e1bc5d1b | 196 | #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12 |
9dbd5bb2 SP |
197 | #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11 |
198 | #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10 | |
199 | #define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5 | |
200 | ||
201 | #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ | |
202 | ESR_ELx_SYS64_ISS_OP1_MASK | \ | |
203 | ESR_ELx_SYS64_ISS_OP2_MASK | \ | |
204 | ESR_ELx_SYS64_ISS_CRN_MASK | \ | |
205 | ESR_ELx_SYS64_ISS_DIR_MASK) | |
206 | #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \ | |
207 | (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \ | |
208 | ESR_ELx_SYS64_ISS_DIR_WRITE) | |
21f84796 AK |
209 | /* |
210 | * User space MRS operations which are supported for emulation | |
211 | * have the following sysreg encoding in System instructions. | |
212 | * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1) | |
213 | */ | |
214 | #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ | |
215 | ESR_ELx_SYS64_ISS_OP1_MASK | \ | |
216 | ESR_ELx_SYS64_ISS_CRN_MASK | \ | |
217 | ESR_ELx_SYS64_ISS_DIR_MASK) | |
218 | #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \ | |
219 | (ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \ | |
220 | ESR_ELx_SYS64_ISS_DIR_READ) | |
116c81f4 SP |
221 | |
222 | #define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0) | |
223 | #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \ | |
224 | ESR_ELx_SYS64_ISS_DIR_READ) | |
225 | ||
6126ce05 MZ |
226 | #define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ |
227 | ESR_ELx_SYS64_ISS_DIR_READ) | |
9842119a MZ |
228 | |
229 | #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \ | |
230 | ESR_ELx_SYS64_ISS_DIR_READ) | |
231 | ||
d251f67a MZ |
232 | #define esr_sys64_to_sysreg(e) \ |
233 | sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \ | |
234 | ESR_ELx_SYS64_ISS_OP0_SHIFT), \ | |
235 | (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ | |
236 | ESR_ELx_SYS64_ISS_OP1_SHIFT), \ | |
237 | (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ | |
238 | ESR_ELx_SYS64_ISS_CRN_SHIFT), \ | |
239 | (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ | |
240 | ESR_ELx_SYS64_ISS_CRM_SHIFT), \ | |
241 | (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ | |
242 | ESR_ELx_SYS64_ISS_OP2_SHIFT)) | |
243 | ||
244 | #define esr_cp15_to_sysreg(e) \ | |
245 | sys_reg(3, \ | |
246 | (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ | |
247 | ESR_ELx_SYS64_ISS_OP1_SHIFT), \ | |
248 | (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ | |
249 | ESR_ELx_SYS64_ISS_CRN_SHIFT), \ | |
250 | (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ | |
251 | ESR_ELx_SYS64_ISS_CRM_SHIFT), \ | |
252 | (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ | |
253 | ESR_ELx_SYS64_ISS_OP2_SHIFT)) | |
254 | ||
af4a81b9 DM |
255 | /* |
256 | * ISS field definitions for floating-point exception traps | |
257 | * (FP_EXC_32/FP_EXC_64). | |
258 | * | |
259 | * (The FPEXC_* constants are used instead for common bits.) | |
260 | */ | |
261 | ||
262 | #define ESR_ELx_FP_EXC_TFV (UL(1) << 23) | |
263 | ||
bd7ac140 MZ |
264 | /* |
265 | * ISS field definitions for CP15 accesses | |
266 | */ | |
267 | #define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1 | |
268 | #define ESR_ELx_CP15_32_ISS_DIR_READ 0x1 | |
269 | #define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0 | |
270 | ||
271 | #define ESR_ELx_CP15_32_ISS_RT_SHIFT 5 | |
272 | #define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT) | |
273 | #define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1 | |
274 | #define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT) | |
275 | #define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10 | |
276 | #define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | |
277 | #define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14 | |
278 | #define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | |
279 | #define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17 | |
280 | #define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | |
281 | ||
282 | #define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | \ | |
283 | ESR_ELx_CP15_32_ISS_OP2_MASK | \ | |
284 | ESR_ELx_CP15_32_ISS_CRN_MASK | \ | |
285 | ESR_ELx_CP15_32_ISS_CRM_MASK | \ | |
286 | ESR_ELx_CP15_32_ISS_DIR_MASK) | |
287 | #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \ | |
288 | (((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \ | |
289 | ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \ | |
290 | ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \ | |
291 | ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)) | |
292 | ||
293 | #define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1 | |
294 | #define ESR_ELx_CP15_64_ISS_DIR_READ 0x1 | |
295 | #define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0 | |
296 | ||
297 | #define ESR_ELx_CP15_64_ISS_RT_SHIFT 5 | |
298 | #define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT) | |
299 | ||
300 | #define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10 | |
301 | #define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT) | |
302 | ||
303 | #define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16 | |
304 | #define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | |
305 | #define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1 | |
306 | #define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT) | |
307 | ||
308 | #define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \ | |
309 | (((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \ | |
310 | ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)) | |
311 | ||
312 | #define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | \ | |
313 | ESR_ELx_CP15_64_ISS_CRM_MASK | \ | |
314 | ESR_ELx_CP15_64_ISS_DIR_MASK) | |
315 | ||
50de013d MZ |
316 | #define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \ |
317 | ESR_ELx_CP15_64_ISS_DIR_READ) | |
318 | ||
32a3e635 MZ |
319 | #define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\ |
320 | ESR_ELx_CP15_32_ISS_DIR_READ) | |
321 | ||
60a1f02c MR |
322 | #ifndef __ASSEMBLY__ |
323 | #include <asm/types.h> | |
324 | ||
1f9b8936 JT |
325 | static inline bool esr_is_data_abort(u32 esr) |
326 | { | |
327 | const u32 ec = ESR_ELx_EC(esr); | |
328 | ||
329 | return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR; | |
330 | } | |
331 | ||
60a1f02c MR |
332 | const char *esr_get_class_string(u32 esr); |
333 | #endif /* __ASSEMBLY */ | |
334 | ||
5c1ce6f7 | 335 | #endif /* __ASM_ESR_H */ |