[linux-2.6-block.git] / arch / arm64 / include / asm / esr.h

/*
 * Copyright (C) 2013 - ARM Ltd
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __ASM_ESR_H
#define __ASM_ESR_H

#include <asm/memory.h>
#include <asm/sysreg.h>

#define ESR_ELx_EC_UNKNOWN	(0x00)
#define ESR_ELx_EC_WFx		(0x01)
/* Unallocated EC: 0x02 */
#define ESR_ELx_EC_CP15_32	(0x03)
#define ESR_ELx_EC_CP15_64	(0x04)
#define ESR_ELx_EC_CP14_MR	(0x05)
#define ESR_ELx_EC_CP14_LS	(0x06)
#define ESR_ELx_EC_FP_ASIMD	(0x07)
#define ESR_ELx_EC_CP10_ID	(0x08)	/* EL2 only */
#define ESR_ELx_EC_PAC		(0x09)	/* EL2 and above */
/* Unallocated EC: 0x0A - 0x0B */
#define ESR_ELx_EC_CP14_64	(0x0C)
/* Unallocated EC: 0x0d */
#define ESR_ELx_EC_ILL		(0x0E)
/* Unallocated EC: 0x0F - 0x10 */
#define ESR_ELx_EC_SVC32	(0x11)
#define ESR_ELx_EC_HVC32	(0x12)	/* EL2 only */
#define ESR_ELx_EC_SMC32	(0x13)	/* EL2 and above */
/* Unallocated EC: 0x14 */
#define ESR_ELx_EC_SVC64	(0x15)
#define ESR_ELx_EC_HVC64	(0x16)	/* EL2 and above */
#define ESR_ELx_EC_SMC64	(0x17)	/* EL2 and above */
#define ESR_ELx_EC_SYS64	(0x18)
#define ESR_ELx_EC_SVE		(0x19)
/* Unallocated EC: 0x1A - 0x1E */
#define ESR_ELx_EC_IMP_DEF	(0x1f)	/* EL3 only */
#define ESR_ELx_EC_IABT_LOW	(0x20)
#define ESR_ELx_EC_IABT_CUR	(0x21)
#define ESR_ELx_EC_PC_ALIGN	(0x22)
/* Unallocated EC: 0x23 */
#define ESR_ELx_EC_DABT_LOW	(0x24)
#define ESR_ELx_EC_DABT_CUR	(0x25)
#define ESR_ELx_EC_SP_ALIGN	(0x26)
/* Unallocated EC: 0x27 */
#define ESR_ELx_EC_FP_EXC32	(0x28)
/* Unallocated EC: 0x29 - 0x2B */
#define ESR_ELx_EC_FP_EXC64	(0x2C)
/* Unallocated EC: 0x2D - 0x2E */
#define ESR_ELx_EC_SERROR	(0x2F)
#define ESR_ELx_EC_BREAKPT_LOW	(0x30)
#define ESR_ELx_EC_BREAKPT_CUR	(0x31)
#define ESR_ELx_EC_SOFTSTP_LOW	(0x32)
#define ESR_ELx_EC_SOFTSTP_CUR	(0x33)
#define ESR_ELx_EC_WATCHPT_LOW	(0x34)
#define ESR_ELx_EC_WATCHPT_CUR	(0x35)
/* Unallocated EC: 0x36 - 0x37 */
#define ESR_ELx_EC_BKPT32	(0x38)
/* Unallocated EC: 0x39 */
#define ESR_ELx_EC_VECTOR32	(0x3A)	/* EL2 only */
/* Unallocted EC: 0x3B */
#define ESR_ELx_EC_BRK64	(0x3C)
/* Unallocated EC: 0x3D - 0x3F */
#define ESR_ELx_EC_MAX		(0x3F)

#define ESR_ELx_EC_SHIFT	(26)
#define ESR_ELx_EC_MASK		(UL(0x3F) << ESR_ELx_EC_SHIFT)
#define ESR_ELx_EC(esr)		(((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)

#define ESR_ELx_IL_SHIFT	(25)
#define ESR_ELx_IL		(UL(1) << ESR_ELx_IL_SHIFT)
#define ESR_ELx_ISS_MASK	(ESR_ELx_IL - 1)

/* ISS field definitions shared by different classes */
#define ESR_ELx_WNR_SHIFT	(6)
#define ESR_ELx_WNR		(UL(1) << ESR_ELx_WNR_SHIFT)

/* Asynchronous Error Type */
#define ESR_ELx_IDS_SHIFT	(24)
#define ESR_ELx_IDS		(UL(1) << ESR_ELx_IDS_SHIFT)
#define ESR_ELx_AET_SHIFT	(10)
#define ESR_ELx_AET		(UL(0x7) << ESR_ELx_AET_SHIFT)

#define ESR_ELx_AET_UC		(UL(0) << ESR_ELx_AET_SHIFT)
#define ESR_ELx_AET_UEU		(UL(1) << ESR_ELx_AET_SHIFT)
#define ESR_ELx_AET_UEO		(UL(2) << ESR_ELx_AET_SHIFT)
#define ESR_ELx_AET_UER		(UL(3) << ESR_ELx_AET_SHIFT)
#define ESR_ELx_AET_CE		(UL(6) << ESR_ELx_AET_SHIFT)

/* Shared ISS field definitions for Data/Instruction aborts */
#define ESR_ELx_SET_SHIFT	(11)
#define ESR_ELx_SET_MASK	(UL(3) << ESR_ELx_SET_SHIFT)
#define ESR_ELx_FnV_SHIFT	(10)
#define ESR_ELx_FnV		(UL(1) << ESR_ELx_FnV_SHIFT)
#define ESR_ELx_EA_SHIFT	(9)
#define ESR_ELx_EA		(UL(1) << ESR_ELx_EA_SHIFT)
#define ESR_ELx_S1PTW_SHIFT	(7)
#define ESR_ELx_S1PTW		(UL(1) << ESR_ELx_S1PTW_SHIFT)

/* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
#define ESR_ELx_FSC		(0x3F)
#define ESR_ELx_FSC_TYPE	(0x3C)
#define ESR_ELx_FSC_EXTABT	(0x10)
#define ESR_ELx_FSC_SERROR	(0x11)
#define ESR_ELx_FSC_ACCESS	(0x08)
#define ESR_ELx_FSC_FAULT	(0x04)
#define ESR_ELx_FSC_PERM	(0x0C)

/* ISS field definitions for Data Aborts */
#define ESR_ELx_ISV_SHIFT	(24)
#define ESR_ELx_ISV		(UL(1) << ESR_ELx_ISV_SHIFT)
#define ESR_ELx_SAS_SHIFT	(22)
#define ESR_ELx_SAS		(UL(3) << ESR_ELx_SAS_SHIFT)
#define ESR_ELx_SSE_SHIFT	(21)
#define ESR_ELx_SSE		(UL(1) << ESR_ELx_SSE_SHIFT)
#define ESR_ELx_SRT_SHIFT	(16)
#define ESR_ELx_SRT_MASK	(UL(0x1F) << ESR_ELx_SRT_SHIFT)
#define ESR_ELx_SF_SHIFT	(15)
#define ESR_ELx_SF 		(UL(1) << ESR_ELx_SF_SHIFT)
#define ESR_ELx_AR_SHIFT	(14)
#define ESR_ELx_AR 		(UL(1) << ESR_ELx_AR_SHIFT)
#define ESR_ELx_CM_SHIFT	(8)
#define ESR_ELx_CM 		(UL(1) << ESR_ELx_CM_SHIFT)

/* ISS field definitions for exceptions taken in to Hyp */
#define ESR_ELx_CV		(UL(1) << 24)
#define ESR_ELx_COND_SHIFT	(20)
#define ESR_ELx_COND_MASK	(UL(0xF) << ESR_ELx_COND_SHIFT)
#define ESR_ELx_WFx_ISS_TI	(UL(1) << 0)
#define ESR_ELx_WFx_ISS_WFI	(UL(0) << 0)
#define ESR_ELx_WFx_ISS_WFE	(UL(1) << 0)
#define ESR_ELx_xVC_IMM_MASK	((1UL << 16) - 1)

#define DISR_EL1_IDS		(UL(1) << 24)
/*
 * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean
 * different things in the future...
 */
#define DISR_EL1_ESR_MASK	(ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)

/* ESR value templates for specific events */
#define ESR_ELx_WFx_MASK	(ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI)
#define ESR_ELx_WFx_WFI_VAL	((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) |	\
				 ESR_ELx_WFx_ISS_WFI)

/* BRK instruction trap from AArch64 state */
#define ESR_ELx_BRK64_ISS_COMMENT_MASK	0xffff

/* ISS field definitions for System instruction traps */
#define ESR_ELx_SYS64_ISS_RES0_SHIFT	22
#define ESR_ELx_SYS64_ISS_RES0_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
#define ESR_ELx_SYS64_ISS_DIR_MASK	0x1
#define ESR_ELx_SYS64_ISS_DIR_READ	0x1
#define ESR_ELx_SYS64_ISS_DIR_WRITE	0x0

#define ESR_ELx_SYS64_ISS_RT_SHIFT	5
#define ESR_ELx_SYS64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
#define ESR_ELx_SYS64_ISS_CRM_SHIFT	1
#define ESR_ELx_SYS64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
#define ESR_ELx_SYS64_ISS_CRN_SHIFT	10
#define ESR_ELx_SYS64_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
#define ESR_ELx_SYS64_ISS_OP1_SHIFT	14
#define ESR_ELx_SYS64_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
#define ESR_ELx_SYS64_ISS_OP2_SHIFT	17
#define ESR_ELx_SYS64_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
#define ESR_ELx_SYS64_ISS_OP0_SHIFT	20
#define ESR_ELx_SYS64_ISS_OP0_MASK	(UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
#define ESR_ELx_SYS64_ISS_SYS_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
					 ESR_ELx_SYS64_ISS_OP1_MASK | \
					 ESR_ELx_SYS64_ISS_OP2_MASK | \
					 ESR_ELx_SYS64_ISS_CRN_MASK | \
					 ESR_ELx_SYS64_ISS_CRM_MASK)
#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
					(((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \
					 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \
					 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
					 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
					 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))

#define ESR_ELx_SYS64_ISS_SYS_OP_MASK	(ESR_ELx_SYS64_ISS_SYS_MASK | \
					 ESR_ELx_SYS64_ISS_DIR_MASK)
#define ESR_ELx_SYS64_ISS_RT(esr) \
	(((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
/*
 * User space cache operations have the following sysreg encoding
 * in System instructions.
 * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 14 }, WRITE (L=0)
 */
#define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC	14
#define ESR_ELx_SYS64_ISS_CRM_DC_CVAP	12
#define ESR_ELx_SYS64_ISS_CRM_DC_CVAU	11
#define ESR_ELx_SYS64_ISS_CRM_DC_CVAC	10
#define ESR_ELx_SYS64_ISS_CRM_IC_IVAU	5

#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
						 ESR_ELx_SYS64_ISS_OP1_MASK | \
						 ESR_ELx_SYS64_ISS_OP2_MASK | \
						 ESR_ELx_SYS64_ISS_CRN_MASK | \
						 ESR_ELx_SYS64_ISS_DIR_MASK)
#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
				(ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
				 ESR_ELx_SYS64_ISS_DIR_WRITE)
/*
 * User space MRS operations which are supported for emulation
 * have the following sysreg encoding in System instructions.
 * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
 */
#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
						 ESR_ELx_SYS64_ISS_OP1_MASK | \
						 ESR_ELx_SYS64_ISS_CRN_MASK | \
						 ESR_ELx_SYS64_ISS_DIR_MASK)
#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \
				(ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \
				 ESR_ELx_SYS64_ISS_DIR_READ)

#define ESR_ELx_SYS64_ISS_SYS_CTR	ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
#define ESR_ELx_SYS64_ISS_SYS_CTR_READ	(ESR_ELx_SYS64_ISS_SYS_CTR | \
					 ESR_ELx_SYS64_ISS_DIR_READ)

#define ESR_ELx_SYS64_ISS_SYS_CNTVCT	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
					 ESR_ELx_SYS64_ISS_DIR_READ)

#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
					 ESR_ELx_SYS64_ISS_DIR_READ)

#define esr_sys64_to_sysreg(e)					\
	sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >>		\
		 ESR_ELx_SYS64_ISS_OP0_SHIFT),			\
		(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >>		\
		 ESR_ELx_SYS64_ISS_OP1_SHIFT),			\
		(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >>		\
		 ESR_ELx_SYS64_ISS_CRN_SHIFT),			\
		(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >>		\
		 ESR_ELx_SYS64_ISS_CRM_SHIFT),			\
		(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >>		\
		 ESR_ELx_SYS64_ISS_OP2_SHIFT))

#define esr_cp15_to_sysreg(e)					\
	sys_reg(3,						\
		(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >>		\
		 ESR_ELx_SYS64_ISS_OP1_SHIFT),			\
		(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >>		\
		 ESR_ELx_SYS64_ISS_CRN_SHIFT),			\
		(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >>		\
		 ESR_ELx_SYS64_ISS_CRM_SHIFT),			\
		(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >>		\
		 ESR_ELx_SYS64_ISS_OP2_SHIFT))

/*
 * ISS field definitions for floating-point exception traps
 * (FP_EXC_32/FP_EXC_64).
 *
 * (The FPEXC_* constants are used instead for common bits.)
 */

#define ESR_ELx_FP_EXC_TFV	(UL(1) << 23)

/*
 * ISS field definitions for CP15 accesses
 */
#define ESR_ELx_CP15_32_ISS_DIR_MASK	0x1
#define ESR_ELx_CP15_32_ISS_DIR_READ	0x1
#define ESR_ELx_CP15_32_ISS_DIR_WRITE	0x0

#define ESR_ELx_CP15_32_ISS_RT_SHIFT	5
#define ESR_ELx_CP15_32_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
#define ESR_ELx_CP15_32_ISS_CRM_SHIFT	1
#define ESR_ELx_CP15_32_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
#define ESR_ELx_CP15_32_ISS_CRN_SHIFT	10
#define ESR_ELx_CP15_32_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
#define ESR_ELx_CP15_32_ISS_OP1_SHIFT	14
#define ESR_ELx_CP15_32_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
#define ESR_ELx_CP15_32_ISS_OP2_SHIFT	17
#define ESR_ELx_CP15_32_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)

#define ESR_ELx_CP15_32_ISS_SYS_MASK	(ESR_ELx_CP15_32_ISS_OP1_MASK | \
					 ESR_ELx_CP15_32_ISS_OP2_MASK | \
					 ESR_ELx_CP15_32_ISS_CRN_MASK | \
					 ESR_ELx_CP15_32_ISS_CRM_MASK | \
					 ESR_ELx_CP15_32_ISS_DIR_MASK)
#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
					(((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \
					 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
					 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
					 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))

#define ESR_ELx_CP15_64_ISS_DIR_MASK	0x1
#define ESR_ELx_CP15_64_ISS_DIR_READ	0x1
#define ESR_ELx_CP15_64_ISS_DIR_WRITE	0x0

#define ESR_ELx_CP15_64_ISS_RT_SHIFT	5
#define ESR_ELx_CP15_64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)

#define ESR_ELx_CP15_64_ISS_RT2_SHIFT	10
#define ESR_ELx_CP15_64_ISS_RT2_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)

#define ESR_ELx_CP15_64_ISS_OP1_SHIFT	16
#define ESR_ELx_CP15_64_ISS_OP1_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
#define ESR_ELx_CP15_64_ISS_CRM_SHIFT	1
#define ESR_ELx_CP15_64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)

#define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
					(((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
					 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))

#define ESR_ELx_CP15_64_ISS_SYS_MASK	(ESR_ELx_CP15_64_ISS_OP1_MASK |	\
					 ESR_ELx_CP15_64_ISS_CRM_MASK | \
					 ESR_ELx_CP15_64_ISS_DIR_MASK)

#define ESR_ELx_CP15_64_ISS_SYS_CNTVCT	(ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
					 ESR_ELx_CP15_64_ISS_DIR_READ)

#define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ	(ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\
					 ESR_ELx_CP15_32_ISS_DIR_READ)

#ifndef __ASSEMBLY__
#include <asm/types.h>

static inline bool esr_is_data_abort(u32 esr)
{
	const u32 ec = ESR_ELx_EC(esr);

	return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR;
}

const char *esr_get_class_string(u32 esr);
#endif /* __ASSEMBLY */

#endif /* __ASM_ESR_H */
Commit	Line	Data
5c1ce6f7 MZ	1	/*
	2	* Copyright (C) 2013 - ARM Ltd
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#ifndef __ASM_ESR_H
	19	#define __ASM_ESR_H
	20
d7a33f4f	21	#include <asm/memory.h>
d251f67a	22	#include <asm/sysreg.h>
d7a33f4f	23
cf99a48d MR	24	#define ESR_ELx_EC_UNKNOWN (0x00)
	25	#define ESR_ELx_EC_WFx (0x01)
	26	/* Unallocated EC: 0x02 */
	27	#define ESR_ELx_EC_CP15_32 (0x03)
	28	#define ESR_ELx_EC_CP15_64 (0x04)
	29	#define ESR_ELx_EC_CP14_MR (0x05)
	30	#define ESR_ELx_EC_CP14_LS (0x06)
	31	#define ESR_ELx_EC_FP_ASIMD (0x07)
15560657	32	#define ESR_ELx_EC_CP10_ID (0x08) /* EL2 only */
aa6eece8 MR	33	#define ESR_ELx_EC_PAC (0x09) /* EL2 and above */
aa6eece8 MR	34	/* Unallocated EC: 0x0A - 0x0B */
cf99a48d MR	35	#define ESR_ELx_EC_CP14_64 (0x0C)
	36	/* Unallocated EC: 0x0d */
	37	#define ESR_ELx_EC_ILL (0x0E)
	38	/* Unallocated EC: 0x0F - 0x10 */
	39	#define ESR_ELx_EC_SVC32 (0x11)
15560657 KM	40	#define ESR_ELx_EC_HVC32 (0x12) /* EL2 only */
15560657 KM	41	#define ESR_ELx_EC_SMC32 (0x13) /* EL2 and above */
cf99a48d MR	42	/* Unallocated EC: 0x14 */
cf99a48d MR	43	#define ESR_ELx_EC_SVC64 (0x15)
15560657 KM	44	#define ESR_ELx_EC_HVC64 (0x16) /* EL2 and above */
15560657 KM	45	#define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */
cf99a48d	46	#define ESR_ELx_EC_SYS64 (0x18)
67236564 DM	47	#define ESR_ELx_EC_SVE (0x19)
67236564 DM	48	/* Unallocated EC: 0x1A - 0x1E */
15560657	49	#define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */
cf99a48d MR	50	#define ESR_ELx_EC_IABT_LOW (0x20)
	51	#define ESR_ELx_EC_IABT_CUR (0x21)
	52	#define ESR_ELx_EC_PC_ALIGN (0x22)
	53	/* Unallocated EC: 0x23 */
	54	#define ESR_ELx_EC_DABT_LOW (0x24)
	55	#define ESR_ELx_EC_DABT_CUR (0x25)
	56	#define ESR_ELx_EC_SP_ALIGN (0x26)
	57	/* Unallocated EC: 0x27 */
	58	#define ESR_ELx_EC_FP_EXC32 (0x28)
	59	/* Unallocated EC: 0x29 - 0x2B */
	60	#define ESR_ELx_EC_FP_EXC64 (0x2C)
	61	/* Unallocated EC: 0x2D - 0x2E */
	62	#define ESR_ELx_EC_SERROR (0x2F)
	63	#define ESR_ELx_EC_BREAKPT_LOW (0x30)
	64	#define ESR_ELx_EC_BREAKPT_CUR (0x31)
	65	#define ESR_ELx_EC_SOFTSTP_LOW (0x32)
	66	#define ESR_ELx_EC_SOFTSTP_CUR (0x33)
	67	#define ESR_ELx_EC_WATCHPT_LOW (0x34)
	68	#define ESR_ELx_EC_WATCHPT_CUR (0x35)
	69	/* Unallocated EC: 0x36 - 0x37 */
	70	#define ESR_ELx_EC_BKPT32 (0x38)
	71	/* Unallocated EC: 0x39 */
15560657	72	#define ESR_ELx_EC_VECTOR32 (0x3A) /* EL2 only */
cf99a48d MR	73	/* Unallocted EC: 0x3B */
	74	#define ESR_ELx_EC_BRK64 (0x3C)
	75	/* Unallocated EC: 0x3D - 0x3F */
	76	#define ESR_ELx_EC_MAX (0x3F)
	77
	78	#define ESR_ELx_EC_SHIFT (26)
	79	#define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
275f344b	80	#define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
cf99a48d	81
1f9b8936 JT	82	#define ESR_ELx_IL_SHIFT (25)
1f9b8936 JT	83	#define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
cf99a48d	84	#define ESR_ELx_ISS_MASK (ESR_ELx_IL - 1)
9dbd5bb2 SP	85
9dbd5bb2 SP	86	/* ISS field definitions shared by different classes */
1f9b8936 JT	87	#define ESR_ELx_WNR_SHIFT (6)
1f9b8936 JT	88	#define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
9dbd5bb2	89
6bf0dcfd JM	90	/* Asynchronous Error Type */
	91	#define ESR_ELx_IDS_SHIFT (24)
	92	#define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
	93	#define ESR_ELx_AET_SHIFT (10)
	94	#define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
	95
	96	#define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
	97	#define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
	98	#define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT)
	99	#define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
	100	#define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT)
	101
9dbd5bb2	102	/* Shared ISS field definitions for Data/Instruction aborts */
1f9b8936 JT	103	#define ESR_ELx_SET_SHIFT (11)
	104	#define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT)
	105	#define ESR_ELx_FnV_SHIFT (10)
	106	#define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT)
	107	#define ESR_ELx_EA_SHIFT (9)
	108	#define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT)
	109	#define ESR_ELx_S1PTW_SHIFT (7)
	110	#define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT)
9dbd5bb2 SP	111
	112	/* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
	113	#define ESR_ELx_FSC (0x3F)
	114	#define ESR_ELx_FSC_TYPE (0x3C)
	115	#define ESR_ELx_FSC_EXTABT (0x10)
6bf0dcfd	116	#define ESR_ELx_FSC_SERROR (0x11)
9dbd5bb2 SP	117	#define ESR_ELx_FSC_ACCESS (0x08)
	118	#define ESR_ELx_FSC_FAULT (0x04)
	119	#define ESR_ELx_FSC_PERM (0x0C)
	120
	121	/* ISS field definitions for Data Aborts */
1f9b8936 JT	122	#define ESR_ELx_ISV_SHIFT (24)
1f9b8936 JT	123	#define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
cf99a48d MR	124	#define ESR_ELx_SAS_SHIFT (22)
cf99a48d MR	125	#define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
1f9b8936 JT	126	#define ESR_ELx_SSE_SHIFT (21)
1f9b8936 JT	127	#define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT)
cf99a48d MR	128	#define ESR_ELx_SRT_SHIFT (16)
cf99a48d MR	129	#define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
1f9b8936 JT	130	#define ESR_ELx_SF_SHIFT (15)
	131	#define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT)
	132	#define ESR_ELx_AR_SHIFT (14)
	133	#define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT)
	134	#define ESR_ELx_CM_SHIFT (8)
	135	#define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT)
9dbd5bb2 SP	136
9dbd5bb2 SP	137	/* ISS field definitions for exceptions taken in to Hyp */
cf99a48d MR	138	#define ESR_ELx_CV (UL(1) << 24)
	139	#define ESR_ELx_COND_SHIFT (20)
	140	#define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
c219bc4e MZ	141	#define ESR_ELx_WFx_ISS_TI (UL(1) << 0)
c219bc4e MZ	142	#define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
cf99a48d	143	#define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
1c6007d5	144	#define ESR_ELx_xVC_IMM_MASK ((1UL << 16) - 1)
cf99a48d	145
68ddbf09 JM	146	#define DISR_EL1_IDS (UL(1) << 24)
	147	/*
	148	* DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean
	149	* different things in the future...
	150	*/
	151	#define DISR_EL1_ESR_MASK (ESR_ELx_AET \| ESR_ELx_EA \| ESR_ELx_FSC)
	152
72d033e8	153	/* ESR value templates for specific events */
c219bc4e MZ	154	#define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK \| ESR_ELx_WFx_ISS_TI)
	155	#define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) \| \
	156	ESR_ELx_WFx_ISS_WFI)
72d033e8 DM	157
72d033e8 DM	158	/* BRK instruction trap from AArch64 state */
453b7740	159	#define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff
72d033e8	160
9dbd5bb2 SP	161	/* ISS field definitions for System instruction traps */
	162	#define ESR_ELx_SYS64_ISS_RES0_SHIFT 22
	163	#define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
	164	#define ESR_ELx_SYS64_ISS_DIR_MASK 0x1
	165	#define ESR_ELx_SYS64_ISS_DIR_READ 0x1
	166	#define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0
	167
	168	#define ESR_ELx_SYS64_ISS_RT_SHIFT 5
	169	#define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
	170	#define ESR_ELx_SYS64_ISS_CRM_SHIFT 1
	171	#define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
	172	#define ESR_ELx_SYS64_ISS_CRN_SHIFT 10
	173	#define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
	174	#define ESR_ELx_SYS64_ISS_OP1_SHIFT 14
	175	#define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
	176	#define ESR_ELx_SYS64_ISS_OP2_SHIFT 17
	177	#define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
	178	#define ESR_ELx_SYS64_ISS_OP0_SHIFT 20
	179	#define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
	180	#define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK \| \
	181	ESR_ELx_SYS64_ISS_OP1_MASK \| \
	182	ESR_ELx_SYS64_ISS_OP2_MASK \| \
	183	ESR_ELx_SYS64_ISS_CRN_MASK \| \
	184	ESR_ELx_SYS64_ISS_CRM_MASK)
	185	#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
	186	(((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) \| \
	187	((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) \| \
	188	((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) \| \
	189	((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) \| \
	190	((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
116c81f4 SP	191
	192	#define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK \| \
	193	ESR_ELx_SYS64_ISS_DIR_MASK)
1c839141 AK	194	#define ESR_ELx_SYS64_ISS_RT(esr) \
1c839141 AK	195	(((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
9dbd5bb2 SP	196	/*
	197	* User space cache operations have the following sysreg encoding
	198	* in System instructions.
e1bc5d1b	199	* op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 14 }, WRITE (L=0)
9dbd5bb2 SP	200	*/
9dbd5bb2 SP	201	#define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14
e1bc5d1b	202	#define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12
9dbd5bb2 SP	203	#define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11
	204	#define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10
	205	#define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5
	206
	207	#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK \| \
	208	ESR_ELx_SYS64_ISS_OP1_MASK \| \
	209	ESR_ELx_SYS64_ISS_OP2_MASK \| \
	210	ESR_ELx_SYS64_ISS_CRN_MASK \| \
	211	ESR_ELx_SYS64_ISS_DIR_MASK)
	212	#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
	213	(ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) \| \
	214	ESR_ELx_SYS64_ISS_DIR_WRITE)
21f84796 AK	215	/*
	216	* User space MRS operations which are supported for emulation
	217	* have the following sysreg encoding in System instructions.
	218	* op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
	219	*/
	220	#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK \| \
	221	ESR_ELx_SYS64_ISS_OP1_MASK \| \
	222	ESR_ELx_SYS64_ISS_CRN_MASK \| \
	223	ESR_ELx_SYS64_ISS_DIR_MASK)
	224	#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \
	225	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) \| \
	226	ESR_ELx_SYS64_ISS_DIR_READ)
116c81f4 SP	227
	228	#define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
	229	#define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR \| \
	230	ESR_ELx_SYS64_ISS_DIR_READ)
	231
6126ce05 MZ	232	#define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) \| \
6126ce05 MZ	233	ESR_ELx_SYS64_ISS_DIR_READ)
9842119a MZ	234
	235	#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) \| \
	236	ESR_ELx_SYS64_ISS_DIR_READ)
	237
d251f67a MZ	238	#define esr_sys64_to_sysreg(e) \
	239	sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \
	240	ESR_ELx_SYS64_ISS_OP0_SHIFT), \
	241	(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
	242	ESR_ELx_SYS64_ISS_OP1_SHIFT), \
	243	(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
	244	ESR_ELx_SYS64_ISS_CRN_SHIFT), \
	245	(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
	246	ESR_ELx_SYS64_ISS_CRM_SHIFT), \
	247	(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
	248	ESR_ELx_SYS64_ISS_OP2_SHIFT))
	249
	250	#define esr_cp15_to_sysreg(e) \
	251	sys_reg(3, \
	252	(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
	253	ESR_ELx_SYS64_ISS_OP1_SHIFT), \
	254	(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
	255	ESR_ELx_SYS64_ISS_CRN_SHIFT), \
	256	(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
	257	ESR_ELx_SYS64_ISS_CRM_SHIFT), \
	258	(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
	259	ESR_ELx_SYS64_ISS_OP2_SHIFT))
	260
af4a81b9 DM	261	/*
	262	* ISS field definitions for floating-point exception traps
	263	* (FP_EXC_32/FP_EXC_64).
	264	*
	265	* (The FPEXC_* constants are used instead for common bits.)
	266	*/
	267
	268	#define ESR_ELx_FP_EXC_TFV (UL(1) << 23)
	269
bd7ac140 MZ	270	/*
	271	* ISS field definitions for CP15 accesses
	272	*/
	273	#define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1
	274	#define ESR_ELx_CP15_32_ISS_DIR_READ 0x1
	275	#define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0
	276
	277	#define ESR_ELx_CP15_32_ISS_RT_SHIFT 5
	278	#define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
	279	#define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1
	280	#define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
	281	#define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10
	282	#define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
	283	#define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14
	284	#define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
	285	#define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17
	286	#define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
	287
	288	#define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK \| \
	289	ESR_ELx_CP15_32_ISS_OP2_MASK \| \
	290	ESR_ELx_CP15_32_ISS_CRN_MASK \| \
	291	ESR_ELx_CP15_32_ISS_CRM_MASK \| \
	292	ESR_ELx_CP15_32_ISS_DIR_MASK)
	293	#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
	294	(((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) \| \
	295	((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) \| \
	296	((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) \| \
	297	((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
	298
	299	#define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1
	300	#define ESR_ELx_CP15_64_ISS_DIR_READ 0x1
	301	#define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0
	302
	303	#define ESR_ELx_CP15_64_ISS_RT_SHIFT 5
	304	#define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
	305
	306	#define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10
	307	#define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
	308
	309	#define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16
	310	#define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
	311	#define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1
	312	#define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
	313
	314	#define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
	315	(((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) \| \
	316	((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
	317
	318	#define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK \| \
	319	ESR_ELx_CP15_64_ISS_CRM_MASK \| \
	320	ESR_ELx_CP15_64_ISS_DIR_MASK)
	321
50de013d MZ	322	#define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) \| \
	323	ESR_ELx_CP15_64_ISS_DIR_READ)
	324
32a3e635 MZ	325	#define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) \|\
	326	ESR_ELx_CP15_32_ISS_DIR_READ)
	327
60a1f02c MR	328	#ifndef __ASSEMBLY__
	329	#include <asm/types.h>
	330
1f9b8936 JT	331	static inline bool esr_is_data_abort(u32 esr)
	332	{
	333	const u32 ec = ESR_ELx_EC(esr);
	334
	335	return ec == ESR_ELx_EC_DABT_LOW \|\| ec == ESR_ELx_EC_DABT_CUR;
	336	}
	337
60a1f02c MR	338	const char *esr_get_class_string(u32 esr);
	339	#endif /* __ASSEMBLY */
	340
5c1ce6f7	341	#endif /* __ASM_ESR_H */