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478fcb2c WD |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | #ifndef __ASM_DEBUG_MONITORS_H | |
17 | #define __ASM_DEBUG_MONITORS_H | |
18 | ||
19 | #ifdef __KERNEL__ | |
20 | ||
d7a33f4f DM |
21 | #include <linux/errno.h> |
22 | #include <linux/types.h> | |
f98deee9 | 23 | #include <asm/brk-imm.h> |
03923696 | 24 | #include <asm/esr.h> |
951757ae | 25 | #include <asm/insn.h> |
d7a33f4f | 26 | #include <asm/ptrace.h> |
951757ae | 27 | |
51ba2481 MZ |
28 | /* Low-level stepping controls. */ |
29 | #define DBG_MDSCR_SS (1 << 0) | |
30 | #define DBG_SPSR_SS (1 << 21) | |
31 | ||
32 | /* MDSCR_EL1 enabling bits */ | |
33 | #define DBG_MDSCR_KDE (1 << 13) | |
34 | #define DBG_MDSCR_MDE (1 << 15) | |
35 | #define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE) | |
36 | ||
478fcb2c WD |
37 | #define DBG_ESR_EVT(x) (((x) >> 27) & 0x7) |
38 | ||
39 | /* AArch64 */ | |
40 | #define DBG_ESR_EVT_HWBP 0x0 | |
41 | #define DBG_ESR_EVT_HWSS 0x1 | |
42 | #define DBG_ESR_EVT_HWWP 0x2 | |
43 | #define DBG_ESR_EVT_BRK 0x6 | |
44 | ||
bcf5763b VK |
45 | /* |
46 | * Break point instruction encoding | |
47 | */ | |
951757ae | 48 | #define BREAK_INSTR_SIZE AARCH64_INSN_SIZE |
bcf5763b | 49 | |
bcf5763b VK |
50 | /* |
51 | * BRK instruction encoding | |
52 | * The #imm16 value should be placed at bits[20:5] within BRK ins | |
53 | */ | |
54 | #define AARCH64_BREAK_MON 0xd4200000 | |
55 | ||
a9ae04c9 MB |
56 | /* |
57 | * BRK instruction for provoking a fault on purpose | |
58 | * Unlike kgdb, #imm16 value with unallocated handler is used for faulting. | |
59 | */ | |
60 | #define AARCH64_BREAK_FAULT (AARCH64_BREAK_MON | (FAULT_BRK_IMM << 5)) | |
61 | ||
c696b934 DM |
62 | #define AARCH64_BREAK_KGDB_DYN_DBG \ |
63 | (AARCH64_BREAK_MON | (KGDB_DYN_DBG_BRK_IMM << 5)) | |
64 | #define KGDB_DYN_BRK_INS_BYTE(x) \ | |
65 | ((AARCH64_BREAK_KGDB_DYN_DBG >> (8 * (x))) & 0xff) | |
bcf5763b VK |
66 | |
67 | #define CACHE_FLUSH_IS_SAFE 1 | |
68 | ||
2dd0e8d2 SP |
69 | /* kprobes BRK opcodes with ESR encoding */ |
70 | #define BRK64_ESR_MASK 0xFFFF | |
71 | #define BRK64_ESR_KPROBES 0x0004 | |
72 | #define BRK64_OPCODE_KPROBES (AARCH64_BREAK_MON | (BRK64_ESR_KPROBES << 5)) | |
73 | ||
478fcb2c WD |
74 | /* AArch32 */ |
75 | #define DBG_ESR_EVT_BKPT 0x4 | |
76 | #define DBG_ESR_EVT_VECC 0x5 | |
77 | ||
78 | #define AARCH32_BREAK_ARM 0x07f001f0 | |
79 | #define AARCH32_BREAK_THUMB 0xde01 | |
80 | #define AARCH32_BREAK_THUMB2_LO 0xf7f0 | |
81 | #define AARCH32_BREAK_THUMB2_HI 0xa000 | |
82 | ||
83 | #ifndef __ASSEMBLY__ | |
84 | struct task_struct; | |
85 | ||
478fcb2c WD |
86 | #define DBG_ARCH_ID_RESERVED 0 /* In case of ptrace ABI updates. */ |
87 | ||
ee6214ce SP |
88 | #define DBG_HOOK_HANDLED 0 |
89 | #define DBG_HOOK_ERROR 1 | |
90 | ||
91 | struct step_hook { | |
92 | struct list_head node; | |
93 | int (*fn)(struct pt_regs *regs, unsigned int esr); | |
94 | }; | |
95 | ||
96 | void register_step_hook(struct step_hook *hook); | |
97 | void unregister_step_hook(struct step_hook *hook); | |
98 | ||
99 | struct break_hook { | |
100 | struct list_head node; | |
101 | u32 esr_val; | |
102 | u32 esr_mask; | |
103 | int (*fn)(struct pt_regs *regs, unsigned int esr); | |
104 | }; | |
105 | ||
106 | void register_break_hook(struct break_hook *hook); | |
107 | void unregister_break_hook(struct break_hook *hook); | |
108 | ||
478fcb2c WD |
109 | u8 debug_monitors_arch(void); |
110 | ||
6f883d10 | 111 | enum dbg_active_el { |
51ba2481 MZ |
112 | DBG_ACTIVE_EL0 = 0, |
113 | DBG_ACTIVE_EL1, | |
114 | }; | |
115 | ||
6f883d10 WD |
116 | void enable_debug_monitors(enum dbg_active_el el); |
117 | void disable_debug_monitors(enum dbg_active_el el); | |
478fcb2c WD |
118 | |
119 | void user_rewind_single_step(struct task_struct *task); | |
120 | void user_fastforward_single_step(struct task_struct *task); | |
121 | ||
122 | void kernel_enable_single_step(struct pt_regs *regs); | |
123 | void kernel_disable_single_step(void); | |
124 | int kernel_active_single_step(void); | |
125 | ||
126 | #ifdef CONFIG_HAVE_HW_BREAKPOINT | |
127 | int reinstall_suspended_bps(struct pt_regs *regs); | |
128 | #else | |
129 | static inline int reinstall_suspended_bps(struct pt_regs *regs) | |
130 | { | |
131 | return -ENODEV; | |
132 | } | |
133 | #endif | |
134 | ||
1442b6ed | 135 | int aarch32_break_handler(struct pt_regs *regs); |
1442b6ed | 136 | |
478fcb2c WD |
137 | #endif /* __ASSEMBLY */ |
138 | #endif /* __KERNEL__ */ | |
139 | #endif /* __ASM_DEBUG_MONITORS_H */ |