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f1a0c4aa CM |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | #ifndef __ASM_CACHE_H | |
17 | #define __ASM_CACHE_H | |
18 | ||
02f7760e WD |
19 | #include <asm/cputype.h> |
20 | ||
21 | #define CTR_L1IP_SHIFT 14 | |
22 | #define CTR_L1IP_MASK 3 | |
6ae4b6e0 | 23 | #define CTR_DMINLINE_SHIFT 16 |
4c4a39dd | 24 | #define CTR_IMINLINE_SHIFT 0 |
6ae4b6e0 | 25 | #define CTR_ERG_SHIFT 20 |
02f7760e WD |
26 | #define CTR_CWG_SHIFT 24 |
27 | #define CTR_CWG_MASK 15 | |
6ae4b6e0 SD |
28 | #define CTR_IDC_SHIFT 28 |
29 | #define CTR_DIC_SHIFT 29 | |
02f7760e | 30 | |
4c4a39dd SP |
31 | #define CTR_CACHE_MINLINE_MASK \ |
32 | (0xf << CTR_DMINLINE_SHIFT | 0xf << CTR_IMINLINE_SHIFT) | |
33 | ||
02f7760e WD |
34 | #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) |
35 | ||
dda288d7 | 36 | #define ICACHE_POLICY_VPIPT 0 |
02f7760e WD |
37 | #define ICACHE_POLICY_VIPT 2 |
38 | #define ICACHE_POLICY_PIPT 3 | |
a41dc0e8 | 39 | |
d93277b9 | 40 | #define L1_CACHE_SHIFT (6) |
f1a0c4aa CM |
41 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) |
42 | ||
1602df02 SP |
43 | |
44 | #define CLIDR_LOUU_SHIFT 27 | |
45 | #define CLIDR_LOC_SHIFT 24 | |
46 | #define CLIDR_LOUIS_SHIFT 21 | |
47 | ||
48 | #define CLIDR_LOUU(clidr) (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7) | |
49 | #define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7) | |
50 | #define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7) | |
51 | ||
f1a0c4aa CM |
52 | /* |
53 | * Memory returned by kmalloc() may be used for DMA, so we must make | |
54 | * sure that all such allocations are cache aligned. Otherwise, | |
55 | * unrelated code may cause parts of the buffer to be read into the | |
56 | * cache before the transfer is done, causing old data to be seen by | |
57 | * the CPU. | |
58 | */ | |
ebc7e21e | 59 | #define ARCH_DMA_MINALIGN (128) |
a41dc0e8 | 60 | |
eb214f2d AK |
61 | #ifdef CONFIG_KASAN_SW_TAGS |
62 | #define ARCH_SLAB_MINALIGN (1ULL << KASAN_SHADOW_SCALE_SHIFT) | |
63 | #else | |
64 | #define ARCH_SLAB_MINALIGN __alignof__(unsigned long long) | |
65 | #endif | |
66 | ||
a41dc0e8 CM |
67 | #ifndef __ASSEMBLY__ |
68 | ||
02f7760e WD |
69 | #include <linux/bitops.h> |
70 | ||
71 | #define ICACHEF_ALIASING 0 | |
dda288d7 | 72 | #define ICACHEF_VPIPT 1 |
02f7760e WD |
73 | extern unsigned long __icache_flags; |
74 | ||
75 | /* | |
76 | * Whilst the D-side always behaves as PIPT on AArch64, aliasing is | |
77 | * permitted in the I-cache. | |
78 | */ | |
79 | static inline int icache_is_aliasing(void) | |
80 | { | |
81 | return test_bit(ICACHEF_ALIASING, &__icache_flags); | |
82 | } | |
83 | ||
dda288d7 WD |
84 | static inline int icache_is_vpipt(void) |
85 | { | |
86 | return test_bit(ICACHEF_VPIPT, &__icache_flags); | |
87 | } | |
88 | ||
02f7760e WD |
89 | static inline u32 cache_type_cwg(void) |
90 | { | |
91 | return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; | |
92 | } | |
93 | ||
e4f88d83 JL |
94 | #define __read_mostly __attribute__((__section__(".data..read_mostly"))) |
95 | ||
a41dc0e8 CM |
96 | static inline int cache_line_size(void) |
97 | { | |
98 | u32 cwg = cache_type_cwg(); | |
ebc7e21e | 99 | return cwg ? 4 << cwg : ARCH_DMA_MINALIGN; |
a41dc0e8 CM |
100 | } |
101 | ||
1602df02 SP |
102 | /* |
103 | * Read the effective value of CTR_EL0. | |
104 | * | |
105 | * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a), | |
106 | * section D10.2.33 "CTR_EL0, Cache Type Register" : | |
107 | * | |
108 | * CTR_EL0.IDC reports the data cache clean requirements for | |
109 | * instruction to data coherence. | |
110 | * | |
111 | * 0 - dcache clean to PoU is required unless : | |
112 | * (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0) | |
113 | * 1 - dcache clean to PoU is not required for i-to-d coherence. | |
114 | * | |
115 | * This routine provides the CTR_EL0 with the IDC field updated to the | |
116 | * effective state. | |
117 | */ | |
118 | static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void) | |
119 | { | |
120 | u32 ctr = read_cpuid_cachetype(); | |
121 | ||
122 | if (!(ctr & BIT(CTR_IDC_SHIFT))) { | |
123 | u64 clidr = read_sysreg(clidr_el1); | |
124 | ||
125 | if (CLIDR_LOC(clidr) == 0 || | |
126 | (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0)) | |
127 | ctr |= BIT(CTR_IDC_SHIFT); | |
128 | } | |
129 | ||
130 | return ctr; | |
131 | } | |
132 | ||
a41dc0e8 | 133 | #endif /* __ASSEMBLY__ */ |
f1a0c4aa CM |
134 | |
135 | #endif |