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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
e039ee4e AP |
2 | #ifndef __ASM_ALTERNATIVE_H |
3 | #define __ASM_ALTERNATIVE_H | |
4 | ||
272d01bd | 5 | #include <asm/cpucaps.h> |
792d4737 | 6 | #include <asm/insn.h> |
57f4959b | 7 | |
dea5e2a4 MZ |
8 | #define ARM64_CB_PATCH ARM64_NCAPS |
9 | ||
8d883b23 MZ |
10 | #ifndef __ASSEMBLY__ |
11 | ||
ef5e724b | 12 | #include <linux/init.h> |
e039ee4e AP |
13 | #include <linux/types.h> |
14 | #include <linux/stddef.h> | |
15 | #include <linux/stringify.h> | |
16 | ||
17 | struct alt_instr { | |
18 | s32 orig_offset; /* offset to original instruction */ | |
19 | s32 alt_offset; /* offset to replacement instruction */ | |
20 | u16 cpufeature; /* cpufeature bit set for replacement */ | |
21 | u8 orig_len; /* size of original instruction(s) */ | |
22 | u8 alt_len; /* size of new instruction(s), <= orig_len */ | |
23 | }; | |
24 | ||
dea5e2a4 MZ |
25 | typedef void (*alternative_cb_t)(struct alt_instr *alt, |
26 | __le32 *origptr, __le32 *updptr, int nr_inst); | |
27 | ||
0ceb0d56 | 28 | void __init apply_boot_alternatives(void); |
ef5e724b | 29 | void __init apply_alternatives_all(void); |
e9ab7a2e | 30 | bool alternative_is_applied(u16 cpufeature); |
42938868 WD |
31 | |
32 | #ifdef CONFIG_MODULES | |
33 | void apply_alternatives_module(void *start, size_t length); | |
34 | #else | |
35 | static inline void apply_alternatives_module(void *start, size_t length) { } | |
36 | #endif | |
e039ee4e | 37 | |
c54f90c2 | 38 | #define ALTINSTR_ENTRY(feature) \ |
e039ee4e AP |
39 | " .word 661b - .\n" /* label */ \ |
40 | " .word 663f - .\n" /* new instruction */ \ | |
c54f90c2 ST |
41 | " .hword " __stringify(feature) "\n" /* feature bit */ \ |
42 | " .byte 662b-661b\n" /* source len */ \ | |
43 | " .byte 664f-663f\n" /* replacement len */ | |
44 | ||
45 | #define ALTINSTR_ENTRY_CB(feature, cb) \ | |
46 | " .word 661b - .\n" /* label */ \ | |
dea5e2a4 | 47 | " .word " __stringify(cb) "- .\n" /* callback */ \ |
e039ee4e AP |
48 | " .hword " __stringify(feature) "\n" /* feature bit */ \ |
49 | " .byte 662b-661b\n" /* source len */ \ | |
50 | " .byte 664f-663f\n" /* replacement len */ | |
51 | ||
eb7c11ee MZ |
52 | /* |
53 | * alternative assembly primitive: | |
54 | * | |
55 | * If any of these .org directive fail, it means that insn1 and insn2 | |
56 | * don't have the same length. This used to be written as | |
57 | * | |
58 | * .if ((664b-663b) != (662b-661b)) | |
59 | * .error "Alternatives instruction length mismatch" | |
60 | * .endif | |
61 | * | |
62 | * but most assemblers die if insn1 or insn2 have a .inst. This should | |
63 | * be fixed in a binutils release posterior to 2.25.51.0.2 (anything | |
64 | * containing commit 4e4d08cf7399b606 or c1baaddf8861). | |
dea5e2a4 MZ |
65 | * |
66 | * Alternatives with callbacks do not generate replacement instructions. | |
eb7c11ee | 67 | */ |
c54f90c2 | 68 | #define __ALTERNATIVE_CFG(oldinstr, newinstr, feature, cfg_enabled) \ |
91a5cefa | 69 | ".if "__stringify(cfg_enabled)" == 1\n" \ |
e039ee4e AP |
70 | "661:\n\t" \ |
71 | oldinstr "\n" \ | |
72 | "662:\n" \ | |
73 | ".pushsection .altinstructions,\"a\"\n" \ | |
c54f90c2 | 74 | ALTINSTR_ENTRY(feature) \ |
e039ee4e | 75 | ".popsection\n" \ |
f7b93d42 | 76 | ".subsection 1\n" \ |
e039ee4e AP |
77 | "663:\n\t" \ |
78 | newinstr "\n" \ | |
79 | "664:\n\t" \ | |
eb7c11ee | 80 | ".org . - (664b-663b) + (662b-661b)\n\t" \ |
966a0acc ST |
81 | ".org . - (662b-661b) + (664b-663b)\n\t" \ |
82 | ".previous\n" \ | |
c54f90c2 ST |
83 | ".endif\n" |
84 | ||
85 | #define __ALTERNATIVE_CFG_CB(oldinstr, feature, cfg_enabled, cb) \ | |
86 | ".if "__stringify(cfg_enabled)" == 1\n" \ | |
87 | "661:\n\t" \ | |
88 | oldinstr "\n" \ | |
89 | "662:\n" \ | |
90 | ".pushsection .altinstructions,\"a\"\n" \ | |
91 | ALTINSTR_ENTRY_CB(feature, cb) \ | |
92 | ".popsection\n" \ | |
dea5e2a4 MZ |
93 | "663:\n\t" \ |
94 | "664:\n\t" \ | |
91a5cefa JM |
95 | ".endif\n" |
96 | ||
97 | #define _ALTERNATIVE_CFG(oldinstr, newinstr, feature, cfg, ...) \ | |
c54f90c2 | 98 | __ALTERNATIVE_CFG(oldinstr, newinstr, feature, IS_ENABLED(cfg)) |
e039ee4e | 99 | |
dea5e2a4 | 100 | #define ALTERNATIVE_CB(oldinstr, cb) \ |
c54f90c2 | 101 | __ALTERNATIVE_CFG_CB(oldinstr, ARM64_CB_PATCH, 1, cb) |
8d883b23 MZ |
102 | #else |
103 | ||
57f4959b JM |
104 | #include <asm/assembler.h> |
105 | ||
8d883b23 MZ |
106 | .macro altinstruction_entry orig_offset alt_offset feature orig_len alt_len |
107 | .word \orig_offset - . | |
108 | .word \alt_offset - . | |
109 | .hword \feature | |
110 | .byte \orig_len | |
111 | .byte \alt_len | |
112 | .endm | |
113 | ||
91a5cefa JM |
114 | .macro alternative_insn insn1, insn2, cap, enable = 1 |
115 | .if \enable | |
8d883b23 MZ |
116 | 661: \insn1 |
117 | 662: .pushsection .altinstructions, "a" | |
118 | altinstruction_entry 661b, 663f, \cap, 662b-661b, 664f-663f | |
119 | .popsection | |
f7b93d42 | 120 | .subsection 1 |
8d883b23 | 121 | 663: \insn2 |
f7b93d42 | 122 | 664: .previous |
eb7c11ee MZ |
123 | .org . - (664b-663b) + (662b-661b) |
124 | .org . - (662b-661b) + (664b-663b) | |
91a5cefa | 125 | .endif |
8d883b23 MZ |
126 | .endm |
127 | ||
63e40815 | 128 | /* |
792d4737 MR |
129 | * Alternative sequences |
130 | * | |
131 | * The code for the case where the capability is not present will be | |
132 | * assembled and linked as normal. There are no restrictions on this | |
133 | * code. | |
134 | * | |
135 | * The code for the case where the capability is present will be | |
136 | * assembled into a special section to be used for dynamic patching. | |
137 | * Code for that case must: | |
138 | * | |
139 | * 1. Be exactly the same length (in bytes) as the default code | |
140 | * sequence. | |
63e40815 | 141 | * |
792d4737 MR |
142 | * 2. Not contain a branch target that is used outside of the |
143 | * alternative sequence it is defined in (branches into an | |
144 | * alternative sequence are not fixed up). | |
145 | */ | |
146 | ||
147 | /* | |
148 | * Begin an alternative code sequence. | |
63e40815 | 149 | */ |
b82bfa47 | 150 | .macro alternative_if_not cap |
792d4737 | 151 | .set .Lasm_alt_mode, 0 |
63e40815 DT |
152 | .pushsection .altinstructions, "a" |
153 | altinstruction_entry 661f, 663f, \cap, 662f-661f, 664f-663f | |
154 | .popsection | |
155 | 661: | |
156 | .endm | |
157 | ||
792d4737 MR |
158 | .macro alternative_if cap |
159 | .set .Lasm_alt_mode, 1 | |
160 | .pushsection .altinstructions, "a" | |
161 | altinstruction_entry 663f, 661f, \cap, 664f-663f, 662f-661f | |
162 | .popsection | |
f7b93d42 | 163 | .subsection 1 |
792d4737 MR |
164 | .align 2 /* So GAS knows label 661 is suitably aligned */ |
165 | 661: | |
166 | .endm | |
167 | ||
dea5e2a4 MZ |
168 | .macro alternative_cb cb |
169 | .set .Lasm_alt_mode, 0 | |
170 | .pushsection .altinstructions, "a" | |
171 | altinstruction_entry 661f, \cb, ARM64_CB_PATCH, 662f-661f, 0 | |
172 | .popsection | |
173 | 661: | |
174 | .endm | |
175 | ||
63e40815 | 176 | /* |
792d4737 | 177 | * Provide the other half of the alternative code sequence. |
63e40815 | 178 | */ |
b82bfa47 | 179 | .macro alternative_else |
792d4737 MR |
180 | 662: |
181 | .if .Lasm_alt_mode==0 | |
f7b93d42 | 182 | .subsection 1 |
792d4737 | 183 | .else |
f7b93d42 | 184 | .previous |
792d4737 | 185 | .endif |
63e40815 DT |
186 | 663: |
187 | .endm | |
188 | ||
189 | /* | |
190 | * Complete an alternative code sequence. | |
191 | */ | |
b82bfa47 | 192 | .macro alternative_endif |
792d4737 MR |
193 | 664: |
194 | .if .Lasm_alt_mode==0 | |
f7b93d42 | 195 | .previous |
792d4737 | 196 | .endif |
63e40815 DT |
197 | .org . - (664b-663b) + (662b-661b) |
198 | .org . - (662b-661b) + (664b-663b) | |
199 | .endm | |
200 | ||
dea5e2a4 MZ |
201 | /* |
202 | * Callback-based alternative epilogue | |
203 | */ | |
204 | .macro alternative_cb_end | |
205 | 662: | |
206 | .endm | |
207 | ||
792d4737 MR |
208 | /* |
209 | * Provides a trivial alternative or default sequence consisting solely | |
210 | * of NOPs. The number of NOPs is chosen automatically to match the | |
211 | * previous case. | |
212 | */ | |
213 | .macro alternative_else_nop_endif | |
214 | alternative_else | |
215 | nops (662b-661b) / AARCH64_INSN_SIZE | |
216 | alternative_endif | |
217 | .endm | |
218 | ||
91a5cefa JM |
219 | #define _ALTERNATIVE_CFG(insn1, insn2, cap, cfg, ...) \ |
220 | alternative_insn insn1, insn2, cap, IS_ENABLED(cfg) | |
221 | ||
290622ef AP |
222 | .macro user_alt, label, oldinstr, newinstr, cond |
223 | 9999: alternative_insn "\oldinstr", "\newinstr", \cond | |
6f5459da | 224 | _asm_extable 9999b, \label |
290622ef | 225 | .endm |
91a5cefa | 226 | |
8d883b23 MZ |
227 | #endif /* __ASSEMBLY__ */ |
228 | ||
91a5cefa JM |
229 | /* |
230 | * Usage: asm(ALTERNATIVE(oldinstr, newinstr, feature)); | |
231 | * | |
232 | * Usage: asm(ALTERNATIVE(oldinstr, newinstr, feature, CONFIG_FOO)); | |
233 | * N.B. If CONFIG_FOO is specified, but not selected, the whole block | |
234 | * will be omitted, including oldinstr. | |
235 | */ | |
236 | #define ALTERNATIVE(oldinstr, newinstr, ...) \ | |
237 | _ALTERNATIVE_CFG(oldinstr, newinstr, __VA_ARGS__, 1) | |
238 | ||
e039ee4e | 239 | #endif /* __ASM_ALTERNATIVE_H */ |