[linux-2.6-block.git] / arch / arm64 / boot / dts / ti / k3-j721e.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for J721E SoC Family
 *
 * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>

/ {
	model = "Texas Instruments K3 J721E SoC";
	compatible = "ti,j721e";
	interrupt-parent = <&gic500>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &wkup_uart0;
		serial1 = &mcu_uart0;
		serial2 = &main_uart0;
		serial3 = &main_uart1;
		serial4 = &main_uart2;
		serial5 = &main_uart3;
		serial6 = &main_uart4;
		serial7 = &main_uart5;
		serial8 = &main_uart6;
		serial9 = &main_uart7;
		serial10 = &main_uart8;
		serial11 = &main_uart9;
	};

	chosen { };

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu-map {
			cluster0: cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};
			};

		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a72";
			reg = <0x000>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xC000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&L2_0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a72";
			reg = <0x001>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xC000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&L2_0>;
		};
	};

	L2_0: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		cache-size = <0x100000>;
		cache-line-size = <64>;
		cache-sets = <2048>;
		next-level-cache = <&msmc_l3>;
	};

	msmc_l3: l3-cache0 {
		compatible = "cache";
		cache-level = <3>;
	};

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};

		psci: psci {
			compatible = "arm,psci-1.0";
			method = "smc";
		};
	};

	a72_timer0: timer-cl0-cpu0 {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
	};

	pmu: pmu {
		compatible = "arm,armv8-pmuv3";
		/* Recommendation from GIC500 TRM Table A.3 */
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	cbass_main: interconnect@100000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
			 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
			 <0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */
			 <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
			 <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */
			 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
			 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
			 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
			 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
			 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
			 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
			 <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */
			 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */

			 /* MCUSS_WKUP Range */
			 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
			 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
			 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
			 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
			 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
			 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
			 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
			 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
			 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
			 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
			 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
			 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;

		cbass_mcu_wakeup: interconnect@28380000 {
			compatible = "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
				 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
				 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
				 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
				 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
				 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
				 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
				 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
				 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
				 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
				 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
				 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
				 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
		};
	};
};

/* Now include the peripherals for each bus segments */
#include "k3-j721e-main.dtsi"
#include "k3-j721e-mcu-wakeup.dtsi"
Commit	Line	Data
2d87061e NM	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Device Tree Source for J721E SoC Family
	4	*
	5	* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
	6	*/
	7
	8	#include <dt-bindings/interrupt-controller/irq.h>
	9	#include <dt-bindings/interrupt-controller/arm-gic.h>
	10	#include <dt-bindings/pinctrl/k3.h>
bf146a1a	11	#include <dt-bindings/soc/ti,sci_pm_domain.h>
2d87061e NM	12
	13	/ {
	14	model = "Texas Instruments K3 J721E SoC";
	15	compatible = "ti,j721e";
	16	interrupt-parent = <&gic500>;
	17	#address-cells = <2>;
	18	#size-cells = <2>;
	19
	20	aliases {
	21	serial0 = &wkup_uart0;
	22	serial1 = &mcu_uart0;
	23	serial2 = &main_uart0;
	24	serial3 = &main_uart1;
	25	serial4 = &main_uart2;
	26	serial5 = &main_uart3;
	27	serial6 = &main_uart4;
	28	serial7 = &main_uart5;
	29	serial8 = &main_uart6;
	30	serial9 = &main_uart7;
	31	serial10 = &main_uart8;
	32	serial11 = &main_uart9;
	33	};
	34
	35	chosen { };
	36
	37	cpus {
	38	#address-cells = <1>;
	39	#size-cells = <0>;
	40	cpu-map {
	41	cluster0: cluster0 {
	42	core0 {
	43	cpu = <&cpu0>;
	44	};
	45
	46	core1 {
	47	cpu = <&cpu1>;
	48	};
	49	};
	50
	51	};
	52
	53	cpu0: cpu@0 {
	54	compatible = "arm,cortex-a72";
	55	reg = <0x000>;
	56	device_type = "cpu";
	57	enable-method = "psci";
	58	i-cache-size = <0xC000>;
	59	i-cache-line-size = <64>;
	60	i-cache-sets = <256>;
	61	d-cache-size = <0x8000>;
	62	d-cache-line-size = <64>;
	63	d-cache-sets = <128>;
	64	next-level-cache = <&L2_0>;
	65	};
	66
	67	cpu1: cpu@1 {
	68	compatible = "arm,cortex-a72";
	69	reg = <0x001>;
	70	device_type = "cpu";
	71	enable-method = "psci";
	72	i-cache-size = <0xC000>;
	73	i-cache-line-size = <64>;
	74	i-cache-sets = <256>;
	75	d-cache-size = <0x8000>;
76	d-cache-line-size = <64>;
77	d-cache-sets = <128>;
78	next-level-cache = <&L2_0>;
79	};
80	};
81
82	L2_0: l2-cache0 {
83	compatible = "cache";
84	cache-level = <2>;
85	cache-size = <0x100000>;
86	cache-line-size = <64>;
87	cache-sets = <2048>;
88	next-level-cache = <&msmc_l3>;
89	};
90
91	msmc_l3: l3-cache0 {
92	compatible = "cache";
93	cache-level = <3>;
94	};
95
96	firmware {
97	optee {
98	compatible = "linaro,optee-tz";
99	method = "smc";
100	};
101
102	psci: psci {
103	compatible = "arm,psci-1.0";
104	method = "smc";
105	};
106	};
107
108	a72_timer0: timer-cl0-cpu0 {
109	compatible = "arm,armv8-timer";
110	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
111	<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
112	<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
113	<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
114	};
115
116	pmu: pmu {
117	compatible = "arm,armv8-pmuv3";
118	/* Recommendation from GIC500 TRM Table A.3 */
119	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
120	};
121
122	cbass_main: interconnect@100000 {
123	compatible = "simple-bus";
124	#address-cells = <2>;
125	#size-cells = <2>;
126	ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
127	<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
128	<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
129	<0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */
451555c8 RQ	130	<0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
451555c8 RQ	131	<0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */
2d87061e NM	132	<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
	133	<0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
	134	<0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
	135	<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
	136	<0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
	137	<0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
	138	<0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */
	139	<0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
	140	<0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
	141
	142	/* MCUSS_WKUP Range */
	143	<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
	144	<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
	145	<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
	146	<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
	147	<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
	148	<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
	149	<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
	150	<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
	151	<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
	152	<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
	153	<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
	154	<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
	155	<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
	156
	157	cbass_mcu_wakeup: interconnect@28380000 {
	158	compatible = "simple-bus";
	159	#address-cells = <2>;
	160	#size-cells = <2>;
	161	ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
	162	<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
	163	<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
	164	<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
	165	<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
	166	<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
	167	<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
	168	<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
	169	<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
	170	<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
	171	<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
	172	<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
	173	<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
	174	};
	175	};
	176	};
	177
	178	/* Now include the peripherals for each bus segments */
	179	#include "k3-j721e-main.dtsi"
	180	#include "k3-j721e-mcu-wakeup.dtsi"