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2d87061e NM |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals | |
4 | * | |
5 | * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ | |
6 | */ | |
7 | ||
8 | &cbass_mcu_wakeup { | |
9 | dmsc: dmsc@44083000 { | |
10 | compatible = "ti,k2g-sci"; | |
11 | ti,host-id = <12>; | |
12 | ||
13 | mbox-names = "rx", "tx"; | |
14 | ||
15 | mboxes= <&secure_proxy_main 11>, | |
16 | <&secure_proxy_main 13>; | |
17 | ||
18 | reg-names = "debug_messages"; | |
19 | reg = <0x00 0x44083000 0x0 0x1000>; | |
20 | ||
21 | k3_pds: power-controller { | |
22 | compatible = "ti,sci-pm-domain"; | |
23 | #power-domain-cells = <1>; | |
24 | }; | |
25 | ||
26 | k3_clks: clocks { | |
27 | compatible = "ti,k2g-sci-clk"; | |
28 | #clock-cells = <2>; | |
29 | }; | |
30 | ||
31 | k3_reset: reset-controller { | |
32 | compatible = "ti,sci-reset"; | |
33 | #reset-cells = <2>; | |
34 | }; | |
35 | }; | |
36 | ||
37 | wkup_pmx0: pinmux@4301c000 { | |
38 | compatible = "pinctrl-single"; | |
39 | /* Proxy 0 addressing */ | |
40 | reg = <0x00 0x4301c000 0x00 0x178>; | |
41 | #pinctrl-cells = <1>; | |
42 | pinctrl-single,register-width = <32>; | |
43 | pinctrl-single,function-mask = <0xffffffff>; | |
44 | }; | |
45 | ||
78eccc2a SA |
46 | mcu_ram: sram@41c00000 { |
47 | compatible = "mmio-sram"; | |
48 | reg = <0x00 0x41c00000 0x00 0x100000>; | |
49 | ranges = <0x0 0x00 0x41c00000 0x100000>; | |
50 | #address-cells = <1>; | |
51 | #size-cells = <1>; | |
52 | }; | |
53 | ||
2d87061e NM |
54 | wkup_uart0: serial@42300000 { |
55 | compatible = "ti,j721e-uart", "ti,am654-uart"; | |
56 | reg = <0x00 0x42300000 0x00 0x100>; | |
57 | reg-shift = <2>; | |
58 | reg-io-width = <4>; | |
59 | interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; | |
60 | clock-frequency = <48000000>; | |
61 | current-speed = <115200>; | |
62 | power-domains = <&k3_pds 287>; | |
63 | clocks = <&k3_clks 287 0>; | |
64 | clock-names = "fclk"; | |
65 | }; | |
66 | ||
67 | mcu_uart0: serial@40a00000 { | |
68 | compatible = "ti,j721e-uart", "ti,am654-uart"; | |
69 | reg = <0x00 0x40a00000 0x00 0x100>; | |
70 | reg-shift = <2>; | |
71 | reg-io-width = <4>; | |
72 | interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; | |
73 | clock-frequency = <96000000>; | |
74 | current-speed = <115200>; | |
75 | power-domains = <&k3_pds 149>; | |
76 | clocks = <&k3_clks 149 0>; | |
77 | clock-names = "fclk"; | |
78 | }; | |
ae7d8505 LV |
79 | |
80 | wkup_gpio_intr: interrupt-controller2 { | |
81 | compatible = "ti,sci-intr"; | |
82 | ti,intr-trigger-type = <1>; | |
83 | interrupt-controller; | |
84 | interrupt-parent = <&gic500>; | |
85 | #interrupt-cells = <2>; | |
86 | ti,sci = <&dmsc>; | |
87 | ti,sci-dst-id = <14>; | |
88 | ti,sci-rm-range-girq = <0x5>; | |
89 | }; | |
2d87061e | 90 | }; |