[linux-block.git] / arch / arm64 / boot / dts / ti / k3-j721e-mcu-wakeup.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
 *
 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
 */

&cbass_mcu_wakeup {
	dmsc: system-controller@44083000 {
		compatible = "ti,k2g-sci";
		ti,host-id = <12>;

		mbox-names = "rx", "tx";

		mboxes = <&secure_proxy_main 11>,
			 <&secure_proxy_main 13>;

		reg-names = "debug_messages";
		reg = <0x00 0x44083000 0x0 0x1000>;

		k3_pds: power-controller {
			compatible = "ti,sci-pm-domain";
			#power-domain-cells = <2>;
		};

		k3_clks: clock-controller {
			compatible = "ti,k2g-sci-clk";
			#clock-cells = <2>;
		};

		k3_reset: reset-controller {
			compatible = "ti,sci-reset";
			#reset-cells = <2>;
		};
	};

	mcu_conf: syscon@40f00000 {
		compatible = "syscon", "simple-mfd";
		reg = <0x0 0x40f00000 0x0 0x20000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x40f00000 0x20000>;

		phy_gmii_sel: phy@4040 {
			compatible = "ti,am654-phy-gmii-sel";
			reg = <0x4040 0x4>;
			#phy-cells = <1>;
		};
	};

	chipid@43000014 {
		compatible = "ti,am654-chipid";
		reg = <0x0 0x43000014 0x0 0x4>;
	};

	wkup_pmx0: pinctrl@4301c000 {
		compatible = "pinctrl-single";
		/* Proxy 0 addressing */
		reg = <0x00 0x4301c000 0x00 0x178>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	mcu_ram: sram@41c00000 {
		compatible = "mmio-sram";
		reg = <0x00 0x41c00000 0x00 0x100000>;
		ranges = <0x0 0x00 0x41c00000 0x100000>;
		#address-cells = <1>;
		#size-cells = <1>;
	};

	wkup_uart0: serial@42300000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x42300000 0x00 0x100>;
		interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 287 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	mcu_uart0: serial@40a00000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x40a00000 0x00 0x100>;
		interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <96000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 149 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	wkup_gpio_intr: interrupt-controller@42200000 {
		compatible = "ti,sci-intr";
		reg = <0x00 0x42200000 0x00 0x400>;
		ti,intr-trigger-type = <1>;
		interrupt-controller;
		interrupt-parent = <&gic500>;
		#interrupt-cells = <1>;
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <137>;
		ti,interrupt-ranges = <16 960 16>;
	};

	wkup_gpio0: gpio@42110000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x42110000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&wkup_gpio_intr>;
		interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <84>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 113 0>;
		clock-names = "gpio";
	};

	wkup_gpio1: gpio@42100000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x42100000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&wkup_gpio_intr>;
		interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <84>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 114 0>;
		clock-names = "gpio";
	};

	mcu_i2c0: i2c@40b00000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x40b00000 0x0 0x100>;
		interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 194 0>;
		power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcu_i2c1: i2c@40b10000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x40b10000 0x0 0x100>;
		interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 195 0>;
		power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	wkup_i2c0: i2c@42120000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x42120000 0x0 0x100>;
		interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 197 0>;
		power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
		status = "disabled";
	};

	fss: fss@47000000 {
		compatible = "simple-bus";
		reg = <0x0 0x47000000 0x0 0x100>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ospi0: spi@47040000 {
			compatible = "ti,am654-ospi", "cdns,qspi-nor";
			reg = <0x0 0x47040000 0x0 0x100>,
				<0x5 0x00000000 0x1 0x0000000>;
			interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
			cdns,fifo-depth = <256>;
			cdns,fifo-width = <4>;
			cdns,trigger-address = <0x0>;
			clocks = <&k3_clks 103 0>;
			assigned-clocks = <&k3_clks 103 0>;
			assigned-clock-parents = <&k3_clks 103 2>;
			assigned-clock-rates = <166666666>;
			power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		ospi1: spi@47050000 {
			compatible = "ti,am654-ospi", "cdns,qspi-nor";
			reg = <0x0 0x47050000 0x0 0x100>,
				<0x7 0x00000000 0x1 0x00000000>;
			interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
			cdns,fifo-depth = <256>;
			cdns,fifo-width = <4>;
			cdns,trigger-address = <0x0>;
			clocks = <&k3_clks 104 0>;
			power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	tscadc0: tscadc@40200000 {
		compatible = "ti,am3359-tscadc";
		reg = <0x0 0x40200000 0x0 0x1000>;
		interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 0 1>;
		assigned-clocks = <&k3_clks 0 3>;
		assigned-clock-rates = <60000000>;
		clock-names = "fck";
		dmas = <&main_udmap 0x7400>,
			<&main_udmap 0x7401>;
		dma-names = "fifo0", "fifo1";

		adc {
			#io-channel-cells = <1>;
			compatible = "ti,am3359-adc";
		};
	};

	tscadc1: tscadc@40210000 {
		compatible = "ti,am3359-tscadc";
		reg = <0x0 0x40210000 0x0 0x1000>;
		interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 1 1>;
		assigned-clocks = <&k3_clks 1 3>;
		assigned-clock-rates = <60000000>;
		clock-names = "fck";
		dmas = <&main_udmap 0x7402>,
			<&main_udmap 0x7403>;
		dma-names = "fifo0", "fifo1";

		adc {
			#io-channel-cells = <1>;
			compatible = "ti,am3359-adc";
		};
	};

	mcu_navss: bus@28380000 {
		compatible = "simple-mfd";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
		dma-coherent;
		dma-ranges;

		ti,sci-dev-id = <232>;

		mcu_ringacc: ringacc@2b800000 {
			compatible = "ti,am654-navss-ringacc";
			reg =	<0x0 0x2b800000 0x0 0x400000>,
				<0x0 0x2b000000 0x0 0x400000>,
				<0x0 0x28590000 0x0 0x100>,
				<0x0 0x2a500000 0x0 0x40000>;
			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
			ti,num-rings = <286>;
			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <235>;
			msi-parent = <&main_udmass_inta>;
		};

		mcu_udmap: dma-controller@285c0000 {
			compatible = "ti,j721e-navss-mcu-udmap";
			reg =	<0x0 0x285c0000 0x0 0x100>,
				<0x0 0x2a800000 0x0 0x40000>,
				<0x0 0x2aa00000 0x0 0x40000>;
			reg-names = "gcfg", "rchanrt", "tchanrt";
			msi-parent = <&main_udmass_inta>;
			#dma-cells = <1>;

			ti,sci = <&dmsc>;
			ti,sci-dev-id = <236>;
			ti,ringacc = <&mcu_ringacc>;

			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
						<0x0f>; /* TX_HCHAN */
			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
						<0x0b>; /* RX_HCHAN */
			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
		};
	};

	mcu_cpsw: ethernet@46000000 {
		compatible = "ti,j721e-cpsw-nuss";
		#address-cells = <2>;
		#size-cells = <2>;
		reg = <0x0 0x46000000 0x0 0x200000>;
		reg-names = "cpsw_nuss";
		ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
		dma-coherent;
		clocks = <&k3_clks 18 22>;
		clock-names = "fck";
		power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;

		dmas = <&mcu_udmap 0xf000>,
		       <&mcu_udmap 0xf001>,
		       <&mcu_udmap 0xf002>,
		       <&mcu_udmap 0xf003>,
		       <&mcu_udmap 0xf004>,
		       <&mcu_udmap 0xf005>,
		       <&mcu_udmap 0xf006>,
		       <&mcu_udmap 0xf007>,
		       <&mcu_udmap 0x7000>;
		dma-names = "tx0", "tx1", "tx2", "tx3",
			    "tx4", "tx5", "tx6", "tx7",
			    "rx";

		ethernet-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			cpsw_port1: port@1 {
				reg = <1>;
				ti,mac-only;
				label = "port1";
				ti,syscon-efuse = <&mcu_conf 0x200>;
				phys = <&phy_gmii_sel 1>;
			};
		};

		davinci_mdio: mdio@f00 {
			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
			reg = <0x0 0xf00 0x0 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&k3_clks 18 22>;
			clock-names = "fck";
			bus_freq = <1000000>;
		};

		cpts@3d000 {
			compatible = "ti,am65-cpts";
			reg = <0x0 0x3d000 0x0 0x400>;
			clocks = <&k3_clks 18 2>;
			clock-names = "cpts";
			interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "cpts";
			ti,cpts-ext-ts-inputs = <4>;
			ti,cpts-periodic-outputs = <2>;
		};
	};

	mcu_r5fss0: r5fss@41000000 {
		compatible = "ti,j721e-r5fss";
		ti,cluster-mode = <1>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x41000000 0x00 0x41000000 0x20000>,
			 <0x41400000 0x00 0x41400000 0x20000>;
		power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;

		mcu_r5fss0_core0: r5f@41000000 {
			compatible = "ti,j721e-r5f";
			reg = <0x41000000 0x00008000>,
			      <0x41010000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <250>;
			ti,sci-proc-ids = <0x01 0xff>;
			resets = <&k3_reset 250 1>;
			firmware-name = "j7-mcu-r5f0_0-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};

		mcu_r5fss0_core1: r5f@41400000 {
			compatible = "ti,j721e-r5f";
			reg = <0x41400000 0x00008000>,
			      <0x41410000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <251>;
			ti,sci-proc-ids = <0x02 0xff>;
			resets = <&k3_reset 251 1>;
			firmware-name = "j7-mcu-r5f0_1-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};
	};

	mcu_mcan0: can@40528000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x40528000 0x00 0x200>,
		      <0x00 0x40500000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 172 0>, <&k3_clks 172 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	mcu_mcan1: can@40568000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x40568000 0x00 0x200>,
		      <0x00 0x40540000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 173 0>, <&k3_clks 173 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	mcu_spi0: spi@40300000 {
		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
		reg = <0x00 0x040300000 0x00 0x400>;
		interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 274 0>;
		status = "disabled";
	};

	mcu_spi1: spi@40310000 {
		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
		reg = <0x00 0x040310000 0x00 0x400>;
		interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 275 0>;
		status = "disabled";
	};

	mcu_spi2: spi@40320000 {
		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
		reg = <0x00 0x040320000 0x00 0x400>;
		interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 276 0>;
		status = "disabled";
	};

	wkup_vtm0: temperature-sensor@42040000 {
		compatible = "ti,j721e-vtm";
		reg = <0x00 0x42040000 0x00 0x350>,
		      <0x00 0x42050000 0x00 0x350>,
		      <0x00 0x43000300 0x00 0x10>;
		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
		#thermal-sensor-cells = <1>;
	};
};
Commit	Line	Data
2d87061e NM	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
	4	*
dd74c945	5	* Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
2d87061e NM	6	*/
	7
	8	&cbass_mcu_wakeup {
9d3c9378	9	dmsc: system-controller@44083000 {
2d87061e NM	10	compatible = "ti,k2g-sci";
	11	ti,host-id = <12>;
	12
	13	mbox-names = "rx", "tx";
	14
5888f1ed KK	15	mboxes = <&secure_proxy_main 11>,
5888f1ed KK	16	<&secure_proxy_main 13>;
2d87061e NM	17
	18	reg-names = "debug_messages";
	19	reg = <0x00 0x44083000 0x0 0x1000>;
	20
	21	k3_pds: power-controller {
	22	compatible = "ti,sci-pm-domain";
bf146a1a	23	#power-domain-cells = <2>;
2d87061e NM	24	};
2d87061e NM	25
a0812885	26	k3_clks: clock-controller {
2d87061e NM	27	compatible = "ti,k2g-sci-clk";
	28	#clock-cells = <2>;
	29	};
	30
	31	k3_reset: reset-controller {
	32	compatible = "ti,sci-reset";
	33	#reset-cells = <2>;
	34	};
	35	};
	36
ad3bcb0f GS	37	mcu_conf: syscon@40f00000 {
	38	compatible = "syscon", "simple-mfd";
	39	reg = <0x0 0x40f00000 0x0 0x20000>;
	40	#address-cells = <1>;
	41	#size-cells = <1>;
	42	ranges = <0x0 0x0 0x40f00000 0x20000>;
	43
	44	phy_gmii_sel: phy@4040 {
	45	compatible = "ti,am654-phy-gmii-sel";
	46	reg = <0x4040 0x4>;
	47	#phy-cells = <1>;
	48	};
	49	};
	50
23d160ef GS	51	chipid@43000014 {
	52	compatible = "ti,am654-chipid";
	53	reg = <0x0 0x43000014 0x0 0x4>;
	54	};
	55
dcccf770	56	wkup_pmx0: pinctrl@4301c000 {
2d87061e NM	57	compatible = "pinctrl-single";
	58	/* Proxy 0 addressing */
	59	reg = <0x00 0x4301c000 0x00 0x178>;
	60	#pinctrl-cells = <1>;
	61	pinctrl-single,register-width = <32>;
	62	pinctrl-single,function-mask = <0xffffffff>;
	63	};
	64
78eccc2a SA	65	mcu_ram: sram@41c00000 {
	66	compatible = "mmio-sram";
	67	reg = <0x00 0x41c00000 0x00 0x100000>;
	68	ranges = <0x0 0x00 0x41c00000 0x100000>;
	69	#address-cells = <1>;
	70	#size-cells = <1>;
	71	};
	72
2d87061e NM	73	wkup_uart0: serial@42300000 {
	74	compatible = "ti,j721e-uart", "ti,am654-uart";
	75	reg = <0x00 0x42300000 0x00 0x100>;
2d87061e NM	76	interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
	77	clock-frequency = <48000000>;
	78	current-speed = <115200>;
bf146a1a	79	power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
2d87061e NM	80	clocks = <&k3_clks 287 0>;
2d87061e NM	81	clock-names = "fclk";
fe17e20f	82	status = "disabled";
2d87061e NM	83	};
	84
	85	mcu_uart0: serial@40a00000 {
	86	compatible = "ti,j721e-uart", "ti,am654-uart";
	87	reg = <0x00 0x40a00000 0x00 0x100>;
2d87061e NM	88	interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
	89	clock-frequency = <96000000>;
	90	current-speed = <115200>;
bf146a1a	91	power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
2d87061e NM	92	clocks = <&k3_clks 149 0>;
2d87061e NM	93	clock-names = "fclk";
fe17e20f	94	status = "disabled";
2d87061e	95	};
ae7d8505	96
cab12bad	97	wkup_gpio_intr: interrupt-controller@42200000 {
ae7d8505	98	compatible = "ti,sci-intr";
cab12bad	99	reg = <0x00 0x42200000 0x00 0x400>;
ae7d8505 LV	100	ti,intr-trigger-type = <1>;
	101	interrupt-controller;
	102	interrupt-parent = <&gic500>;
8d523f09	103	#interrupt-cells = <1>;
ae7d8505	104	ti,sci = <&dmsc>;
8d523f09 LV	105	ti,sci-dev-id = <137>;
8d523f09 LV	106	ti,interrupt-ranges = <16 960 16>;
ae7d8505	107	};
caaaa1f8 LV	108
	109	wkup_gpio0: gpio@42110000 {
	110	compatible = "ti,j721e-gpio", "ti,keystone-gpio";
	111	reg = <0x0 0x42110000 0x0 0x100>;
	112	gpio-controller;
	113	#gpio-cells = <2>;
	114	interrupt-parent = <&wkup_gpio_intr>;
8d523f09	115	interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
caaaa1f8 LV	116	interrupt-controller;
	117	#interrupt-cells = <2>;
	118	ti,ngpio = <84>;
	119	ti,davinci-gpio-unbanked = <0>;
	120	power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
	121	clocks = <&k3_clks 113 0>;
	122	clock-names = "gpio";
	123	};
	124
	125	wkup_gpio1: gpio@42100000 {
	126	compatible = "ti,j721e-gpio", "ti,keystone-gpio";
	127	reg = <0x0 0x42100000 0x0 0x100>;
	128	gpio-controller;
	129	#gpio-cells = <2>;
	130	interrupt-parent = <&wkup_gpio_intr>;
8d523f09	131	interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
caaaa1f8 LV	132	interrupt-controller;
	133	#interrupt-cells = <2>;
	134	ti,ngpio = <84>;
	135	ti,davinci-gpio-unbanked = <0>;
	136	power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
	137	clocks = <&k3_clks 114 0>;
	138	clock-names = "gpio";
	139	};
cb27354b VR	140
	141	mcu_i2c0: i2c@40b00000 {
	142	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
	143	reg = <0x0 0x40b00000 0x0 0x100>;
	144	interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
	145	#address-cells = <1>;
	146	#size-cells = <0>;
	147	clock-names = "fck";
	148	clocks = <&k3_clks 194 0>;
	149	power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
282c4ad3	150	status = "disabled";
cb27354b VR	151	};
	152
	153	mcu_i2c1: i2c@40b10000 {
	154	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
	155	reg = <0x0 0x40b10000 0x0 0x100>;
	156	interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
	157	#address-cells = <1>;
	158	#size-cells = <0>;
	159	clock-names = "fck";
	160	clocks = <&k3_clks 195 0>;
	161	power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
282c4ad3	162	status = "disabled";
cb27354b VR	163	};
	164
	165	wkup_i2c0: i2c@42120000 {
	166	compatible = "ti,j721e-i2c", "ti,omap4-i2c";
	167	reg = <0x0 0x42120000 0x0 0x100>;
	168	interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
	169	#address-cells = <1>;
	170	#size-cells = <0>;
	171	clock-names = "fck";
	172	clocks = <&k3_clks 197 0>;
	173	power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
282c4ad3	174	status = "disabled";
cb27354b VR	175	};
	176
	177	fss: fss@47000000 {
	178	compatible = "simple-bus";
	179	reg = <0x0 0x47000000 0x0 0x100>;
	180	#address-cells = <2>;
	181	#size-cells = <2>;
	182	ranges;
	183
	184	ospi0: spi@47040000 {
f1b6f6e7	185	compatible = "ti,am654-ospi", "cdns,qspi-nor";
cb27354b VR	186	reg = <0x0 0x47040000 0x0 0x100>,
	187	<0x5 0x00000000 0x1 0x0000000>;
	188	interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
	189	cdns,fifo-depth = <256>;
	190	cdns,fifo-width = <4>;
	191	cdns,trigger-address = <0x0>;
	192	clocks = <&k3_clks 103 0>;
	193	assigned-clocks = <&k3_clks 103 0>;
	194	assigned-clock-parents = <&k3_clks 103 2>;
	195	assigned-clock-rates = <166666666>;
	196	power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
	197	#address-cells = <1>;
	198	#size-cells = <0>;
	199	};
	200
	201	ospi1: spi@47050000 {
f1b6f6e7	202	compatible = "ti,am654-ospi", "cdns,qspi-nor";
cb27354b VR	203	reg = <0x0 0x47050000 0x0 0x100>,
	204	<0x7 0x00000000 0x1 0x00000000>;
	205	interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
	206	cdns,fifo-depth = <256>;
	207	cdns,fifo-width = <4>;
	208	cdns,trigger-address = <0x0>;
	209	clocks = <&k3_clks 104 0>;
	210	power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
	211	#address-cells = <1>;
	212	#size-cells = <0>;
	213	};
	214	};
	215
	216	tscadc0: tscadc@40200000 {
	217	compatible = "ti,am3359-tscadc";
	218	reg = <0x0 0x40200000 0x0 0x1000>;
	219	interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
	220	power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
	221	clocks = <&k3_clks 0 1>;
	222	assigned-clocks = <&k3_clks 0 3>;
	223	assigned-clock-rates = <60000000>;
e5bad300	224	clock-names = "fck";
5ccd8dfe VR	225	dmas = <&main_udmap 0x7400>,
	226	<&main_udmap 0x7401>;
	227	dma-names = "fifo0", "fifo1";
cb27354b VR	228
	229	adc {
	230	#io-channel-cells = <1>;
	231	compatible = "ti,am3359-adc";
	232	};
	233	};
	234
	235	tscadc1: tscadc@40210000 {
	236	compatible = "ti,am3359-tscadc";
	237	reg = <0x0 0x40210000 0x0 0x1000>;
	238	interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
	239	power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
	240	clocks = <&k3_clks 1 1>;
	241	assigned-clocks = <&k3_clks 1 3>;
	242	assigned-clock-rates = <60000000>;
e5bad300	243	clock-names = "fck";
5ccd8dfe VR	244	dmas = <&main_udmap 0x7402>,
	245	<&main_udmap 0x7403>;
	246	dma-names = "fifo0", "fifo1";
cb27354b VR	247
	248	adc {
	249	#io-channel-cells = <1>;
	250	compatible = "ti,am3359-adc";
	251	};
	252	};
6f73c1e5	253
9ecdb6d6	254	mcu_navss: bus@28380000 {
6f73c1e5 PU	255	compatible = "simple-mfd";
	256	#address-cells = <2>;
	257	#size-cells = <2>;
9ecdb6d6	258	ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
6f73c1e5 PU	259	dma-coherent;
	260	dma-ranges;
	261
	262	ti,sci-dev-id = <232>;
	263
	264	mcu_ringacc: ringacc@2b800000 {
	265	compatible = "ti,am654-navss-ringacc";
	266	reg = <0x0 0x2b800000 0x0 0x400000>,
	267	<0x0 0x2b000000 0x0 0x400000>,
	268	<0x0 0x28590000 0x0 0x100>,
	269	<0x0 0x2a500000 0x0 0x40000>;
	270	reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
	271	ti,num-rings = <286>;
	272	ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
	273	ti,sci = <&dmsc>;
	274	ti,sci-dev-id = <235>;
	275	msi-parent = <&main_udmass_inta>;
	276	};
	277
	278	mcu_udmap: dma-controller@285c0000 {
	279	compatible = "ti,j721e-navss-mcu-udmap";
	280	reg = <0x0 0x285c0000 0x0 0x100>,
	281	<0x0 0x2a800000 0x0 0x40000>,
	282	<0x0 0x2aa00000 0x0 0x40000>;
	283	reg-names = "gcfg", "rchanrt", "tchanrt";
	284	msi-parent = <&main_udmass_inta>;
	285	#dma-cells = <1>;
	286
	287	ti,sci = <&dmsc>;
	288	ti,sci-dev-id = <236>;
	289	ti,ringacc = <&mcu_ringacc>;
	290
	291	ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
	292	<0x0f>; /* TX_HCHAN */
	293	ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
	294	<0x0b>; /* RX_HCHAN */
	295	ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
	296	};
	297	};
ae7fdac8 GS	298
	299	mcu_cpsw: ethernet@46000000 {
	300	compatible = "ti,j721e-cpsw-nuss";
	301	#address-cells = <2>;
	302	#size-cells = <2>;
	303	reg = <0x0 0x46000000 0x0 0x200000>;
	304	reg-names = "cpsw_nuss";
	305	ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
	306	dma-coherent;
	307	clocks = <&k3_clks 18 22>;
	308	clock-names = "fck";
	309	power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
	310
	311	dmas = <&mcu_udmap 0xf000>,
	312	<&mcu_udmap 0xf001>,
	313	<&mcu_udmap 0xf002>,
	314	<&mcu_udmap 0xf003>,
	315	<&mcu_udmap 0xf004>,
	316	<&mcu_udmap 0xf005>,
	317	<&mcu_udmap 0xf006>,
	318	<&mcu_udmap 0xf007>,
	319	<&mcu_udmap 0x7000>;
	320	dma-names = "tx0", "tx1", "tx2", "tx3",
	321	"tx4", "tx5", "tx6", "tx7",
	322	"rx";
	323
	324	ethernet-ports {
	325	#address-cells = <1>;
	326	#size-cells = <0>;
	327
	328	cpsw_port1: port@1 {
	329	reg = <1>;
	330	ti,mac-only;
	331	label = "port1";
	332	ti,syscon-efuse = <&mcu_conf 0x200>;
	333	phys = <&phy_gmii_sel 1>;
	334	};
	335	};
	336
	337	davinci_mdio: mdio@f00 {
	338	compatible = "ti,cpsw-mdio","ti,davinci_mdio";
	339	reg = <0x0 0xf00 0x0 0x100>;
	340	#address-cells = <1>;
	341	#size-cells = <0>;
	342	clocks = <&k3_clks 18 22>;
	343	clock-names = "fck";
	344	bus_freq = <1000000>;
	345	};
29390928	346
ef2d1363 GS	347	cpts@3d000 {
	348	compatible = "ti,am65-cpts";
	349	reg = <0x0 0x3d000 0x0 0x400>;
29390928 GS	350	clocks = <&k3_clks 18 2>;
	351	clock-names = "cpts";
	352	interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
	353	interrupt-names = "cpts";
	354	ti,cpts-ext-ts-inputs = <4>;
	355	ti,cpts-periodic-outputs = <2>;
	356	};
ae7fdac8	357	};
dd74c945 SA	358
	359	mcu_r5fss0: r5fss@41000000 {
	360	compatible = "ti,j721e-r5fss";
	361	ti,cluster-mode = <1>;
	362	#address-cells = <1>;
	363	#size-cells = <1>;
	364	ranges = <0x41000000 0x00 0x41000000 0x20000>,
	365	<0x41400000 0x00 0x41400000 0x20000>;
	366	power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
	367
	368	mcu_r5fss0_core0: r5f@41000000 {
	369	compatible = "ti,j721e-r5f";
	370	reg = <0x41000000 0x00008000>,
	371	<0x41010000 0x00008000>;
	372	reg-names = "atcm", "btcm";
	373	ti,sci = <&dmsc>;
	374	ti,sci-dev-id = <250>;
	375	ti,sci-proc-ids = <0x01 0xff>;
	376	resets = <&k3_reset 250 1>;
	377	firmware-name = "j7-mcu-r5f0_0-fw";
	378	ti,atcm-enable = <1>;
	379	ti,btcm-enable = <1>;
	380	ti,loczrama = <1>;
	381	};
	382
	383	mcu_r5fss0_core1: r5f@41400000 {
	384	compatible = "ti,j721e-r5f";
	385	reg = <0x41400000 0x00008000>,
	386	<0x41410000 0x00008000>;
	387	reg-names = "atcm", "btcm";
	388	ti,sci = <&dmsc>;
	389	ti,sci-dev-id = <251>;
	390	ti,sci-proc-ids = <0x02 0xff>;
	391	resets = <&k3_reset 251 1>;
	392	firmware-name = "j7-mcu-r5f0_1-fw";
	393	ti,atcm-enable = <1>;
	394	ti,btcm-enable = <1>;
	395	ti,loczrama = <1>;
	396	};
	397	};
4688a4fc FA	398
	399	mcu_mcan0: can@40528000 {
	400	compatible = "bosch,m_can";
	401	reg = <0x00 0x40528000 0x00 0x200>,
	402	<0x00 0x40500000 0x00 0x8000>;
	403	reg-names = "m_can", "message_ram";
	404	power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>;
	405	clocks = <&k3_clks 172 0>, <&k3_clks 172 1>;
	406	clock-names = "hclk", "cclk";
	407	interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
	408	<GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
	409	interrupt-names = "int0", "int1";
	410	bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
39e7758b	411	status = "disabled";
4688a4fc FA	412	};
	413
	414	mcu_mcan1: can@40568000 {
	415	compatible = "bosch,m_can";
	416	reg = <0x00 0x40568000 0x00 0x200>,
	417	<0x00 0x40540000 0x00 0x8000>;
	418	reg-names = "m_can", "message_ram";
	419	power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>;
	420	clocks = <&k3_clks 173 0>, <&k3_clks 173 1>;
	421	clock-names = "hclk", "cclk";
	422	interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
	423	<GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
	424	interrupt-names = "int0", "int1";
	425	bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
39e7758b	426	status = "disabled";
4688a4fc	427	};
76aa309f VA	428
	429	mcu_spi0: spi@40300000 {
	430	compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
	431	reg = <0x00 0x040300000 0x00 0x400>;
	432	interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
	433	#address-cells = <1>;
	434	#size-cells = <0>;
	435	power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
	436	clocks = <&k3_clks 274 0>;
	437	status = "disabled";
	438	};
	439
	440	mcu_spi1: spi@40310000 {
	441	compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
	442	reg = <0x00 0x040310000 0x00 0x400>;
	443	interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
	444	#address-cells = <1>;
	445	#size-cells = <0>;
	446	power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
	447	clocks = <&k3_clks 275 0>;
	448	status = "disabled";
	449	};
	450
	451	mcu_spi2: spi@40320000 {
	452	compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
	453	reg = <0x00 0x040320000 0x00 0x400>;
	454	interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
	455	#address-cells = <1>;
	456	#size-cells = <0>;
	457	power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
	458	clocks = <&k3_clks 276 0>;
	459	status = "disabled";
	460	};
8fb4e87c K	461
	462	wkup_vtm0: temperature-sensor@42040000 {
	463	compatible = "ti,j721e-vtm";
	464	reg = <0x00 0x42040000 0x00 0x350>,
	465	<0x00 0x42050000 0x00 0x350>,
	466	<0x00 0x43000300 0x00 0x10>;
	467	power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
	468	#thermal-sensor-cells = <1>;
	469	};
2d87061e	470	};