projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 2d87061e NM |
1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* | |
| 3 | * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals | |
| 4 | * | |
| 5 | * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ | |
| 6 | */ | |
| 7 | ||
| 8 | &cbass_mcu_wakeup { | |
| 9 | dmsc: dmsc@44083000 { | |
| 10 | compatible = "ti,k2g-sci"; | |
| 11 | ti,host-id = <12>; | |
| 12 | ||
| 13 | mbox-names = "rx", "tx"; | |
| 14 | ||
| 15 | mboxes= <&secure_proxy_main 11>, | |
| 16 | <&secure_proxy_main 13>; | |
| 17 | ||
| 18 | reg-names = "debug_messages"; | |
| 19 | reg = <0x00 0x44083000 0x0 0x1000>; | |
| 20 | ||
| 21 | k3_pds: power-controller { | |
| 22 | compatible = "ti,sci-pm-domain"; | |
| 23 | #power-domain-cells = <1>; | |
| 24 | }; | |
| 25 | ||
| 26 | k3_clks: clocks { | |
| 27 | compatible = "ti,k2g-sci-clk"; | |
| 28 | #clock-cells = <2>; | |
| 29 | }; | |
| 30 | ||
| 31 | k3_reset: reset-controller { | |
| 32 | compatible = "ti,sci-reset"; | |
| 33 | #reset-cells = <2>; | |
| 34 | }; | |
| 35 | }; | |
| 36 | ||
| 37 | wkup_pmx0: pinmux@4301c000 { | |
| 38 | compatible = "pinctrl-single"; | |
| 39 | /* Proxy 0 addressing */ | |
| 40 | reg = <0x00 0x4301c000 0x00 0x178>; | |
| 41 | #pinctrl-cells = <1>; | |
| 42 | pinctrl-single,register-width = <32>; | |
| 43 | pinctrl-single,function-mask = <0xffffffff>; | |
| 44 | }; | |
| 45 | ||
| 46 | wkup_uart0: serial@42300000 { | |
| 47 | compatible = "ti,j721e-uart", "ti,am654-uart"; | |
| 48 | reg = <0x00 0x42300000 0x00 0x100>; | |
| 49 | reg-shift = <2>; | |
| 50 | reg-io-width = <4>; | |
| 51 | interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; | |
| 52 | clock-frequency = <48000000>; | |
| 53 | current-speed = <115200>; | |
| 54 | power-domains = <&k3_pds 287>; | |
| 55 | clocks = <&k3_clks 287 0>; | |
| 56 | clock-names = "fclk"; | |
| 57 | }; | |
| 58 | ||
| 59 | mcu_uart0: serial@40a00000 { | |
| 60 | compatible = "ti,j721e-uart", "ti,am654-uart"; | |
| 61 | reg = <0x00 0x40a00000 0x00 0x100>; | |
| 62 | reg-shift = <2>; | |
| 63 | reg-io-width = <4>; | |
| 64 | interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; | |
| 65 | clock-frequency = <96000000>; | |
| 66 | current-speed = <115200>; | |
| 67 | power-domains = <&k3_pds 149>; | |
| 68 | clocks = <&k3_clks 149 0>; | |
| 69 | clock-names = "fclk"; | |
| 70 | }; | |
| ae7d8505 LV |
71 | |
| 72 | wkup_gpio_intr: interrupt-controller2 { | |
| 73 | compatible = "ti,sci-intr"; | |
| 74 | ti,intr-trigger-type = <1>; | |
| 75 | interrupt-controller; | |
| 76 | interrupt-parent = <&gic500>; | |
| 77 | #interrupt-cells = <2>; | |
| 78 | ti,sci = <&dmsc>; | |
| 79 | ti,sci-dst-id = <14>; | |
| 80 | ti,sci-rm-range-girq = <0x5>; | |
| 81 | }; | |
| 2d87061e | 82 | }; |