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Merge tag 'soc-drivers-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[linux-block.git] / arch / arm64 / boot / dts / ti / k3-j721e-mcu-wakeup.dtsi
CommitLineData
111f6dac 1// SPDX-License-Identifier: GPL-2.0-only OR MIT
2d87061e
NM		 2/*
3 * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
4 *
111f6dac 5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
2d87061e
NM		 6 */
7
8&cbass_mcu_wakeup {
9d3c9378 9 dmsc: system-controller@44083000 {
2d87061e
NM		 10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
12
13 mbox-names = "rx", "tx";
14
5888f1ed
KK		 15 mboxes = <&secure_proxy_main 11>,
16 <&secure_proxy_main 13>;
2d87061e
NM		 17
18 reg-names = "debug_messages";
19 reg = <0x00 0x44083000 0x0 0x1000>;
20
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
bf146a1a 23 #power-domain-cells = <2>;
2d87061e
NM		 24 };
25
a0812885 26 k3_clks: clock-controller {
2d87061e
NM		 27 compatible = "ti,k2g-sci-clk";
28 #clock-cells = <2>;
29 };
30
31 k3_reset: reset-controller {
32 compatible = "ti,sci-reset";
33 #reset-cells = <2>;
34 };
35 };
36
ad3bcb0f
GS		 37 mcu_conf: syscon@40f00000 {
38 compatible = "syscon", "simple-mfd";
39 reg = <0x0 0x40f00000 0x0 0x20000>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42 ranges = <0x0 0x0 0x40f00000 0x20000>;
43
44 phy_gmii_sel: phy@4040 {
45 compatible = "ti,am654-phy-gmii-sel";
46 reg = <0x4040 0x4>;
47 #phy-cells = <1>;
48 };
49 };
50
27e5b733
AD		 51 wkup_conf: bus@43000000 {
52 compatible = "simple-bus";
53 #address-cells = <1>;
54 #size-cells = <1>;
55 ranges = <0x0 0x00 0x43000000 0x20000>;
56
57 chipid: chipid@14 {
58 compatible = "ti,am654-chipid";
59 reg = <0x14 0x4>;
60 };
23d160ef
GS		 61 };
62
dcccf770 63 wkup_pmx0: pinctrl@4301c000 {
2d87061e
NM		 64 compatible = "pinctrl-single";
65 /* Proxy 0 addressing */
66 reg = <0x00 0x4301c000 0x00 0x178>;
67 #pinctrl-cells = <1>;
68 pinctrl-single,register-width = <32>;
69 pinctrl-single,function-mask = <0xffffffff>;
70 };
71
72a44d1c
NM		 72 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
73 mcu_timerio_input: pinctrl@40f04200 {
74 compatible = "pinctrl-single";
75 reg = <0x00 0x40f04200 0x00 0x28>;
76 #pinctrl-cells = <1>;
77 pinctrl-single,register-width = <32>;
78 pinctrl-single,function-mask = <0x0000000f>;
79 /* Non-MPU Firmware usage */
80 status = "reserved";
81 };
82
83 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
84 mcu_timerio_output: pinctrl@40f04280 {
85 compatible = "pinctrl-single";
86 reg = <0x00 0x40f04280 0x00 0x28>;
87 #pinctrl-cells = <1>;
88 pinctrl-single,register-width = <32>;
89 pinctrl-single,function-mask = <0x0000000f>;
90 /* Non-MPU Firmware usage */
91 status = "reserved";
92 };
93
78eccc2a
SA		 94 mcu_ram: sram@41c00000 {
95 compatible = "mmio-sram";
96 reg = <0x00 0x41c00000 0x00 0x100000>;
97 ranges = <0x0 0x00 0x41c00000 0x100000>;
98 #address-cells = <1>;
99 #size-cells = <1>;
100 };
101
7f209dd1
NM		 102 mcu_timer0: timer@40400000 {
103 compatible = "ti,am654-timer";
104 reg = <0x00 0x40400000 0x00 0x400>;
105 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
106 clocks = <&k3_clks 35 1>;
107 clock-names = "fck";
108 assigned-clocks = <&k3_clks 35 1>;
109 assigned-clock-parents = <&k3_clks 35 2>;
110 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
111 ti,timer-pwm;
112 /* Non-MPU Firmware usage */
113 status = "reserved";
114 };
115
116 mcu_timer1: timer@40410000 {
117 compatible = "ti,am654-timer";
118 reg = <0x00 0x40410000 0x00 0x400>;
119 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
120 clocks = <&k3_clks 71 1>;
121 clock-names = "fck";
122 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>;
123 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>;
124 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
125 ti,timer-pwm;
126 /* Non-MPU Firmware usage */
127 status = "reserved";
128 };
129
130 mcu_timer2: timer@40420000 {
131 compatible = "ti,am654-timer";
132 reg = <0x00 0x40420000 0x00 0x400>;
133 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&k3_clks 72 1>;
135 clock-names = "fck";
136 assigned-clocks = <&k3_clks 72 1>;
137 assigned-clock-parents = <&k3_clks 72 2>;
138 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
139 ti,timer-pwm;
140 /* Non-MPU Firmware usage */
141 status = "reserved";
142 };
143
144 mcu_timer3: timer@40430000 {
145 compatible = "ti,am654-timer";
146 reg = <0x00 0x40430000 0x00 0x400>;
147 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&k3_clks 73 1>;
149 clock-names = "fck";
150 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>;
151 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>;
152 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
153 ti,timer-pwm;
154 /* Non-MPU Firmware usage */
155 status = "reserved";
156 };
157
158 mcu_timer4: timer@40440000 {
159 compatible = "ti,am654-timer";
160 reg = <0x00 0x40440000 0x00 0x400>;
161 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
162 clocks = <&k3_clks 74 1>;
163 clock-names = "fck";
164 assigned-clocks = <&k3_clks 74 1>;
165 assigned-clock-parents = <&k3_clks 74 2>;
166 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
167 ti,timer-pwm;
168 /* Non-MPU Firmware usage */
169 status = "reserved";
170 };
171
172 mcu_timer5: timer@40450000 {
173 compatible = "ti,am654-timer";
174 reg = <0x00 0x40450000 0x00 0x400>;
175 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&k3_clks 75 1>;
177 clock-names = "fck";
178 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>;
179 assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 324 1>;
180 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
181 ti,timer-pwm;
182 /* Non-MPU Firmware usage */
183 status = "reserved";
184 };
185
186 mcu_timer6: timer@40460000 {
187 compatible = "ti,am654-timer";
188 reg = <0x00 0x40460000 0x00 0x400>;
189 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&k3_clks 76 1>;
191 clock-names = "fck";
192 assigned-clocks = <&k3_clks 76 1>;
193 assigned-clock-parents = <&k3_clks 76 2>;
194 power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
195 ti,timer-pwm;
196 /* Non-MPU Firmware usage */
197 status = "reserved";
198 };
199
200 mcu_timer7: timer@40470000 {
201 compatible = "ti,am654-timer";
202 reg = <0x00 0x40470000 0x00 0x400>;
203 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&k3_clks 77 1>;
205 clock-names = "fck";
206 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>;
207 assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 325 1>;
208 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
209 ti,timer-pwm;
210 /* Non-MPU Firmware usage */
211 status = "reserved";
212 };
213
214 mcu_timer8: timer@40480000 {
215 compatible = "ti,am654-timer";
216 reg = <0x00 0x40480000 0x00 0x400>;
217 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&k3_clks 78 1>;
219 clock-names = "fck";
220 assigned-clocks = <&k3_clks 78 1>;
221 assigned-clock-parents = <&k3_clks 78 2>;
222 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
223 ti,timer-pwm;
224 /* Non-MPU Firmware usage */
225 status = "reserved";
226 };
227
228 mcu_timer9: timer@40490000 {
229 compatible = "ti,am654-timer";
230 reg = <0x00 0x40490000 0x00 0x400>;
231 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&k3_clks 79 1>;
233 clock-names = "fck";
234 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>;
235 assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 326 1>;
236 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
237 ti,timer-pwm;
238 /* Non-MPU Firmware usage */
239 status = "reserved";
240 };
2d87061e
NM		 241 wkup_uart0: serial@42300000 {
242 compatible = "ti,j721e-uart", "ti,am654-uart";
243 reg = <0x00 0x42300000 0x00 0x100>;
2d87061e
NM		 244 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
245 clock-frequency = <48000000>;
246 current-speed = <115200>;
bf146a1a 247 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
2d87061e
NM		 248 clocks = <&k3_clks 287 0>;
249 clock-names = "fclk";
fe17e20f 250 status = "disabled";
2d87061e
NM		 251 };
252
253 mcu_uart0: serial@40a00000 {
254 compatible = "ti,j721e-uart", "ti,am654-uart";
255 reg = <0x00 0x40a00000 0x00 0x100>;
2d87061e
NM		 256 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
257 clock-frequency = <96000000>;
258 current-speed = <115200>;
bf146a1a 259 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
2d87061e
NM		 260 clocks = <&k3_clks 149 0>;
261 clock-names = "fclk";
fe17e20f 262 status = "disabled";
2d87061e 263 };
ae7d8505 264
cab12bad 265 wkup_gpio_intr: interrupt-controller@42200000 {
ae7d8505 266 compatible = "ti,sci-intr";
cab12bad 267 reg = <0x00 0x42200000 0x00 0x400>;
ae7d8505
LV		 268 ti,intr-trigger-type = <1>;
269 interrupt-controller;
270 interrupt-parent = <&gic500>;
8d523f09 271 #interrupt-cells = <1>;
ae7d8505 272 ti,sci = <&dmsc>;
8d523f09
LV		 273 ti,sci-dev-id = <137>;
274 ti,interrupt-ranges = <16 960 16>;
ae7d8505 275 };
caaaa1f8
LV		 276
277 wkup_gpio0: gpio@42110000 {
278 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
279 reg = <0x0 0x42110000 0x0 0x100>;
280 gpio-controller;
281 #gpio-cells = <2>;
282 interrupt-parent = <&wkup_gpio_intr>;
8d523f09 283 interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
caaaa1f8
LV		 284 interrupt-controller;
285 #interrupt-cells = <2>;
286 ti,ngpio = <84>;
287 ti,davinci-gpio-unbanked = <0>;
288 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
289 clocks = <&k3_clks 113 0>;
290 clock-names = "gpio";
8757108b 291 status = "disabled";
caaaa1f8
LV		 292 };
293
294 wkup_gpio1: gpio@42100000 {
295 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
296 reg = <0x0 0x42100000 0x0 0x100>;
297 gpio-controller;
298 #gpio-cells = <2>;
299 interrupt-parent = <&wkup_gpio_intr>;
8d523f09 300 interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
caaaa1f8
LV		 301 interrupt-controller;
302 #interrupt-cells = <2>;
303 ti,ngpio = <84>;
304 ti,davinci-gpio-unbanked = <0>;
305 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
306 clocks = <&k3_clks 114 0>;
307 clock-names = "gpio";
8757108b 308 status = "disabled";
caaaa1f8 309 };
cb27354b
VR		 310
311 mcu_i2c0: i2c@40b00000 {
312 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
313 reg = <0x0 0x40b00000 0x0 0x100>;
314 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
315 #address-cells = <1>;
316 #size-cells = <0>;
317 clock-names = "fck";
318 clocks = <&k3_clks 194 0>;
319 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
282c4ad3 320 status = "disabled";
cb27354b
VR		 321 };
322
323 mcu_i2c1: i2c@40b10000 {
324 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
325 reg = <0x0 0x40b10000 0x0 0x100>;
326 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
327 #address-cells = <1>;
328 #size-cells = <0>;
329 clock-names = "fck";
330 clocks = <&k3_clks 195 0>;
331 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
282c4ad3 332 status = "disabled";
cb27354b
VR		 333 };
334
335 wkup_i2c0: i2c@42120000 {
336 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
337 reg = <0x0 0x42120000 0x0 0x100>;
338 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
339 #address-cells = <1>;
340 #size-cells = <0>;
341 clock-names = "fck";
342 clocks = <&k3_clks 197 0>;
343 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
282c4ad3 344 status = "disabled";
cb27354b
VR		 345 };
346
8ea3fc2b 347 fss: bus@47000000 {
cb27354b
VR		 348 compatible = "simple-bus";
349 reg = <0x0 0x47000000 0x0 0x100>;
350 #address-cells = <2>;
351 #size-cells = <2>;
352 ranges;
353
d93036b4
VA		 354 hbmc_mux: mux-controller@47000004 {
355 compatible = "reg-mux";
3d585389 356 reg = <0x00 0x47000004 0x00 0x4>;
d93036b4 357 #mux-control-cells = <1>;
3d585389 358 mux-reg-masks = <0x0 0x2>; /* HBMC select */
d93036b4
VA		 359 };
360
361 hbmc: hyperbus@47034000 {
362 compatible = "ti,am654-hbmc";
363 reg = <0x00 0x47034000 0x00 0x100>,
364 <0x05 0x00000000 0x01 0x0000000>;
365 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
366 clocks = <&k3_clks 102 0>;
367 assigned-clocks = <&k3_clks 102 5>;
368 assigned-clock-rates = <333333333>;
369 #address-cells = <2>;
370 #size-cells = <1>;
371 mux-controls = <&hbmc_mux 0>;
372 status = "disabled";
373 };
374
cb27354b 375 ospi0: spi@47040000 {
f1b6f6e7 376 compatible = "ti,am654-ospi", "cdns,qspi-nor";
cb27354b
VR		 377 reg = <0x0 0x47040000 0x0 0x100>,
378 <0x5 0x00000000 0x1 0x0000000>;
379 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
380 cdns,fifo-depth = <256>;
381 cdns,fifo-width = <4>;
382 cdns,trigger-address = <0x0>;
383 clocks = <&k3_clks 103 0>;
384 assigned-clocks = <&k3_clks 103 0>;
385 assigned-clock-parents = <&k3_clks 103 2>;
386 assigned-clock-rates = <166666666>;
387 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
388 #address-cells = <1>;
389 #size-cells = <0>;
73676c48 390 status = "disabled";
cb27354b
VR		 391 };
392
393 ospi1: spi@47050000 {
f1b6f6e7 394 compatible = "ti,am654-ospi", "cdns,qspi-nor";
cb27354b
VR		 395 reg = <0x0 0x47050000 0x0 0x100>,
396 <0x7 0x00000000 0x1 0x00000000>;
397 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
398 cdns,fifo-depth = <256>;
399 cdns,fifo-width = <4>;
400 cdns,trigger-address = <0x0>;
401 clocks = <&k3_clks 104 0>;
402 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
403 #address-cells = <1>;
404 #size-cells = <0>;
73676c48 405 status = "disabled";
cb27354b
VR		 406 };
407 };
408
409 tscadc0: tscadc@40200000 {
410 compatible = "ti,am3359-tscadc";
411 reg = <0x0 0x40200000 0x0 0x1000>;
412 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
413 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
414 clocks = <&k3_clks 0 1>;
415 assigned-clocks = <&k3_clks 0 3>;
416 assigned-clock-rates = <60000000>;
e5bad300 417 clock-names = "fck";
5ccd8dfe
VR		 418 dmas = <&main_udmap 0x7400>,
419 <&main_udmap 0x7401>;
420 dma-names = "fifo0", "fifo1";
a5a4cdda 421 status = "disabled";
cb27354b
VR		 422
423 adc {
424 #io-channel-cells = <1>;
425 compatible = "ti,am3359-adc";
426 };
427 };
428
429 tscadc1: tscadc@40210000 {
430 compatible = "ti,am3359-tscadc";
431 reg = <0x0 0x40210000 0x0 0x1000>;
432 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
433 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
434 clocks = <&k3_clks 1 1>;
435 assigned-clocks = <&k3_clks 1 3>;
436 assigned-clock-rates = <60000000>;
e5bad300 437 clock-names = "fck";
5ccd8dfe
VR		 438 dmas = <&main_udmap 0x7402>,
439 <&main_udmap 0x7403>;
440 dma-names = "fifo0", "fifo1";
a5a4cdda 441 status = "disabled";
cb27354b
VR		 442
443 adc {
444 #io-channel-cells = <1>;
445 compatible = "ti,am3359-adc";
446 };
447 };
6f73c1e5 448
9ecdb6d6 449 mcu_navss: bus@28380000 {
6507bfa7 450 compatible = "simple-bus";
6f73c1e5
PU		 451 #address-cells = <2>;
452 #size-cells = <2>;
9ecdb6d6 453 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
6f73c1e5
PU		 454 dma-coherent;
455 dma-ranges;
456
457 ti,sci-dev-id = <232>;
458
459 mcu_ringacc: ringacc@2b800000 {
460 compatible = "ti,am654-navss-ringacc";
414772b8
KK		 461 reg = <0x0 0x2b800000 0x0 0x400000>,
462 <0x0 0x2b000000 0x0 0x400000>,
463 <0x0 0x28590000 0x0 0x100>,
702110c2
VR		 464 <0x0 0x2a500000 0x0 0x40000>,
465 <0x0 0x28440000 0x0 0x40000>;
466 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
6f73c1e5
PU		 467 ti,num-rings = <286>;
468 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
469 ti,sci = <&dmsc>;
470 ti,sci-dev-id = <235>;
471 msi-parent = <&main_udmass_inta>;
472 };
473
474 mcu_udmap: dma-controller@285c0000 {
475 compatible = "ti,j721e-navss-mcu-udmap";
414772b8
KK		 476 reg = <0x0 0x285c0000 0x0 0x100>,
477 <0x0 0x2a800000 0x0 0x40000>,
1b62a3cf
MC		 478 <0x0 0x2aa00000 0x0 0x40000>,
479 <0x0 0x284a0000 0x0 0x4000>,
480 <0x0 0x284c0000 0x0 0x4000>,
481 <0x0 0x28400000 0x0 0x2000>;
482 reg-names = "gcfg", "rchanrt", "tchanrt",
483 "tchan", "rchan", "rflow";
6f73c1e5
PU		 484 msi-parent = <&main_udmass_inta>;
485 #dma-cells = <1>;
486
487 ti,sci = <&dmsc>;
488 ti,sci-dev-id = <236>;
489 ti,ringacc = <&mcu_ringacc>;
490
491 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
492 <0x0f>; /* TX_HCHAN */
493 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
494 <0x0b>; /* RX_HCHAN */
495 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
496 };
497 };
ae7fdac8 498
753904da
NM		 499 secure_proxy_mcu: mailbox@2a480000 {
500 compatible = "ti,am654-secure-proxy";
501 #mbox-cells = <1>;
502 reg-names = "target_data", "rt", "scfg";
503 reg = <0x0 0x2a480000 0x0 0x80000>,
504 <0x0 0x2a380000 0x0 0x80000>,
505 <0x0 0x2a400000 0x0 0x80000>;
506 /*
507 * Marked Disabled:
508 * Node is incomplete as it is meant for bootloaders and
509 * firmware on non-MPU processors
510 */
511 status = "disabled";
512 };
513
ae7fdac8
GS		 514 mcu_cpsw: ethernet@46000000 {
515 compatible = "ti,j721e-cpsw-nuss";
516 #address-cells = <2>;
517 #size-cells = <2>;
518 reg = <0x0 0x46000000 0x0 0x200000>;
519 reg-names = "cpsw_nuss";
520 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
521 dma-coherent;
522 clocks = <&k3_clks 18 22>;
523 clock-names = "fck";
524 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
525
526 dmas = <&mcu_udmap 0xf000>,
527 <&mcu_udmap 0xf001>,
528 <&mcu_udmap 0xf002>,
529 <&mcu_udmap 0xf003>,
530 <&mcu_udmap 0xf004>,
531 <&mcu_udmap 0xf005>,
532 <&mcu_udmap 0xf006>,
533 <&mcu_udmap 0xf007>,
534 <&mcu_udmap 0x7000>;
535 dma-names = "tx0", "tx1", "tx2", "tx3",
536 "tx4", "tx5", "tx6", "tx7",
537 "rx";
538
539 ethernet-ports {
540 #address-cells = <1>;
541 #size-cells = <0>;
542
543 cpsw_port1: port@1 {
544 reg = <1>;
545 ti,mac-only;
546 label = "port1";
547 ti,syscon-efuse = <&mcu_conf 0x200>;
548 phys = <&phy_gmii_sel 1>;
549 };
550 };
551
552 davinci_mdio: mdio@f00 {
553 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
554 reg = <0x0 0xf00 0x0 0x100>;
555 #address-cells = <1>;
556 #size-cells = <0>;
557 clocks = <&k3_clks 18 22>;
558 clock-names = "fck";
559 bus_freq = <1000000>;
560 };
29390928 561
ef2d1363
GS		 562 cpts@3d000 {
563 compatible = "ti,am65-cpts";
564 reg = <0x0 0x3d000 0x0 0x400>;
29390928
GS		 565 clocks = <&k3_clks 18 2>;
566 clock-names = "cpts";
567 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
568 interrupt-names = "cpts";
569 ti,cpts-ext-ts-inputs = <4>;
570 ti,cpts-periodic-outputs = <2>;
571 };
ae7fdac8 572 };
dd74c945
SA		 573
574 mcu_r5fss0: r5fss@41000000 {
575 compatible = "ti,j721e-r5fss";
576 ti,cluster-mode = <1>;
577 #address-cells = <1>;
578 #size-cells = <1>;
579 ranges = <0x41000000 0x00 0x41000000 0x20000>,
580 <0x41400000 0x00 0x41400000 0x20000>;
581 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
582
583 mcu_r5fss0_core0: r5f@41000000 {
584 compatible = "ti,j721e-r5f";
585 reg = <0x41000000 0x00008000>,
586 <0x41010000 0x00008000>;
587 reg-names = "atcm", "btcm";
588 ti,sci = <&dmsc>;
589 ti,sci-dev-id = <250>;
590 ti,sci-proc-ids = <0x01 0xff>;
591 resets = <&k3_reset 250 1>;
592 firmware-name = "j7-mcu-r5f0_0-fw";
593 ti,atcm-enable = <1>;
594 ti,btcm-enable = <1>;
595 ti,loczrama = <1>;
596 };
597
598 mcu_r5fss0_core1: r5f@41400000 {
599 compatible = "ti,j721e-r5f";
600 reg = <0x41400000 0x00008000>,
601 <0x41410000 0x00008000>;
602 reg-names = "atcm", "btcm";
603 ti,sci = <&dmsc>;
604 ti,sci-dev-id = <251>;
605 ti,sci-proc-ids = <0x02 0xff>;
606 resets = <&k3_reset 251 1>;
607 firmware-name = "j7-mcu-r5f0_1-fw";
608 ti,atcm-enable = <1>;
609 ti,btcm-enable = <1>;
610 ti,loczrama = <1>;
611 };
612 };
4688a4fc
FA		 613
614 mcu_mcan0: can@40528000 {
615 compatible = "bosch,m_can";
616 reg = <0x00 0x40528000 0x00 0x200>,
617 <0x00 0x40500000 0x00 0x8000>;
618 reg-names = "m_can", "message_ram";
619 power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>;
620 clocks = <&k3_clks 172 0>, <&k3_clks 172 1>;
621 clock-names = "hclk", "cclk";
622 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
624 interrupt-names = "int0", "int1";
625 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
39e7758b 626 status = "disabled";
4688a4fc
FA		 627 };
628
629 mcu_mcan1: can@40568000 {
630 compatible = "bosch,m_can";
631 reg = <0x00 0x40568000 0x00 0x200>,
632 <0x00 0x40540000 0x00 0x8000>;
633 reg-names = "m_can", "message_ram";
634 power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>;
635 clocks = <&k3_clks 173 0>, <&k3_clks 173 1>;
636 clock-names = "hclk", "cclk";
637 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
639 interrupt-names = "int0", "int1";
640 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
39e7758b 641 status = "disabled";
4688a4fc 642 };
76aa309f
VA		 643
644 mcu_spi0: spi@40300000 {
645 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
646 reg = <0x00 0x040300000 0x00 0x400>;
647 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
648 #address-cells = <1>;
649 #size-cells = <0>;
650 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
651 clocks = <&k3_clks 274 0>;
652 status = "disabled";
653 };
654
655 mcu_spi1: spi@40310000 {
656 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
657 reg = <0x00 0x040310000 0x00 0x400>;
658 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
659 #address-cells = <1>;
660 #size-cells = <0>;
661 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
662 clocks = <&k3_clks 275 0>;
663 status = "disabled";
664 };
665
666 mcu_spi2: spi@40320000 {
667 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
668 reg = <0x00 0x040320000 0x00 0x400>;
669 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
670 #address-cells = <1>;
671 #size-cells = <0>;
672 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
673 clocks = <&k3_clks 276 0>;
674 status = "disabled";
675 };
8fb4e87c
K		 676
677 wkup_vtm0: temperature-sensor@42040000 {
678 compatible = "ti,j721e-vtm";
679 reg = <0x00 0x42040000 0x00 0x350>,
680 <0x00 0x42050000 0x00 0x350>,
681 <0x00 0x43000300 0x00 0x10>;
682 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
683 #thermal-sensor-cells = <1>;
684 };
0997638a
NMF		 685
686 mcu_esm: esm@40800000 {
687 compatible = "ti,j721e-esm";
688 reg = <0x00 0x40800000 0x00 0x1000>;
689 ti,esm-pins = <95>;
690 bootph-pre-ram;
691 };
2d87061e 692};
Linux 6.x block layer and io_uring tree(s)