Commit | Line | Data |
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111f6dac | 1 | // SPDX-License-Identifier: GPL-2.0-only OR MIT |
2d87061e NM |
2 | /* |
3 | * Device Tree Source for J721E SoC Family Main Domain peripherals | |
4 | * | |
111f6dac | 5 | * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ |
2d87061e | 6 | */ |
afd094eb | 7 | #include <dt-bindings/phy/phy.h> |
92c996f4 | 8 | #include <dt-bindings/phy/phy-ti.h> |
b766e3b0 | 9 | #include <dt-bindings/mux/mux.h> |
8d08d7aa JC |
10 | |
11 | #include "k3-serdes.h" | |
2d87061e | 12 | |
5c6d0b55 KVA |
13 | / { |
14 | cmn_refclk: clock-cmnrefclk { | |
15 | #clock-cells = <0>; | |
16 | compatible = "fixed-clock"; | |
17 | clock-frequency = <0>; | |
18 | }; | |
19 | ||
20 | cmn_refclk1: clock-cmnrefclk1 { | |
21 | #clock-cells = <0>; | |
22 | compatible = "fixed-clock"; | |
23 | clock-frequency = <0>; | |
24 | }; | |
25 | }; | |
26 | ||
2d87061e NM |
27 | &cbass_main { |
28 | msmc_ram: sram@70000000 { | |
29 | compatible = "mmio-sram"; | |
30 | reg = <0x0 0x70000000 0x0 0x800000>; | |
31 | #address-cells = <1>; | |
32 | #size-cells = <1>; | |
33 | ranges = <0x0 0x0 0x70000000 0x800000>; | |
34 | ||
35 | atf-sram@0 { | |
36 | reg = <0x0 0x20000>; | |
37 | }; | |
38 | }; | |
39 | ||
b766e3b0 KVA |
40 | scm_conf: scm-conf@100000 { |
41 | compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; | |
42 | reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ | |
43 | #address-cells = <1>; | |
44 | #size-cells = <1>; | |
45 | ranges = <0x0 0x0 0x00100000 0x1c000>; | |
46 | ||
3f92a5be | 47 | serdes_ln_ctrl: mux-controller@4080 { |
4cd6d56c AD |
48 | compatible = "reg-mux"; |
49 | reg = <0x4080 0x50>; | |
b766e3b0 | 50 | #mux-control-cells = <1>; |
4cd6d56c AD |
51 | mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ |
52 | <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ | |
53 | <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ | |
54 | <0x30 0x3>, <0x34 0x3>, /* SERDES3 lane0/1 select */ | |
55 | <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */ | |
56 | <0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */ | |
c65176fd RQ |
57 | idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, |
58 | <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, | |
59 | <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, | |
60 | <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>, | |
61 | <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, | |
62 | <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; | |
b766e3b0 | 63 | }; |
4716053a | 64 | |
a2ff7f11 SV |
65 | cpsw0_phy_gmii_sel: phy@4044 { |
66 | compatible = "ti,j721e-cpsw9g-phy-gmii-sel"; | |
67 | ti,qsgmii-main-ports = <2>, <2>; | |
68 | reg = <0x4044 0x20>; | |
69 | #phy-cells = <1>; | |
70 | }; | |
71 | ||
4716053a | 72 | usb_serdes_mux: mux-controller@4000 { |
62b19a64 AD |
73 | compatible = "reg-mux"; |
74 | reg = <0x4000 0x20>; | |
4716053a | 75 | #mux-control-cells = <1>; |
62b19a64 AD |
76 | mux-reg-masks = <0x0 0x8000000>, /* USB0 to SERDES0/3 mux */ |
77 | <0x10 0x8000000>; /* USB1 to SERDES1/2 mux */ | |
20f67d1d VP |
78 | }; |
79 | ||
80 | ehrpwm_tbclk: clock-controller@4140 { | |
2a7cc7be | 81 | compatible = "ti,am654-ehrpwm-tbclk"; |
20f67d1d VP |
82 | reg = <0x4140 0x18>; |
83 | #clock-cells = <1>; | |
84 | }; | |
85 | }; | |
86 | ||
87 | main_ehrpwm0: pwm@3000000 { | |
88 | compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; | |
89 | #pwm-cells = <3>; | |
90 | reg = <0x00 0x3000000 0x00 0x100>; | |
91 | power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; | |
92 | clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>; | |
93 | clock-names = "tbclk", "fck"; | |
94 | status = "disabled"; | |
95 | }; | |
96 | ||
97 | main_ehrpwm1: pwm@3010000 { | |
98 | compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; | |
99 | #pwm-cells = <3>; | |
100 | reg = <0x00 0x3010000 0x00 0x100>; | |
101 | power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; | |
102 | clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>; | |
103 | clock-names = "tbclk", "fck"; | |
104 | status = "disabled"; | |
105 | }; | |
106 | ||
107 | main_ehrpwm2: pwm@3020000 { | |
108 | compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; | |
109 | #pwm-cells = <3>; | |
110 | reg = <0x00 0x3020000 0x00 0x100>; | |
111 | power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; | |
112 | clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>; | |
113 | clock-names = "tbclk", "fck"; | |
114 | status = "disabled"; | |
115 | }; | |
116 | ||
117 | main_ehrpwm3: pwm@3030000 { | |
118 | compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; | |
119 | #pwm-cells = <3>; | |
120 | reg = <0x00 0x3030000 0x00 0x100>; | |
121 | power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; | |
122 | clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>; | |
123 | clock-names = "tbclk", "fck"; | |
124 | status = "disabled"; | |
125 | }; | |
126 | ||
127 | main_ehrpwm4: pwm@3040000 { | |
128 | compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; | |
129 | #pwm-cells = <3>; | |
130 | reg = <0x00 0x3040000 0x00 0x100>; | |
131 | power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; | |
132 | clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>; | |
133 | clock-names = "tbclk", "fck"; | |
134 | status = "disabled"; | |
135 | }; | |
136 | ||
137 | main_ehrpwm5: pwm@3050000 { | |
138 | compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; | |
139 | #pwm-cells = <3>; | |
140 | reg = <0x00 0x3050000 0x00 0x100>; | |
141 | power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; | |
142 | clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>; | |
143 | clock-names = "tbclk", "fck"; | |
144 | status = "disabled"; | |
b766e3b0 KVA |
145 | }; |
146 | ||
2d87061e NM |
147 | gic500: interrupt-controller@1800000 { |
148 | compatible = "arm,gic-v3"; | |
149 | #address-cells = <2>; | |
150 | #size-cells = <2>; | |
151 | ranges; | |
152 | #interrupt-cells = <3>; | |
153 | interrupt-controller; | |
154 | reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ | |
a06ed27f NM |
155 | <0x00 0x01900000 0x00 0x100000>, /* GICR */ |
156 | <0x00 0x6f000000 0x00 0x2000>, /* GICC */ | |
157 | <0x00 0x6f010000 0x00 0x1000>, /* GICH */ | |
158 | <0x00 0x6f020000 0x00 0x2000>; /* GICV */ | |
2d87061e NM |
159 | |
160 | /* vcpumntirq: virtual CPU interface maintenance interrupt */ | |
161 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
162 | ||
6e6972f9 | 163 | gic_its: msi-controller@1820000 { |
2d87061e NM |
164 | compatible = "arm,gic-v3-its"; |
165 | reg = <0x00 0x01820000 0x00 0x10000>; | |
166 | socionext,synquacer-pre-its = <0x1000000 0x400000>; | |
167 | msi-controller; | |
168 | #msi-cells = <1>; | |
169 | }; | |
170 | }; | |
171 | ||
cab12bad | 172 | main_gpio_intr: interrupt-controller@a00000 { |
073086fc | 173 | compatible = "ti,sci-intr"; |
cab12bad | 174 | reg = <0x00 0x00a00000 0x00 0x800>; |
073086fc LV |
175 | ti,intr-trigger-type = <1>; |
176 | interrupt-controller; | |
177 | interrupt-parent = <&gic500>; | |
8d523f09 | 178 | #interrupt-cells = <1>; |
073086fc | 179 | ti,sci = <&dmsc>; |
8d523f09 LV |
180 | ti,sci-dev-id = <131>; |
181 | ti,interrupt-ranges = <8 392 56>; | |
073086fc LV |
182 | }; |
183 | ||
9ecdb6d6 | 184 | main_navss: bus@30000000 { |
6507bfa7 | 185 | compatible = "simple-bus"; |
1463a70d SA |
186 | #address-cells = <2>; |
187 | #size-cells = <2>; | |
9ecdb6d6 | 188 | ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; |
6f73c1e5 PU |
189 | dma-coherent; |
190 | dma-ranges; | |
191 | ||
192 | ti,sci-dev-id = <199>; | |
1463a70d | 193 | |
cab12bad | 194 | main_navss_intr: interrupt-controller@310e0000 { |
1463a70d | 195 | compatible = "ti,sci-intr"; |
cab12bad | 196 | reg = <0x0 0x310e0000 0x0 0x4000>; |
1463a70d SA |
197 | ti,intr-trigger-type = <4>; |
198 | interrupt-controller; | |
199 | interrupt-parent = <&gic500>; | |
8d523f09 | 200 | #interrupt-cells = <1>; |
1463a70d | 201 | ti,sci = <&dmsc>; |
8d523f09 LV |
202 | ti,sci-dev-id = <213>; |
203 | ti,interrupt-ranges = <0 64 64>, | |
204 | <64 448 64>, | |
205 | <128 672 64>; | |
1463a70d | 206 | }; |
073086fc LV |
207 | |
208 | main_udmass_inta: interrupt-controller@33d00000 { | |
209 | compatible = "ti,sci-inta"; | |
210 | reg = <0x0 0x33d00000 0x0 0x100000>; | |
211 | interrupt-controller; | |
212 | interrupt-parent = <&main_navss_intr>; | |
213 | msi-controller; | |
15ffd94a | 214 | #interrupt-cells = <0>; |
073086fc LV |
215 | ti,sci = <&dmsc>; |
216 | ti,sci-dev-id = <209>; | |
8d523f09 | 217 | ti,interrupt-ranges = <0 0 256>; |
073086fc | 218 | }; |
7b472ced | 219 | |
515c0340 PU |
220 | secure_proxy_main: mailbox@32c00000 { |
221 | compatible = "ti,am654-secure-proxy"; | |
222 | #mbox-cells = <1>; | |
223 | reg-names = "target_data", "rt", "scfg"; | |
224 | reg = <0x00 0x32c00000 0x00 0x100000>, | |
225 | <0x00 0x32400000 0x00 0x100000>, | |
226 | <0x00 0x32800000 0x00 0x100000>; | |
227 | interrupt-names = "rx_011"; | |
228 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
229 | }; | |
230 | ||
d0c72c77 | 231 | smmu0: iommu@36600000 { |
515c0340 PU |
232 | compatible = "arm,smmu-v3"; |
233 | reg = <0x0 0x36600000 0x0 0x100000>; | |
234 | interrupt-parent = <&gic500>; | |
235 | interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, | |
236 | <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; | |
237 | interrupt-names = "eventq", "gerror"; | |
238 | #iommu-cells = <1>; | |
239 | }; | |
240 | ||
7b472ced SA |
241 | hwspinlock: spinlock@30e00000 { |
242 | compatible = "ti,am654-hwspinlock"; | |
243 | reg = <0x00 0x30e00000 0x00 0x1000>; | |
244 | #hwlock-cells = <1>; | |
245 | }; | |
56f18582 SA |
246 | |
247 | mailbox0_cluster0: mailbox@31f80000 { | |
248 | compatible = "ti,am654-mailbox"; | |
249 | reg = <0x00 0x31f80000 0x00 0x200>; | |
250 | #mbox-cells = <1>; | |
251 | ti,mbox-num-users = <4>; | |
252 | ti,mbox-num-fifos = <16>; | |
253 | interrupt-parent = <&main_navss_intr>; | |
7e48b665 | 254 | status = "disabled"; |
56f18582 SA |
255 | }; |
256 | ||
257 | mailbox0_cluster1: mailbox@31f81000 { | |
258 | compatible = "ti,am654-mailbox"; | |
259 | reg = <0x00 0x31f81000 0x00 0x200>; | |
260 | #mbox-cells = <1>; | |
261 | ti,mbox-num-users = <4>; | |
262 | ti,mbox-num-fifos = <16>; | |
263 | interrupt-parent = <&main_navss_intr>; | |
7e48b665 | 264 | status = "disabled"; |
56f18582 SA |
265 | }; |
266 | ||
267 | mailbox0_cluster2: mailbox@31f82000 { | |
268 | compatible = "ti,am654-mailbox"; | |
269 | reg = <0x00 0x31f82000 0x00 0x200>; | |
270 | #mbox-cells = <1>; | |
271 | ti,mbox-num-users = <4>; | |
272 | ti,mbox-num-fifos = <16>; | |
273 | interrupt-parent = <&main_navss_intr>; | |
7e48b665 | 274 | status = "disabled"; |
56f18582 SA |
275 | }; |
276 | ||
277 | mailbox0_cluster3: mailbox@31f83000 { | |
278 | compatible = "ti,am654-mailbox"; | |
279 | reg = <0x00 0x31f83000 0x00 0x200>; | |
280 | #mbox-cells = <1>; | |
281 | ti,mbox-num-users = <4>; | |
282 | ti,mbox-num-fifos = <16>; | |
283 | interrupt-parent = <&main_navss_intr>; | |
7e48b665 | 284 | status = "disabled"; |
56f18582 SA |
285 | }; |
286 | ||
287 | mailbox0_cluster4: mailbox@31f84000 { | |
288 | compatible = "ti,am654-mailbox"; | |
289 | reg = <0x00 0x31f84000 0x00 0x200>; | |
290 | #mbox-cells = <1>; | |
291 | ti,mbox-num-users = <4>; | |
292 | ti,mbox-num-fifos = <16>; | |
293 | interrupt-parent = <&main_navss_intr>; | |
7e48b665 | 294 | status = "disabled"; |
56f18582 SA |
295 | }; |
296 | ||
297 | mailbox0_cluster5: mailbox@31f85000 { | |
298 | compatible = "ti,am654-mailbox"; | |
299 | reg = <0x00 0x31f85000 0x00 0x200>; | |
300 | #mbox-cells = <1>; | |
301 | ti,mbox-num-users = <4>; | |
302 | ti,mbox-num-fifos = <16>; | |
303 | interrupt-parent = <&main_navss_intr>; | |
7e48b665 | 304 | status = "disabled"; |
56f18582 SA |
305 | }; |
306 | ||
307 | mailbox0_cluster6: mailbox@31f86000 { | |
308 | compatible = "ti,am654-mailbox"; | |
309 | reg = <0x00 0x31f86000 0x00 0x200>; | |
310 | #mbox-cells = <1>; | |
311 | ti,mbox-num-users = <4>; | |
312 | ti,mbox-num-fifos = <16>; | |
313 | interrupt-parent = <&main_navss_intr>; | |
7e48b665 | 314 | status = "disabled"; |
56f18582 SA |
315 | }; |
316 | ||
317 | mailbox0_cluster7: mailbox@31f87000 { | |
318 | compatible = "ti,am654-mailbox"; | |
319 | reg = <0x00 0x31f87000 0x00 0x200>; | |
320 | #mbox-cells = <1>; | |
321 | ti,mbox-num-users = <4>; | |
322 | ti,mbox-num-fifos = <16>; | |
323 | interrupt-parent = <&main_navss_intr>; | |
7e48b665 | 324 | status = "disabled"; |
56f18582 SA |
325 | }; |
326 | ||
327 | mailbox0_cluster8: mailbox@31f88000 { | |
328 | compatible = "ti,am654-mailbox"; | |
329 | reg = <0x00 0x31f88000 0x00 0x200>; | |
330 | #mbox-cells = <1>; | |
331 | ti,mbox-num-users = <4>; | |
332 | ti,mbox-num-fifos = <16>; | |
333 | interrupt-parent = <&main_navss_intr>; | |
7e48b665 | 334 | status = "disabled"; |
56f18582 SA |
335 | }; |
336 | ||
337 | mailbox0_cluster9: mailbox@31f89000 { | |
338 | compatible = "ti,am654-mailbox"; | |
339 | reg = <0x00 0x31f89000 0x00 0x200>; | |
340 | #mbox-cells = <1>; | |
341 | ti,mbox-num-users = <4>; | |
342 | ti,mbox-num-fifos = <16>; | |
343 | interrupt-parent = <&main_navss_intr>; | |
7e48b665 | 344 | status = "disabled"; |
56f18582 SA |
345 | }; |
346 | ||
347 | mailbox0_cluster10: mailbox@31f8a000 { | |
348 | compatible = "ti,am654-mailbox"; | |
349 | reg = <0x00 0x31f8a000 0x00 0x200>; | |
350 | #mbox-cells = <1>; | |
351 | ti,mbox-num-users = <4>; | |
352 | ti,mbox-num-fifos = <16>; | |
353 | interrupt-parent = <&main_navss_intr>; | |
7e48b665 | 354 | status = "disabled"; |
56f18582 SA |
355 | }; |
356 | ||
357 | mailbox0_cluster11: mailbox@31f8b000 { | |
358 | compatible = "ti,am654-mailbox"; | |
359 | reg = <0x00 0x31f8b000 0x00 0x200>; | |
360 | #mbox-cells = <1>; | |
361 | ti,mbox-num-users = <4>; | |
362 | ti,mbox-num-fifos = <16>; | |
363 | interrupt-parent = <&main_navss_intr>; | |
7e48b665 | 364 | status = "disabled"; |
56f18582 | 365 | }; |
6f73c1e5 PU |
366 | |
367 | main_ringacc: ringacc@3c000000 { | |
368 | compatible = "ti,am654-navss-ringacc"; | |
414772b8 KK |
369 | reg = <0x0 0x3c000000 0x0 0x400000>, |
370 | <0x0 0x38000000 0x0 0x400000>, | |
371 | <0x0 0x31120000 0x0 0x100>, | |
702110c2 VR |
372 | <0x0 0x33000000 0x0 0x40000>, |
373 | <0x0 0x31080000 0x0 0x40000>; | |
374 | reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; | |
6f73c1e5 PU |
375 | ti,num-rings = <1024>; |
376 | ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ | |
377 | ti,sci = <&dmsc>; | |
378 | ti,sci-dev-id = <211>; | |
379 | msi-parent = <&main_udmass_inta>; | |
380 | }; | |
381 | ||
382 | main_udmap: dma-controller@31150000 { | |
383 | compatible = "ti,j721e-navss-main-udmap"; | |
414772b8 KK |
384 | reg = <0x0 0x31150000 0x0 0x100>, |
385 | <0x0 0x34000000 0x0 0x100000>, | |
1b62a3cf MC |
386 | <0x0 0x35000000 0x0 0x100000>, |
387 | <0x0 0x30b00000 0x0 0x20000>, | |
388 | <0x0 0x30c00000 0x0 0x10000>, | |
389 | <0x0 0x30d00000 0x0 0x8000>; | |
390 | reg-names = "gcfg", "rchanrt", "tchanrt", | |
391 | "tchan", "rchan", "rflow"; | |
6f73c1e5 PU |
392 | msi-parent = <&main_udmass_inta>; |
393 | #dma-cells = <1>; | |
394 | ||
395 | ti,sci = <&dmsc>; | |
396 | ti,sci-dev-id = <212>; | |
397 | ti,ringacc = <&main_ringacc>; | |
398 | ||
399 | ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ | |
400 | <0x0f>, /* TX_HCHAN */ | |
401 | <0x10>; /* TX_UHCHAN */ | |
402 | ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ | |
403 | <0x0b>, /* RX_HCHAN */ | |
404 | <0x0c>; /* RX_UHCHAN */ | |
405 | ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ | |
406 | }; | |
461d6d05 GS |
407 | |
408 | cpts@310d0000 { | |
409 | compatible = "ti,j721e-cpts"; | |
410 | reg = <0x0 0x310d0000 0x0 0x400>; | |
411 | reg-names = "cpts"; | |
412 | clocks = <&k3_clks 201 1>; | |
413 | clock-names = "cpts"; | |
8d523f09 | 414 | interrupts-extended = <&main_navss_intr 391>; |
461d6d05 GS |
415 | interrupt-names = "cpts"; |
416 | ti,cpts-periodic-outputs = <6>; | |
417 | ti,cpts-ext-ts-inputs = <8>; | |
418 | }; | |
1463a70d SA |
419 | }; |
420 | ||
a2ff7f11 SV |
421 | cpsw0: ethernet@c000000 { |
422 | compatible = "ti,j721e-cpswxg-nuss"; | |
423 | #address-cells = <2>; | |
424 | #size-cells = <2>; | |
425 | reg = <0x0 0xc000000 0x0 0x200000>; | |
426 | reg-names = "cpsw_nuss"; | |
427 | ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>; | |
428 | clocks = <&k3_clks 19 89>; | |
429 | clock-names = "fck"; | |
430 | power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; | |
431 | ||
432 | dmas = <&main_udmap 0xca00>, | |
433 | <&main_udmap 0xca01>, | |
434 | <&main_udmap 0xca02>, | |
435 | <&main_udmap 0xca03>, | |
436 | <&main_udmap 0xca04>, | |
437 | <&main_udmap 0xca05>, | |
438 | <&main_udmap 0xca06>, | |
439 | <&main_udmap 0xca07>, | |
440 | <&main_udmap 0x4a00>; | |
441 | dma-names = "tx0", "tx1", "tx2", "tx3", | |
442 | "tx4", "tx5", "tx6", "tx7", | |
443 | "rx"; | |
444 | ||
445 | status = "disabled"; | |
446 | ||
447 | ethernet-ports { | |
448 | #address-cells = <1>; | |
449 | #size-cells = <0>; | |
450 | cpsw0_port1: port@1 { | |
451 | reg = <1>; | |
452 | ti,mac-only; | |
453 | label = "port1"; | |
454 | status = "disabled"; | |
455 | }; | |
456 | ||
457 | cpsw0_port2: port@2 { | |
458 | reg = <2>; | |
459 | ti,mac-only; | |
460 | label = "port2"; | |
461 | status = "disabled"; | |
462 | }; | |
463 | ||
464 | cpsw0_port3: port@3 { | |
465 | reg = <3>; | |
466 | ti,mac-only; | |
467 | label = "port3"; | |
468 | status = "disabled"; | |
469 | }; | |
470 | ||
471 | cpsw0_port4: port@4 { | |
472 | reg = <4>; | |
473 | ti,mac-only; | |
474 | label = "port4"; | |
475 | status = "disabled"; | |
476 | }; | |
477 | ||
478 | cpsw0_port5: port@5 { | |
479 | reg = <5>; | |
480 | ti,mac-only; | |
481 | label = "port5"; | |
482 | status = "disabled"; | |
483 | }; | |
484 | ||
485 | cpsw0_port6: port@6 { | |
486 | reg = <6>; | |
487 | ti,mac-only; | |
488 | label = "port6"; | |
489 | status = "disabled"; | |
490 | }; | |
491 | ||
492 | cpsw0_port7: port@7 { | |
493 | reg = <7>; | |
494 | ti,mac-only; | |
495 | label = "port7"; | |
496 | status = "disabled"; | |
497 | }; | |
498 | ||
499 | cpsw0_port8: port@8 { | |
500 | reg = <8>; | |
501 | ti,mac-only; | |
502 | label = "port8"; | |
503 | status = "disabled"; | |
504 | }; | |
505 | }; | |
506 | ||
507 | cpsw9g_mdio: mdio@f00 { | |
508 | compatible = "ti,cpsw-mdio","ti,davinci_mdio"; | |
509 | reg = <0x0 0xf00 0x0 0x100>; | |
510 | #address-cells = <1>; | |
511 | #size-cells = <0>; | |
512 | clocks = <&k3_clks 19 89>; | |
513 | clock-names = "fck"; | |
514 | bus_freq = <1000000>; | |
515 | status = "disabled"; | |
516 | }; | |
517 | ||
518 | cpts@3d000 { | |
519 | compatible = "ti,j721e-cpts"; | |
520 | reg = <0x0 0x3d000 0x0 0x400>; | |
521 | clocks = <&k3_clks 19 16>; | |
522 | clock-names = "cpts"; | |
523 | interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
524 | interrupt-names = "cpts"; | |
525 | ti,cpts-ext-ts-inputs = <4>; | |
526 | ti,cpts-periodic-outputs = <2>; | |
527 | }; | |
528 | }; | |
529 | ||
8ebcaaae K |
530 | main_crypto: crypto@4e00000 { |
531 | compatible = "ti,j721e-sa2ul"; | |
532 | reg = <0x0 0x4e00000 0x0 0x1200>; | |
533 | power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; | |
534 | #address-cells = <2>; | |
535 | #size-cells = <2>; | |
536 | ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; | |
537 | ||
8ebcaaae K |
538 | dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, |
539 | <&main_udmap 0x4001>; | |
540 | dma-names = "tx", "rx1", "rx2"; | |
8ebcaaae K |
541 | |
542 | rng: rng@4e10000 { | |
543 | compatible = "inside-secure,safexcel-eip76"; | |
544 | reg = <0x0 0x4e10000 0x0 0x7d>; | |
545 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
8ebcaaae K |
546 | }; |
547 | }; | |
548 | ||
dcccf770 | 549 | main_pmx0: pinctrl@11c000 { |
2d87061e NM |
550 | compatible = "pinctrl-single"; |
551 | /* Proxy 0 addressing */ | |
552 | reg = <0x0 0x11c000 0x0 0x2b4>; | |
553 | #pinctrl-cells = <1>; | |
554 | pinctrl-single,register-width = <32>; | |
555 | pinctrl-single,function-mask = <0xffffffff>; | |
556 | }; | |
557 | ||
72a44d1c NM |
558 | /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ |
559 | main_timerio_input: pinctrl@104200 { | |
560 | compatible = "pinctrl-single"; | |
561 | reg = <0x00 0x104200 0x00 0x50>; | |
562 | #pinctrl-cells = <1>; | |
563 | pinctrl-single,register-width = <32>; | |
564 | pinctrl-single,function-mask = <0x00000007>; | |
565 | }; | |
566 | ||
567 | /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ | |
568 | main_timerio_output: pinctrl@104280 { | |
569 | compatible = "pinctrl-single"; | |
570 | reg = <0x00 0x104280 0x00 0x20>; | |
571 | #pinctrl-cells = <1>; | |
572 | pinctrl-single,register-width = <32>; | |
573 | pinctrl-single,function-mask = <0x0000001f>; | |
574 | }; | |
575 | ||
491821ce VA |
576 | ti_csi2rx0: ticsi2rx@4500000 { |
577 | compatible = "ti,j721e-csi2rx-shim"; | |
578 | reg = <0x0 0x4500000 0x0 0x1000>; | |
579 | ranges; | |
580 | #address-cells = <2>; | |
581 | #size-cells = <2>; | |
582 | dmas = <&main_udmap 0x4940>; | |
583 | dma-names = "rx0"; | |
584 | power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; | |
585 | status = "disabled"; | |
586 | ||
587 | cdns_csi2rx0: csi-bridge@4504000 { | |
588 | compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; | |
589 | reg = <0x0 0x4504000 0x0 0x1000>; | |
590 | clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, | |
591 | <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; | |
592 | clock-names = "sys_clk", "p_clk", "pixel_if0_clk", | |
593 | "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; | |
594 | phys = <&dphy0>; | |
595 | phy-names = "dphy"; | |
596 | ||
597 | ports { | |
598 | #address-cells = <1>; | |
599 | #size-cells = <0>; | |
600 | ||
601 | csi0_port0: port@0 { | |
602 | reg = <0>; | |
603 | status = "disabled"; | |
604 | }; | |
605 | ||
606 | csi0_port1: port@1 { | |
607 | reg = <1>; | |
608 | status = "disabled"; | |
609 | }; | |
610 | ||
611 | csi0_port2: port@2 { | |
612 | reg = <2>; | |
613 | status = "disabled"; | |
614 | }; | |
615 | ||
616 | csi0_port3: port@3 { | |
617 | reg = <3>; | |
618 | status = "disabled"; | |
619 | }; | |
620 | ||
621 | csi0_port4: port@4 { | |
622 | reg = <4>; | |
623 | status = "disabled"; | |
624 | }; | |
625 | }; | |
626 | }; | |
627 | }; | |
628 | ||
629 | ti_csi2rx1: ticsi2rx@4510000 { | |
630 | compatible = "ti,j721e-csi2rx-shim"; | |
631 | reg = <0x0 0x4510000 0x0 0x1000>; | |
632 | ranges; | |
633 | #address-cells = <2>; | |
634 | #size-cells = <2>; | |
635 | dmas = <&main_udmap 0x4960>; | |
636 | dma-names = "rx0"; | |
637 | power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; | |
638 | status = "disabled"; | |
639 | ||
640 | cdns_csi2rx1: csi-bridge@4514000 { | |
641 | compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; | |
642 | reg = <0x0 0x4514000 0x0 0x1000>; | |
643 | clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>, | |
644 | <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>; | |
645 | clock-names = "sys_clk", "p_clk", "pixel_if0_clk", | |
646 | "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; | |
647 | phys = <&dphy1>; | |
648 | phy-names = "dphy"; | |
649 | ||
650 | ports { | |
651 | #address-cells = <1>; | |
652 | #size-cells = <0>; | |
653 | ||
654 | csi1_port0: port@0 { | |
655 | reg = <0>; | |
656 | status = "disabled"; | |
657 | }; | |
658 | ||
659 | csi1_port1: port@1 { | |
660 | reg = <1>; | |
661 | status = "disabled"; | |
662 | }; | |
663 | ||
664 | csi1_port2: port@2 { | |
665 | reg = <2>; | |
666 | status = "disabled"; | |
667 | }; | |
668 | ||
669 | csi1_port3: port@3 { | |
670 | reg = <3>; | |
671 | status = "disabled"; | |
672 | }; | |
673 | ||
674 | csi1_port4: port@4 { | |
675 | reg = <4>; | |
676 | status = "disabled"; | |
677 | }; | |
678 | }; | |
679 | }; | |
680 | }; | |
681 | ||
682 | dphy0: phy@4580000 { | |
683 | compatible = "cdns,dphy-rx"; | |
684 | reg = <0x0 0x4580000 0x0 0x1100>; | |
685 | #phy-cells = <0>; | |
686 | power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; | |
687 | status = "disabled"; | |
688 | }; | |
689 | ||
690 | dphy1: phy@4590000 { | |
691 | compatible = "cdns,dphy-rx"; | |
692 | reg = <0x0 0x4590000 0x0 0x1100>; | |
693 | #phy-cells = <0>; | |
694 | power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; | |
695 | status = "disabled"; | |
696 | }; | |
697 | ||
afd094eb KVA |
698 | serdes_wiz0: wiz@5000000 { |
699 | compatible = "ti,j721e-wiz-16g"; | |
700 | #address-cells = <1>; | |
701 | #size-cells = <1>; | |
702 | power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; | |
5c6d0b55 | 703 | clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; |
afd094eb KVA |
704 | clock-names = "fck", "core_ref_clk", "ext_ref_clk"; |
705 | assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; | |
706 | assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; | |
707 | num-lanes = <2>; | |
708 | #reset-cells = <1>; | |
709 | ranges = <0x5000000 0x0 0x5000000 0x10000>; | |
710 | ||
711 | wiz0_pll0_refclk: pll0-refclk { | |
5c6d0b55 | 712 | clocks = <&k3_clks 292 11>, <&cmn_refclk>; |
afd094eb KVA |
713 | #clock-cells = <0>; |
714 | assigned-clocks = <&wiz0_pll0_refclk>; | |
715 | assigned-clock-parents = <&k3_clks 292 11>; | |
716 | }; | |
717 | ||
718 | wiz0_pll1_refclk: pll1-refclk { | |
5c6d0b55 | 719 | clocks = <&k3_clks 292 0>, <&cmn_refclk1>; |
afd094eb KVA |
720 | #clock-cells = <0>; |
721 | assigned-clocks = <&wiz0_pll1_refclk>; | |
722 | assigned-clock-parents = <&k3_clks 292 0>; | |
723 | }; | |
724 | ||
725 | wiz0_refclk_dig: refclk-dig { | |
5c6d0b55 | 726 | clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; |
afd094eb KVA |
727 | #clock-cells = <0>; |
728 | assigned-clocks = <&wiz0_refclk_dig>; | |
729 | assigned-clock-parents = <&k3_clks 292 11>; | |
730 | }; | |
731 | ||
732 | wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { | |
733 | clocks = <&wiz0_refclk_dig>; | |
734 | #clock-cells = <0>; | |
735 | }; | |
736 | ||
737 | wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { | |
738 | clocks = <&wiz0_pll1_refclk>; | |
739 | #clock-cells = <0>; | |
740 | }; | |
741 | ||
742 | serdes0: serdes@5000000 { | |
743 | compatible = "ti,sierra-phy-t0"; | |
744 | reg-names = "serdes"; | |
745 | reg = <0x5000000 0x10000>; | |
746 | #address-cells = <1>; | |
747 | #size-cells = <0>; | |
2427bfb3 | 748 | #clock-cells = <1>; |
afd094eb KVA |
749 | resets = <&serdes_wiz0 0>; |
750 | reset-names = "sierra_reset"; | |
2427bfb3 KVA |
751 | clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, |
752 | <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>; | |
753 | clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", | |
754 | "pll0_refclk", "pll1_refclk"; | |
afd094eb KVA |
755 | }; |
756 | }; | |
757 | ||
758 | serdes_wiz1: wiz@5010000 { | |
759 | compatible = "ti,j721e-wiz-16g"; | |
760 | #address-cells = <1>; | |
761 | #size-cells = <1>; | |
762 | power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; | |
5c6d0b55 | 763 | clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; |
afd094eb KVA |
764 | clock-names = "fck", "core_ref_clk", "ext_ref_clk"; |
765 | assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; | |
766 | assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; | |
767 | num-lanes = <2>; | |
768 | #reset-cells = <1>; | |
769 | ranges = <0x5010000 0x0 0x5010000 0x10000>; | |
770 | ||
771 | wiz1_pll0_refclk: pll0-refclk { | |
5c6d0b55 | 772 | clocks = <&k3_clks 293 13>, <&cmn_refclk>; |
afd094eb KVA |
773 | #clock-cells = <0>; |
774 | assigned-clocks = <&wiz1_pll0_refclk>; | |
775 | assigned-clock-parents = <&k3_clks 293 13>; | |
776 | }; | |
777 | ||
778 | wiz1_pll1_refclk: pll1-refclk { | |
5c6d0b55 | 779 | clocks = <&k3_clks 293 0>, <&cmn_refclk1>; |
afd094eb KVA |
780 | #clock-cells = <0>; |
781 | assigned-clocks = <&wiz1_pll1_refclk>; | |
782 | assigned-clock-parents = <&k3_clks 293 0>; | |
783 | }; | |
784 | ||
785 | wiz1_refclk_dig: refclk-dig { | |
5c6d0b55 | 786 | clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; |
afd094eb KVA |
787 | #clock-cells = <0>; |
788 | assigned-clocks = <&wiz1_refclk_dig>; | |
789 | assigned-clock-parents = <&k3_clks 293 13>; | |
790 | }; | |
791 | ||
48a498a2 | 792 | wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div { |
afd094eb KVA |
793 | clocks = <&wiz1_refclk_dig>; |
794 | #clock-cells = <0>; | |
795 | }; | |
796 | ||
797 | wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { | |
798 | clocks = <&wiz1_pll1_refclk>; | |
799 | #clock-cells = <0>; | |
800 | }; | |
801 | ||
802 | serdes1: serdes@5010000 { | |
803 | compatible = "ti,sierra-phy-t0"; | |
804 | reg-names = "serdes"; | |
805 | reg = <0x5010000 0x10000>; | |
806 | #address-cells = <1>; | |
807 | #size-cells = <0>; | |
2427bfb3 | 808 | #clock-cells = <1>; |
afd094eb KVA |
809 | resets = <&serdes_wiz1 0>; |
810 | reset-names = "sierra_reset"; | |
2427bfb3 KVA |
811 | clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, |
812 | <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; | |
813 | clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", | |
814 | "pll0_refclk", "pll1_refclk"; | |
afd094eb KVA |
815 | }; |
816 | }; | |
817 | ||
818 | serdes_wiz2: wiz@5020000 { | |
819 | compatible = "ti,j721e-wiz-16g"; | |
820 | #address-cells = <1>; | |
821 | #size-cells = <1>; | |
822 | power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; | |
5c6d0b55 | 823 | clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; |
afd094eb KVA |
824 | clock-names = "fck", "core_ref_clk", "ext_ref_clk"; |
825 | assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; | |
826 | assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; | |
827 | num-lanes = <2>; | |
828 | #reset-cells = <1>; | |
829 | ranges = <0x5020000 0x0 0x5020000 0x10000>; | |
830 | ||
831 | wiz2_pll0_refclk: pll0-refclk { | |
5c6d0b55 | 832 | clocks = <&k3_clks 294 11>, <&cmn_refclk>; |
afd094eb KVA |
833 | #clock-cells = <0>; |
834 | assigned-clocks = <&wiz2_pll0_refclk>; | |
835 | assigned-clock-parents = <&k3_clks 294 11>; | |
836 | }; | |
837 | ||
838 | wiz2_pll1_refclk: pll1-refclk { | |
5c6d0b55 | 839 | clocks = <&k3_clks 294 0>, <&cmn_refclk1>; |
afd094eb KVA |
840 | #clock-cells = <0>; |
841 | assigned-clocks = <&wiz2_pll1_refclk>; | |
842 | assigned-clock-parents = <&k3_clks 294 0>; | |
843 | }; | |
844 | ||
845 | wiz2_refclk_dig: refclk-dig { | |
5c6d0b55 | 846 | clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; |
afd094eb KVA |
847 | #clock-cells = <0>; |
848 | assigned-clocks = <&wiz2_refclk_dig>; | |
849 | assigned-clock-parents = <&k3_clks 294 11>; | |
850 | }; | |
851 | ||
852 | wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { | |
853 | clocks = <&wiz2_refclk_dig>; | |
854 | #clock-cells = <0>; | |
855 | }; | |
856 | ||
857 | wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { | |
858 | clocks = <&wiz2_pll1_refclk>; | |
859 | #clock-cells = <0>; | |
860 | }; | |
861 | ||
862 | serdes2: serdes@5020000 { | |
863 | compatible = "ti,sierra-phy-t0"; | |
864 | reg-names = "serdes"; | |
865 | reg = <0x5020000 0x10000>; | |
866 | #address-cells = <1>; | |
867 | #size-cells = <0>; | |
2427bfb3 | 868 | #clock-cells = <1>; |
afd094eb KVA |
869 | resets = <&serdes_wiz2 0>; |
870 | reset-names = "sierra_reset"; | |
2427bfb3 KVA |
871 | clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, |
872 | <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>; | |
873 | clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", | |
874 | "pll0_refclk", "pll1_refclk"; | |
afd094eb KVA |
875 | }; |
876 | }; | |
877 | ||
878 | serdes_wiz3: wiz@5030000 { | |
879 | compatible = "ti,j721e-wiz-16g"; | |
880 | #address-cells = <1>; | |
881 | #size-cells = <1>; | |
882 | power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; | |
5c6d0b55 | 883 | clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; |
afd094eb KVA |
884 | clock-names = "fck", "core_ref_clk", "ext_ref_clk"; |
885 | assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; | |
886 | assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; | |
887 | num-lanes = <2>; | |
888 | #reset-cells = <1>; | |
889 | ranges = <0x5030000 0x0 0x5030000 0x10000>; | |
890 | ||
891 | wiz3_pll0_refclk: pll0-refclk { | |
5c6d0b55 | 892 | clocks = <&k3_clks 295 9>, <&cmn_refclk>; |
afd094eb KVA |
893 | #clock-cells = <0>; |
894 | assigned-clocks = <&wiz3_pll0_refclk>; | |
895 | assigned-clock-parents = <&k3_clks 295 9>; | |
896 | }; | |
897 | ||
898 | wiz3_pll1_refclk: pll1-refclk { | |
5c6d0b55 | 899 | clocks = <&k3_clks 295 0>, <&cmn_refclk1>; |
afd094eb KVA |
900 | #clock-cells = <0>; |
901 | assigned-clocks = <&wiz3_pll1_refclk>; | |
902 | assigned-clock-parents = <&k3_clks 295 0>; | |
903 | }; | |
904 | ||
905 | wiz3_refclk_dig: refclk-dig { | |
5c6d0b55 | 906 | clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; |
afd094eb KVA |
907 | #clock-cells = <0>; |
908 | assigned-clocks = <&wiz3_refclk_dig>; | |
909 | assigned-clock-parents = <&k3_clks 295 9>; | |
910 | }; | |
911 | ||
912 | wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { | |
913 | clocks = <&wiz3_refclk_dig>; | |
914 | #clock-cells = <0>; | |
915 | }; | |
916 | ||
917 | wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { | |
918 | clocks = <&wiz3_pll1_refclk>; | |
919 | #clock-cells = <0>; | |
920 | }; | |
921 | ||
922 | serdes3: serdes@5030000 { | |
923 | compatible = "ti,sierra-phy-t0"; | |
924 | reg-names = "serdes"; | |
925 | reg = <0x5030000 0x10000>; | |
926 | #address-cells = <1>; | |
927 | #size-cells = <0>; | |
2427bfb3 | 928 | #clock-cells = <1>; |
afd094eb KVA |
929 | resets = <&serdes_wiz3 0>; |
930 | reset-names = "sierra_reset"; | |
2427bfb3 KVA |
931 | clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, |
932 | <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>; | |
933 | clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", | |
934 | "pll0_refclk", "pll1_refclk"; | |
afd094eb KVA |
935 | }; |
936 | }; | |
937 | ||
4e583388 KVA |
938 | pcie0_rc: pcie@2900000 { |
939 | compatible = "ti,j721e-pcie-host"; | |
940 | reg = <0x00 0x02900000 0x00 0x1000>, | |
941 | <0x00 0x02907000 0x00 0x400>, | |
942 | <0x00 0x0d000000 0x00 0x00800000>, | |
943 | <0x00 0x10000000 0x00 0x00001000>; | |
944 | reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; | |
945 | interrupt-names = "link_state"; | |
946 | interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; | |
947 | device_type = "pci"; | |
edb96779 | 948 | ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; |
4e583388 KVA |
949 | max-link-speed = <3>; |
950 | num-lanes = <2>; | |
951 | power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; | |
952 | clocks = <&k3_clks 239 1>; | |
953 | clock-names = "fck"; | |
954 | #address-cells = <3>; | |
955 | #size-cells = <2>; | |
5f466335 | 956 | bus-range = <0x0 0xff>; |
4e583388 KVA |
957 | vendor-id = <0x104c>; |
958 | device-id = <0xb00d>; | |
959 | msi-map = <0x0 &gic_its 0x0 0x10000>; | |
960 | dma-coherent; | |
961 | ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, | |
962 | <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; | |
963 | dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; | |
731c6ded | 964 | status = "disabled"; |
4e583388 KVA |
965 | }; |
966 | ||
4e583388 KVA |
967 | pcie1_rc: pcie@2910000 { |
968 | compatible = "ti,j721e-pcie-host"; | |
969 | reg = <0x00 0x02910000 0x00 0x1000>, | |
970 | <0x00 0x02917000 0x00 0x400>, | |
971 | <0x00 0x0d800000 0x00 0x00800000>, | |
972 | <0x00 0x18000000 0x00 0x00001000>; | |
973 | reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; | |
974 | interrupt-names = "link_state"; | |
975 | interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; | |
976 | device_type = "pci"; | |
edb96779 | 977 | ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; |
4e583388 KVA |
978 | max-link-speed = <3>; |
979 | num-lanes = <2>; | |
980 | power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; | |
981 | clocks = <&k3_clks 240 1>; | |
982 | clock-names = "fck"; | |
983 | #address-cells = <3>; | |
984 | #size-cells = <2>; | |
5f466335 | 985 | bus-range = <0x0 0xff>; |
4e583388 KVA |
986 | vendor-id = <0x104c>; |
987 | device-id = <0xb00d>; | |
988 | msi-map = <0x0 &gic_its 0x10000 0x10000>; | |
989 | dma-coherent; | |
990 | ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, | |
991 | <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; | |
992 | dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; | |
731c6ded | 993 | status = "disabled"; |
4e583388 KVA |
994 | }; |
995 | ||
4e583388 KVA |
996 | pcie2_rc: pcie@2920000 { |
997 | compatible = "ti,j721e-pcie-host"; | |
998 | reg = <0x00 0x02920000 0x00 0x1000>, | |
999 | <0x00 0x02927000 0x00 0x400>, | |
1000 | <0x00 0x0e000000 0x00 0x00800000>, | |
1001 | <0x44 0x00000000 0x00 0x00001000>; | |
1002 | reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; | |
1003 | interrupt-names = "link_state"; | |
1004 | interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; | |
1005 | device_type = "pci"; | |
edb96779 | 1006 | ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; |
4e583388 KVA |
1007 | max-link-speed = <3>; |
1008 | num-lanes = <2>; | |
1009 | power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; | |
1010 | clocks = <&k3_clks 241 1>; | |
1011 | clock-names = "fck"; | |
1012 | #address-cells = <3>; | |
1013 | #size-cells = <2>; | |
5f466335 | 1014 | bus-range = <0x0 0xff>; |
4e583388 KVA |
1015 | vendor-id = <0x104c>; |
1016 | device-id = <0xb00d>; | |
1017 | msi-map = <0x0 &gic_its 0x20000 0x10000>; | |
1018 | dma-coherent; | |
1019 | ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, | |
1020 | <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; | |
1021 | dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; | |
731c6ded | 1022 | status = "disabled"; |
4e583388 KVA |
1023 | }; |
1024 | ||
4e583388 KVA |
1025 | pcie3_rc: pcie@2930000 { |
1026 | compatible = "ti,j721e-pcie-host"; | |
1027 | reg = <0x00 0x02930000 0x00 0x1000>, | |
1028 | <0x00 0x02937000 0x00 0x400>, | |
1029 | <0x00 0x0e800000 0x00 0x00800000>, | |
1030 | <0x44 0x10000000 0x00 0x00001000>; | |
1031 | reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; | |
1032 | interrupt-names = "link_state"; | |
1033 | interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; | |
1034 | device_type = "pci"; | |
edb96779 | 1035 | ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; |
4e583388 KVA |
1036 | max-link-speed = <3>; |
1037 | num-lanes = <2>; | |
1038 | power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; | |
1039 | clocks = <&k3_clks 242 1>; | |
1040 | clock-names = "fck"; | |
1041 | #address-cells = <3>; | |
1042 | #size-cells = <2>; | |
5f466335 | 1043 | bus-range = <0x0 0xff>; |
4e583388 KVA |
1044 | vendor-id = <0x104c>; |
1045 | device-id = <0xb00d>; | |
1046 | msi-map = <0x0 &gic_its 0x30000 0x10000>; | |
1047 | dma-coherent; | |
1048 | ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, | |
1049 | <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; | |
1050 | dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; | |
731c6ded | 1051 | status = "disabled"; |
4e583388 KVA |
1052 | }; |
1053 | ||
92c996f4 TV |
1054 | serdes_wiz4: wiz@5050000 { |
1055 | compatible = "ti,am64-wiz-10g"; | |
1056 | #address-cells = <1>; | |
1057 | #size-cells = <1>; | |
1058 | power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; | |
1059 | clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>; | |
1060 | clock-names = "fck", "core_ref_clk", "ext_ref_clk"; | |
1061 | assigned-clocks = <&k3_clks 297 9>; | |
1062 | assigned-clock-parents = <&k3_clks 297 10>; | |
1063 | assigned-clock-rates = <19200000>; | |
1064 | num-lanes = <4>; | |
1065 | #reset-cells = <1>; | |
1066 | #clock-cells = <1>; | |
1067 | ranges = <0x05050000 0x00 0x05050000 0x010000>, | |
1068 | <0x0a030a00 0x00 0x0a030a00 0x40>; | |
1069 | ||
1070 | serdes4: serdes@5050000 { | |
1071 | /* | |
1072 | * Note: we also map DPTX PHY registers as the Torrent | |
1073 | * needs to manage those. | |
1074 | */ | |
1075 | compatible = "ti,j721e-serdes-10g"; | |
1076 | reg = <0x05050000 0x010000>, | |
1077 | <0x0a030a00 0x40>; /* DPTX PHY */ | |
1078 | reg-names = "torrent_phy", "dptx_phy"; | |
1079 | ||
1080 | resets = <&serdes_wiz4 0>; | |
1081 | reset-names = "torrent_reset"; | |
1082 | clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>; | |
1083 | clock-names = "refclk"; | |
1084 | assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, | |
1085 | <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, | |
1086 | <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; | |
1087 | assigned-clock-parents = <&k3_clks 297 9>, | |
1088 | <&k3_clks 297 9>, | |
1089 | <&k3_clks 297 9>; | |
1090 | #address-cells = <1>; | |
1091 | #size-cells = <0>; | |
1092 | }; | |
1093 | }; | |
1094 | ||
7f209dd1 NM |
1095 | main_timer0: timer@2400000 { |
1096 | compatible = "ti,am654-timer"; | |
1097 | reg = <0x00 0x2400000 0x00 0x400>; | |
1098 | interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; | |
1099 | clocks = <&k3_clks 49 1>; | |
1100 | clock-names = "fck"; | |
1101 | assigned-clocks = <&k3_clks 49 1>; | |
1102 | assigned-clock-parents = <&k3_clks 49 2>; | |
1103 | power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; | |
1104 | ti,timer-pwm; | |
1105 | }; | |
1106 | ||
1107 | main_timer1: timer@2410000 { | |
1108 | compatible = "ti,am654-timer"; | |
1109 | reg = <0x00 0x2410000 0x00 0x400>; | |
1110 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; | |
1111 | clocks = <&k3_clks 50 1>; | |
1112 | clock-names = "fck"; | |
1113 | assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>; | |
1114 | assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>; | |
1115 | power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; | |
1116 | ti,timer-pwm; | |
1117 | }; | |
1118 | ||
1119 | main_timer2: timer@2420000 { | |
1120 | compatible = "ti,am654-timer"; | |
1121 | reg = <0x00 0x2420000 0x00 0x400>; | |
1122 | interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; | |
1123 | clocks = <&k3_clks 51 1>; | |
1124 | clock-names = "fck"; | |
1125 | assigned-clocks = <&k3_clks 51 1>; | |
1126 | assigned-clock-parents = <&k3_clks 51 2>; | |
1127 | power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; | |
1128 | ti,timer-pwm; | |
1129 | }; | |
1130 | ||
1131 | main_timer3: timer@2430000 { | |
1132 | compatible = "ti,am654-timer"; | |
1133 | reg = <0x00 0x2430000 0x00 0x400>; | |
1134 | interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; | |
1135 | clocks = <&k3_clks 52 1>; | |
1136 | clock-names = "fck"; | |
1137 | assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>; | |
1138 | assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>; | |
1139 | power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; | |
1140 | ti,timer-pwm; | |
1141 | }; | |
1142 | ||
1143 | main_timer4: timer@2440000 { | |
1144 | compatible = "ti,am654-timer"; | |
1145 | reg = <0x00 0x2440000 0x00 0x400>; | |
1146 | interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; | |
1147 | clocks = <&k3_clks 53 1>; | |
1148 | clock-names = "fck"; | |
1149 | assigned-clocks = <&k3_clks 53 1>; | |
1150 | assigned-clock-parents = <&k3_clks 53 2>; | |
1151 | power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; | |
1152 | ti,timer-pwm; | |
1153 | }; | |
1154 | ||
1155 | main_timer5: timer@2450000 { | |
1156 | compatible = "ti,am654-timer"; | |
1157 | reg = <0x00 0x2450000 0x00 0x400>; | |
1158 | interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; | |
1159 | clocks = <&k3_clks 54 1>; | |
1160 | clock-names = "fck"; | |
1161 | assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>; | |
1162 | assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>; | |
1163 | power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; | |
1164 | ti,timer-pwm; | |
1165 | }; | |
1166 | ||
1167 | main_timer6: timer@2460000 { | |
1168 | compatible = "ti,am654-timer"; | |
1169 | reg = <0x00 0x2460000 0x00 0x400>; | |
1170 | interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; | |
1171 | clocks = <&k3_clks 55 1>; | |
1172 | clock-names = "fck"; | |
1173 | assigned-clocks = <&k3_clks 55 1>; | |
1174 | assigned-clock-parents = <&k3_clks 55 2>; | |
1175 | power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; | |
1176 | ti,timer-pwm; | |
1177 | }; | |
1178 | ||
1179 | main_timer7: timer@2470000 { | |
1180 | compatible = "ti,am654-timer"; | |
1181 | reg = <0x00 0x2470000 0x00 0x400>; | |
1182 | interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; | |
1183 | clocks = <&k3_clks 57 1>; | |
1184 | clock-names = "fck"; | |
1185 | assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>; | |
1186 | assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>; | |
1187 | power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; | |
1188 | ti,timer-pwm; | |
1189 | }; | |
1190 | ||
1191 | main_timer8: timer@2480000 { | |
1192 | compatible = "ti,am654-timer"; | |
1193 | reg = <0x00 0x2480000 0x00 0x400>; | |
1194 | interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; | |
1195 | clocks = <&k3_clks 58 1>; | |
1196 | clock-names = "fck"; | |
1197 | assigned-clocks = <&k3_clks 58 1>; | |
1198 | assigned-clock-parents = <&k3_clks 58 2>; | |
1199 | power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; | |
1200 | ti,timer-pwm; | |
1201 | }; | |
1202 | ||
1203 | main_timer9: timer@2490000 { | |
1204 | compatible = "ti,am654-timer"; | |
1205 | reg = <0x00 0x2490000 0x00 0x400>; | |
1206 | interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; | |
1207 | clocks = <&k3_clks 59 1>; | |
1208 | clock-names = "fck"; | |
1209 | assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>; | |
1210 | assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>; | |
1211 | power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; | |
1212 | ti,timer-pwm; | |
1213 | }; | |
1214 | ||
1215 | main_timer10: timer@24a0000 { | |
1216 | compatible = "ti,am654-timer"; | |
1217 | reg = <0x00 0x24a0000 0x00 0x400>; | |
1218 | interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; | |
1219 | clocks = <&k3_clks 60 1>; | |
1220 | clock-names = "fck"; | |
1221 | assigned-clocks = <&k3_clks 60 1>; | |
1222 | assigned-clock-parents = <&k3_clks 60 2>; | |
1223 | power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; | |
1224 | ti,timer-pwm; | |
1225 | }; | |
1226 | ||
1227 | main_timer11: timer@24b0000 { | |
1228 | compatible = "ti,am654-timer"; | |
1229 | reg = <0x00 0x24b0000 0x00 0x400>; | |
1230 | interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; | |
1231 | clocks = <&k3_clks 62 1>; | |
1232 | clock-names = "fck"; | |
1233 | assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>; | |
1234 | assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>; | |
1235 | power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; | |
1236 | ti,timer-pwm; | |
1237 | }; | |
1238 | ||
1239 | main_timer12: timer@24c0000 { | |
1240 | compatible = "ti,am654-timer"; | |
1241 | reg = <0x00 0x24c0000 0x00 0x400>; | |
1242 | interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; | |
1243 | clocks = <&k3_clks 63 1>; | |
1244 | clock-names = "fck"; | |
1245 | assigned-clocks = <&k3_clks 63 1>; | |
1246 | assigned-clock-parents = <&k3_clks 63 2>; | |
1247 | power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; | |
1248 | ti,timer-pwm; | |
1249 | }; | |
1250 | ||
1251 | main_timer13: timer@24d0000 { | |
1252 | compatible = "ti,am654-timer"; | |
1253 | reg = <0x00 0x24d0000 0x00 0x400>; | |
1254 | interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; | |
1255 | clocks = <&k3_clks 64 1>; | |
1256 | clock-names = "fck"; | |
1257 | assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>; | |
1258 | assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>; | |
1259 | power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; | |
1260 | ti,timer-pwm; | |
1261 | }; | |
1262 | ||
1263 | main_timer14: timer@24e0000 { | |
1264 | compatible = "ti,am654-timer"; | |
1265 | reg = <0x00 0x24e0000 0x00 0x400>; | |
1266 | interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; | |
1267 | clocks = <&k3_clks 65 1>; | |
1268 | clock-names = "fck"; | |
1269 | assigned-clocks = <&k3_clks 65 1>; | |
1270 | assigned-clock-parents = <&k3_clks 65 2>; | |
1271 | power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; | |
1272 | ti,timer-pwm; | |
1273 | }; | |
1274 | ||
1275 | main_timer15: timer@24f0000 { | |
1276 | compatible = "ti,am654-timer"; | |
1277 | reg = <0x00 0x24f0000 0x00 0x400>; | |
1278 | interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; | |
1279 | clocks = <&k3_clks 66 1>; | |
1280 | clock-names = "fck"; | |
1281 | assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>; | |
1282 | assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>; | |
1283 | power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; | |
1284 | ti,timer-pwm; | |
1285 | }; | |
1286 | ||
1287 | main_timer16: timer@2500000 { | |
1288 | compatible = "ti,am654-timer"; | |
1289 | reg = <0x00 0x2500000 0x00 0x400>; | |
1290 | interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; | |
1291 | clocks = <&k3_clks 67 1>; | |
1292 | clock-names = "fck"; | |
1293 | assigned-clocks = <&k3_clks 67 1>; | |
1294 | assigned-clock-parents = <&k3_clks 67 2>; | |
1295 | power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; | |
1296 | ti,timer-pwm; | |
1297 | }; | |
1298 | ||
1299 | main_timer17: timer@2510000 { | |
1300 | compatible = "ti,am654-timer"; | |
1301 | reg = <0x00 0x2510000 0x00 0x400>; | |
1302 | interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; | |
1303 | clocks = <&k3_clks 68 1>; | |
1304 | clock-names = "fck"; | |
1305 | assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>; | |
1306 | assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>; | |
1307 | power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; | |
1308 | ti,timer-pwm; | |
1309 | }; | |
1310 | ||
1311 | main_timer18: timer@2520000 { | |
1312 | compatible = "ti,am654-timer"; | |
1313 | reg = <0x00 0x2520000 0x00 0x400>; | |
1314 | interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; | |
1315 | clocks = <&k3_clks 69 1>; | |
1316 | clock-names = "fck"; | |
1317 | assigned-clocks = <&k3_clks 69 1>; | |
1318 | assigned-clock-parents = <&k3_clks 69 2>; | |
1319 | power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; | |
1320 | ti,timer-pwm; | |
1321 | }; | |
1322 | ||
1323 | main_timer19: timer@2530000 { | |
1324 | compatible = "ti,am654-timer"; | |
1325 | reg = <0x00 0x2530000 0x00 0x400>; | |
1326 | interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; | |
1327 | clocks = <&k3_clks 70 1>; | |
1328 | clock-names = "fck"; | |
1329 | assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>; | |
1330 | assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>; | |
1331 | power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; | |
1332 | ti,timer-pwm; | |
1333 | }; | |
1334 | ||
2d87061e NM |
1335 | main_uart0: serial@2800000 { |
1336 | compatible = "ti,j721e-uart", "ti,am654-uart"; | |
1337 | reg = <0x00 0x02800000 0x00 0x100>; | |
2d87061e NM |
1338 | interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; |
1339 | clock-frequency = <48000000>; | |
1340 | current-speed = <115200>; | |
bf146a1a | 1341 | power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; |
2d87061e NM |
1342 | clocks = <&k3_clks 146 0>; |
1343 | clock-names = "fclk"; | |
fe17e20f | 1344 | status = "disabled"; |
2d87061e NM |
1345 | }; |
1346 | ||
1347 | main_uart1: serial@2810000 { | |
1348 | compatible = "ti,j721e-uart", "ti,am654-uart"; | |
1349 | reg = <0x00 0x02810000 0x00 0x100>; | |
2d87061e NM |
1350 | interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; |
1351 | clock-frequency = <48000000>; | |
1352 | current-speed = <115200>; | |
bf146a1a | 1353 | power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; |
2d87061e NM |
1354 | clocks = <&k3_clks 278 0>; |
1355 | clock-names = "fclk"; | |
fe17e20f | 1356 | status = "disabled"; |
2d87061e NM |
1357 | }; |
1358 | ||
1359 | main_uart2: serial@2820000 { | |
1360 | compatible = "ti,j721e-uart", "ti,am654-uart"; | |
1361 | reg = <0x00 0x02820000 0x00 0x100>; | |
2d87061e NM |
1362 | interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; |
1363 | clock-frequency = <48000000>; | |
1364 | current-speed = <115200>; | |
bf146a1a | 1365 | power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; |
2d87061e NM |
1366 | clocks = <&k3_clks 279 0>; |
1367 | clock-names = "fclk"; | |
fe17e20f | 1368 | status = "disabled"; |
2d87061e NM |
1369 | }; |
1370 | ||
1371 | main_uart3: serial@2830000 { | |
1372 | compatible = "ti,j721e-uart", "ti,am654-uart"; | |
1373 | reg = <0x00 0x02830000 0x00 0x100>; | |
2d87061e NM |
1374 | interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; |
1375 | clock-frequency = <48000000>; | |
1376 | current-speed = <115200>; | |
bf146a1a | 1377 | power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; |
2d87061e NM |
1378 | clocks = <&k3_clks 280 0>; |
1379 | clock-names = "fclk"; | |
fe17e20f | 1380 | status = "disabled"; |
2d87061e NM |
1381 | }; |
1382 | ||
1383 | main_uart4: serial@2840000 { | |
1384 | compatible = "ti,j721e-uart", "ti,am654-uart"; | |
1385 | reg = <0x00 0x02840000 0x00 0x100>; | |
2d87061e NM |
1386 | interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; |
1387 | clock-frequency = <48000000>; | |
1388 | current-speed = <115200>; | |
bf146a1a | 1389 | power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; |
2d87061e NM |
1390 | clocks = <&k3_clks 281 0>; |
1391 | clock-names = "fclk"; | |
fe17e20f | 1392 | status = "disabled"; |
2d87061e NM |
1393 | }; |
1394 | ||
1395 | main_uart5: serial@2850000 { | |
1396 | compatible = "ti,j721e-uart", "ti,am654-uart"; | |
1397 | reg = <0x00 0x02850000 0x00 0x100>; | |
2d87061e NM |
1398 | interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; |
1399 | clock-frequency = <48000000>; | |
1400 | current-speed = <115200>; | |
bf146a1a | 1401 | power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; |
2d87061e NM |
1402 | clocks = <&k3_clks 282 0>; |
1403 | clock-names = "fclk"; | |
fe17e20f | 1404 | status = "disabled"; |
2d87061e NM |
1405 | }; |
1406 | ||
1407 | main_uart6: serial@2860000 { | |
1408 | compatible = "ti,j721e-uart", "ti,am654-uart"; | |
1409 | reg = <0x00 0x02860000 0x00 0x100>; | |
2d87061e NM |
1410 | interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; |
1411 | clock-frequency = <48000000>; | |
1412 | current-speed = <115200>; | |
bf146a1a | 1413 | power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; |
2d87061e NM |
1414 | clocks = <&k3_clks 283 0>; |
1415 | clock-names = "fclk"; | |
fe17e20f | 1416 | status = "disabled"; |
2d87061e NM |
1417 | }; |
1418 | ||
1419 | main_uart7: serial@2870000 { | |
1420 | compatible = "ti,j721e-uart", "ti,am654-uart"; | |
1421 | reg = <0x00 0x02870000 0x00 0x100>; | |
2d87061e NM |
1422 | interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; |
1423 | clock-frequency = <48000000>; | |
1424 | current-speed = <115200>; | |
bf146a1a | 1425 | power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; |
2d87061e NM |
1426 | clocks = <&k3_clks 284 0>; |
1427 | clock-names = "fclk"; | |
fe17e20f | 1428 | status = "disabled"; |
2d87061e NM |
1429 | }; |
1430 | ||
1431 | main_uart8: serial@2880000 { | |
1432 | compatible = "ti,j721e-uart", "ti,am654-uart"; | |
1433 | reg = <0x00 0x02880000 0x00 0x100>; | |
2d87061e NM |
1434 | interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; |
1435 | clock-frequency = <48000000>; | |
1436 | current-speed = <115200>; | |
bf146a1a | 1437 | power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; |
2d87061e NM |
1438 | clocks = <&k3_clks 285 0>; |
1439 | clock-names = "fclk"; | |
fe17e20f | 1440 | status = "disabled"; |
2d87061e NM |
1441 | }; |
1442 | ||
1443 | main_uart9: serial@2890000 { | |
1444 | compatible = "ti,j721e-uart", "ti,am654-uart"; | |
1445 | reg = <0x00 0x02890000 0x00 0x100>; | |
2d87061e NM |
1446 | interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; |
1447 | clock-frequency = <48000000>; | |
1448 | current-speed = <115200>; | |
bf146a1a | 1449 | power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; |
2d87061e NM |
1450 | clocks = <&k3_clks 286 0>; |
1451 | clock-names = "fclk"; | |
fe17e20f | 1452 | status = "disabled"; |
2d87061e | 1453 | }; |
248f3eae LV |
1454 | |
1455 | main_gpio0: gpio@600000 { | |
1456 | compatible = "ti,j721e-gpio", "ti,keystone-gpio"; | |
1457 | reg = <0x0 0x00600000 0x0 0x100>; | |
1458 | gpio-controller; | |
1459 | #gpio-cells = <2>; | |
1460 | interrupt-parent = <&main_gpio_intr>; | |
8d523f09 LV |
1461 | interrupts = <256>, <257>, <258>, <259>, |
1462 | <260>, <261>, <262>, <263>; | |
248f3eae LV |
1463 | interrupt-controller; |
1464 | #interrupt-cells = <2>; | |
1465 | ti,ngpio = <128>; | |
1466 | ti,davinci-gpio-unbanked = <0>; | |
1467 | power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; | |
1468 | clocks = <&k3_clks 105 0>; | |
1469 | clock-names = "gpio"; | |
8757108b | 1470 | status = "disabled"; |
248f3eae LV |
1471 | }; |
1472 | ||
1473 | main_gpio1: gpio@601000 { | |
1474 | compatible = "ti,j721e-gpio", "ti,keystone-gpio"; | |
1475 | reg = <0x0 0x00601000 0x0 0x100>; | |
1476 | gpio-controller; | |
1477 | #gpio-cells = <2>; | |
1478 | interrupt-parent = <&main_gpio_intr>; | |
8d523f09 | 1479 | interrupts = <288>, <289>, <290>; |
248f3eae LV |
1480 | interrupt-controller; |
1481 | #interrupt-cells = <2>; | |
1482 | ti,ngpio = <36>; | |
1483 | ti,davinci-gpio-unbanked = <0>; | |
1484 | power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; | |
1485 | clocks = <&k3_clks 106 0>; | |
1486 | clock-names = "gpio"; | |
8757108b | 1487 | status = "disabled"; |
248f3eae LV |
1488 | }; |
1489 | ||
1490 | main_gpio2: gpio@610000 { | |
1491 | compatible = "ti,j721e-gpio", "ti,keystone-gpio"; | |
1492 | reg = <0x0 0x00610000 0x0 0x100>; | |
1493 | gpio-controller; | |
1494 | #gpio-cells = <2>; | |
1495 | interrupt-parent = <&main_gpio_intr>; | |
8d523f09 LV |
1496 | interrupts = <264>, <265>, <266>, <267>, |
1497 | <268>, <269>, <270>, <271>; | |
248f3eae LV |
1498 | interrupt-controller; |
1499 | #interrupt-cells = <2>; | |
1500 | ti,ngpio = <128>; | |
1501 | ti,davinci-gpio-unbanked = <0>; | |
1502 | power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; | |
1503 | clocks = <&k3_clks 107 0>; | |
1504 | clock-names = "gpio"; | |
8757108b | 1505 | status = "disabled"; |
248f3eae LV |
1506 | }; |
1507 | ||
1508 | main_gpio3: gpio@611000 { | |
1509 | compatible = "ti,j721e-gpio", "ti,keystone-gpio"; | |
1510 | reg = <0x0 0x00611000 0x0 0x100>; | |
1511 | gpio-controller; | |
1512 | #gpio-cells = <2>; | |
1513 | interrupt-parent = <&main_gpio_intr>; | |
8d523f09 | 1514 | interrupts = <292>, <293>, <294>; |
248f3eae LV |
1515 | interrupt-controller; |
1516 | #interrupt-cells = <2>; | |
1517 | ti,ngpio = <36>; | |
1518 | ti,davinci-gpio-unbanked = <0>; | |
1519 | power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; | |
1520 | clocks = <&k3_clks 108 0>; | |
1521 | clock-names = "gpio"; | |
8757108b | 1522 | status = "disabled"; |
248f3eae LV |
1523 | }; |
1524 | ||
1525 | main_gpio4: gpio@620000 { | |
1526 | compatible = "ti,j721e-gpio", "ti,keystone-gpio"; | |
1527 | reg = <0x0 0x00620000 0x0 0x100>; | |
1528 | gpio-controller; | |
1529 | #gpio-cells = <2>; | |
1530 | interrupt-parent = <&main_gpio_intr>; | |
8d523f09 LV |
1531 | interrupts = <272>, <273>, <274>, <275>, |
1532 | <276>, <277>, <278>, <279>; | |
248f3eae LV |
1533 | interrupt-controller; |
1534 | #interrupt-cells = <2>; | |
1535 | ti,ngpio = <128>; | |
1536 | ti,davinci-gpio-unbanked = <0>; | |
1537 | power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; | |
1538 | clocks = <&k3_clks 109 0>; | |
1539 | clock-names = "gpio"; | |
8757108b | 1540 | status = "disabled"; |
248f3eae LV |
1541 | }; |
1542 | ||
1543 | main_gpio5: gpio@621000 { | |
1544 | compatible = "ti,j721e-gpio", "ti,keystone-gpio"; | |
1545 | reg = <0x0 0x00621000 0x0 0x100>; | |
1546 | gpio-controller; | |
1547 | #gpio-cells = <2>; | |
1548 | interrupt-parent = <&main_gpio_intr>; | |
8d523f09 | 1549 | interrupts = <296>, <297>, <298>; |
248f3eae LV |
1550 | interrupt-controller; |
1551 | #interrupt-cells = <2>; | |
1552 | ti,ngpio = <36>; | |
1553 | ti,davinci-gpio-unbanked = <0>; | |
1554 | power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; | |
1555 | clocks = <&k3_clks 110 0>; | |
1556 | clock-names = "gpio"; | |
8757108b | 1557 | status = "disabled"; |
248f3eae LV |
1558 | }; |
1559 | ||
1560 | main_gpio6: gpio@630000 { | |
1561 | compatible = "ti,j721e-gpio", "ti,keystone-gpio"; | |
1562 | reg = <0x0 0x00630000 0x0 0x100>; | |
1563 | gpio-controller; | |
1564 | #gpio-cells = <2>; | |
1565 | interrupt-parent = <&main_gpio_intr>; | |
8d523f09 LV |
1566 | interrupts = <280>, <281>, <282>, <283>, |
1567 | <284>, <285>, <286>, <287>; | |
248f3eae LV |
1568 | interrupt-controller; |
1569 | #interrupt-cells = <2>; | |
1570 | ti,ngpio = <128>; | |
1571 | ti,davinci-gpio-unbanked = <0>; | |
1572 | power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; | |
1573 | clocks = <&k3_clks 111 0>; | |
1574 | clock-names = "gpio"; | |
8757108b | 1575 | status = "disabled"; |
248f3eae LV |
1576 | }; |
1577 | ||
1578 | main_gpio7: gpio@631000 { | |
1579 | compatible = "ti,j721e-gpio", "ti,keystone-gpio"; | |
1580 | reg = <0x0 0x00631000 0x0 0x100>; | |
1581 | gpio-controller; | |
1582 | #gpio-cells = <2>; | |
1583 | interrupt-parent = <&main_gpio_intr>; | |
8d523f09 | 1584 | interrupts = <300>, <301>, <302>; |
248f3eae LV |
1585 | interrupt-controller; |
1586 | #interrupt-cells = <2>; | |
1587 | ti,ngpio = <36>; | |
1588 | ti,davinci-gpio-unbanked = <0>; | |
1589 | power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; | |
1590 | clocks = <&k3_clks 112 0>; | |
1591 | clock-names = "gpio"; | |
8757108b | 1592 | status = "disabled"; |
248f3eae | 1593 | }; |
e6dc10f2 | 1594 | |
0cf73209 | 1595 | main_sdhci0: mmc@4f80000 { |
e6dc10f2 FA |
1596 | compatible = "ti,j721e-sdhci-8bit"; |
1597 | reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; | |
1598 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
1599 | power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; | |
0cf73209 GS |
1600 | clock-names = "clk_ahb", "clk_xin"; |
1601 | clocks = <&k3_clks 91 0>, <&k3_clks 91 1>; | |
e6dc10f2 FA |
1602 | assigned-clocks = <&k3_clks 91 1>; |
1603 | assigned-clock-parents = <&k3_clks 91 2>; | |
1604 | bus-width = <8>; | |
eb8f6194 | 1605 | mmc-hs200-1_8v; |
e6dc10f2 | 1606 | mmc-ddr-1_8v; |
af398252 BK |
1607 | ti,otap-del-sel-legacy = <0x0>; |
1608 | ti,otap-del-sel-mmc-hs = <0x0>; | |
09ff4e90 FA |
1609 | ti,otap-del-sel-ddr52 = <0x5>; |
1610 | ti,otap-del-sel-hs200 = <0x6>; | |
1611 | ti,otap-del-sel-hs400 = <0x0>; | |
eb8f6194 AG |
1612 | ti,itap-del-sel-legacy = <0x10>; |
1613 | ti,itap-del-sel-mmc-hs = <0xa>; | |
1614 | ti,itap-del-sel-ddr52 = <0x3>; | |
e6dc10f2 | 1615 | ti,trm-icp = <0x8>; |
e6dc10f2 | 1616 | dma-coherent; |
6fbd1310 | 1617 | status = "disabled"; |
e6dc10f2 FA |
1618 | }; |
1619 | ||
0cf73209 | 1620 | main_sdhci1: mmc@4fb0000 { |
e6dc10f2 FA |
1621 | compatible = "ti,j721e-sdhci-4bit"; |
1622 | reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; | |
1623 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
1624 | power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; | |
0cf73209 GS |
1625 | clock-names = "clk_ahb", "clk_xin"; |
1626 | clocks = <&k3_clks 92 5>, <&k3_clks 92 0>; | |
e6dc10f2 FA |
1627 | assigned-clocks = <&k3_clks 92 0>; |
1628 | assigned-clock-parents = <&k3_clks 92 1>; | |
09ff4e90 | 1629 | ti,otap-del-sel-legacy = <0x0>; |
af398252 | 1630 | ti,otap-del-sel-sd-hs = <0x0>; |
09ff4e90 FA |
1631 | ti,otap-del-sel-sdr12 = <0xf>; |
1632 | ti,otap-del-sel-sdr25 = <0xf>; | |
1633 | ti,otap-del-sel-sdr50 = <0xc>; | |
1634 | ti,otap-del-sel-ddr50 = <0xc>; | |
af398252 | 1635 | ti,otap-del-sel-sdr104 = <0x5>; |
eb8f6194 AG |
1636 | ti,itap-del-sel-legacy = <0x0>; |
1637 | ti,itap-del-sel-sd-hs = <0x0>; | |
1638 | ti,itap-del-sel-sdr12 = <0x0>; | |
1639 | ti,itap-del-sel-sdr25 = <0x0>; | |
1640 | ti,itap-del-sel-ddr50 = <0x2>; | |
e6dc10f2 FA |
1641 | ti,trm-icp = <0x8>; |
1642 | ti,clkbuf-sel = <0x7>; | |
1643 | dma-coherent; | |
eb8f6194 | 1644 | sdhci-caps-mask = <0x2 0x0>; |
6fbd1310 | 1645 | status = "disabled"; |
e6dc10f2 FA |
1646 | }; |
1647 | ||
0cf73209 | 1648 | main_sdhci2: mmc@4f98000 { |
e6dc10f2 FA |
1649 | compatible = "ti,j721e-sdhci-4bit"; |
1650 | reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; | |
1651 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
1652 | power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; | |
0cf73209 GS |
1653 | clock-names = "clk_ahb", "clk_xin"; |
1654 | clocks = <&k3_clks 93 5>, <&k3_clks 93 0>; | |
e6dc10f2 FA |
1655 | assigned-clocks = <&k3_clks 93 0>; |
1656 | assigned-clock-parents = <&k3_clks 93 1>; | |
09ff4e90 | 1657 | ti,otap-del-sel-legacy = <0x0>; |
af398252 | 1658 | ti,otap-del-sel-sd-hs = <0x0>; |
09ff4e90 FA |
1659 | ti,otap-del-sel-sdr12 = <0xf>; |
1660 | ti,otap-del-sel-sdr25 = <0xf>; | |
1661 | ti,otap-del-sel-sdr50 = <0xc>; | |
1662 | ti,otap-del-sel-ddr50 = <0xc>; | |
af398252 | 1663 | ti,otap-del-sel-sdr104 = <0x5>; |
eb8f6194 AG |
1664 | ti,itap-del-sel-legacy = <0x0>; |
1665 | ti,itap-del-sel-sd-hs = <0x0>; | |
1666 | ti,itap-del-sel-sdr12 = <0x0>; | |
1667 | ti,itap-del-sel-sdr25 = <0x0>; | |
1668 | ti,itap-del-sel-ddr50 = <0x2>; | |
e6dc10f2 FA |
1669 | ti,trm-icp = <0x8>; |
1670 | ti,clkbuf-sel = <0x7>; | |
1671 | dma-coherent; | |
eb8f6194 | 1672 | sdhci-caps-mask = <0x2 0x0>; |
6fbd1310 | 1673 | status = "disabled"; |
e6dc10f2 | 1674 | }; |
451555c8 | 1675 | |
e5c956c4 | 1676 | usbss0: cdns-usb@4104000 { |
451555c8 RQ |
1677 | compatible = "ti,j721e-usb"; |
1678 | reg = <0x00 0x4104000 0x00 0x100>; | |
1679 | dma-coherent; | |
1680 | power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; | |
1681 | clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; | |
1682 | clock-names = "ref", "lpm"; | |
1683 | assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ | |
1684 | assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ | |
1685 | #address-cells = <2>; | |
1686 | #size-cells = <2>; | |
1687 | ranges; | |
1688 | ||
1689 | usb0: usb@6000000 { | |
1690 | compatible = "cdns,usb3"; | |
1691 | reg = <0x00 0x6000000 0x00 0x10000>, | |
1692 | <0x00 0x6010000 0x00 0x10000>, | |
1693 | <0x00 0x6020000 0x00 0x10000>; | |
1694 | reg-names = "otg", "xhci", "dev"; | |
1695 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ | |
1696 | <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ | |
1697 | <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ | |
1698 | interrupt-names = "host", | |
1699 | "peripheral", | |
1700 | "otg"; | |
1701 | maximum-speed = "super-speed"; | |
1702 | dr_mode = "otg"; | |
1703 | }; | |
1704 | }; | |
1705 | ||
e5c956c4 | 1706 | usbss1: cdns-usb@4114000 { |
451555c8 RQ |
1707 | compatible = "ti,j721e-usb"; |
1708 | reg = <0x00 0x4114000 0x00 0x100>; | |
1709 | dma-coherent; | |
1710 | power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; | |
1711 | clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; | |
1712 | clock-names = "ref", "lpm"; | |
1713 | assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ | |
1714 | assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ | |
1715 | #address-cells = <2>; | |
1716 | #size-cells = <2>; | |
1717 | ranges; | |
1718 | ||
1719 | usb1: usb@6400000 { | |
1720 | compatible = "cdns,usb3"; | |
1721 | reg = <0x00 0x6400000 0x00 0x10000>, | |
1722 | <0x00 0x6410000 0x00 0x10000>, | |
1723 | <0x00 0x6420000 0x00 0x10000>; | |
1724 | reg-names = "otg", "xhci", "dev"; | |
1725 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ | |
1726 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ | |
1727 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ | |
1728 | interrupt-names = "host", | |
1729 | "peripheral", | |
1730 | "otg"; | |
1731 | maximum-speed = "super-speed"; | |
1732 | dr_mode = "otg"; | |
1733 | }; | |
1734 | }; | |
cb27354b VR |
1735 | |
1736 | main_i2c0: i2c@2000000 { | |
1737 | compatible = "ti,j721e-i2c", "ti,omap4-i2c"; | |
1738 | reg = <0x0 0x2000000 0x0 0x100>; | |
1739 | interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; | |
1740 | #address-cells = <1>; | |
1741 | #size-cells = <0>; | |
1742 | clock-names = "fck"; | |
1743 | clocks = <&k3_clks 187 0>; | |
1744 | power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; | |
282c4ad3 | 1745 | status = "disabled"; |
cb27354b VR |
1746 | }; |
1747 | ||
1748 | main_i2c1: i2c@2010000 { | |
1749 | compatible = "ti,j721e-i2c", "ti,omap4-i2c"; | |
1750 | reg = <0x0 0x2010000 0x0 0x100>; | |
1751 | interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; | |
1752 | #address-cells = <1>; | |
1753 | #size-cells = <0>; | |
1754 | clock-names = "fck"; | |
1755 | clocks = <&k3_clks 188 0>; | |
1756 | power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; | |
282c4ad3 | 1757 | status = "disabled"; |
cb27354b VR |
1758 | }; |
1759 | ||
1760 | main_i2c2: i2c@2020000 { | |
1761 | compatible = "ti,j721e-i2c", "ti,omap4-i2c"; | |
1762 | reg = <0x0 0x2020000 0x0 0x100>; | |
1763 | interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; | |
1764 | #address-cells = <1>; | |
1765 | #size-cells = <0>; | |
1766 | clock-names = "fck"; | |
1767 | clocks = <&k3_clks 189 0>; | |
1768 | power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; | |
282c4ad3 | 1769 | status = "disabled"; |
cb27354b VR |
1770 | }; |
1771 | ||
1772 | main_i2c3: i2c@2030000 { | |
1773 | compatible = "ti,j721e-i2c", "ti,omap4-i2c"; | |
1774 | reg = <0x0 0x2030000 0x0 0x100>; | |
1775 | interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; | |
1776 | #address-cells = <1>; | |
1777 | #size-cells = <0>; | |
1778 | clock-names = "fck"; | |
1779 | clocks = <&k3_clks 190 0>; | |
1780 | power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; | |
282c4ad3 | 1781 | status = "disabled"; |
cb27354b VR |
1782 | }; |
1783 | ||
1784 | main_i2c4: i2c@2040000 { | |
1785 | compatible = "ti,j721e-i2c", "ti,omap4-i2c"; | |
1786 | reg = <0x0 0x2040000 0x0 0x100>; | |
1787 | interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; | |
1788 | #address-cells = <1>; | |
1789 | #size-cells = <0>; | |
1790 | clock-names = "fck"; | |
1791 | clocks = <&k3_clks 191 0>; | |
1792 | power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; | |
282c4ad3 | 1793 | status = "disabled"; |
cb27354b VR |
1794 | }; |
1795 | ||
1796 | main_i2c5: i2c@2050000 { | |
1797 | compatible = "ti,j721e-i2c", "ti,omap4-i2c"; | |
1798 | reg = <0x0 0x2050000 0x0 0x100>; | |
1799 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; | |
1800 | #address-cells = <1>; | |
1801 | #size-cells = <0>; | |
1802 | clock-names = "fck"; | |
1803 | clocks = <&k3_clks 192 0>; | |
1804 | power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; | |
282c4ad3 | 1805 | status = "disabled"; |
cb27354b VR |
1806 | }; |
1807 | ||
1808 | main_i2c6: i2c@2060000 { | |
1809 | compatible = "ti,j721e-i2c", "ti,omap4-i2c"; | |
1810 | reg = <0x0 0x2060000 0x0 0x100>; | |
1811 | interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; | |
1812 | #address-cells = <1>; | |
1813 | #size-cells = <0>; | |
1814 | clock-names = "fck"; | |
1815 | clocks = <&k3_clks 193 0>; | |
1816 | power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; | |
282c4ad3 | 1817 | status = "disabled"; |
cb27354b VR |
1818 | }; |
1819 | ||
1820 | ufs_wrapper: ufs-wrapper@4e80000 { | |
1821 | compatible = "ti,j721e-ufs"; | |
1822 | reg = <0x0 0x4e80000 0x0 0x100>; | |
1823 | power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; | |
1824 | clocks = <&k3_clks 277 1>; | |
1825 | assigned-clocks = <&k3_clks 277 1>; | |
1826 | assigned-clock-parents = <&k3_clks 277 4>; | |
1827 | ranges; | |
1828 | #address-cells = <2>; | |
1829 | #size-cells = <2>; | |
1830 | ||
1831 | ufs@4e84000 { | |
1832 | compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; | |
1833 | reg = <0x0 0x4e84000 0x0 0x10000>; | |
1834 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
1835 | freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; | |
1836 | clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; | |
1837 | clock-names = "core_clk", "phy_clk", "ref_clk"; | |
1838 | dma-coherent; | |
1839 | }; | |
1840 | }; | |
1c4d3526 | 1841 | |
92c996f4 TV |
1842 | mhdp: dp-bridge@a000000 { |
1843 | compatible = "ti,j721e-mhdp8546"; | |
1844 | /* | |
1845 | * Note: we do not map DPTX PHY area, as that is handled by | |
1846 | * the PHY driver. | |
1847 | */ | |
1848 | reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */ | |
1849 | <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */ | |
1850 | reg-names = "mhdptx", "j721e-intg"; | |
1851 | ||
1852 | clocks = <&k3_clks 151 36>; | |
1853 | ||
1854 | interrupt-parent = <&gic500>; | |
1855 | interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; | |
1856 | ||
1857 | power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; | |
1858 | ||
1859 | dp0_ports: ports { | |
1860 | #address-cells = <1>; | |
1861 | #size-cells = <0>; | |
1862 | ||
1863 | port@0 { | |
1864 | reg = <0>; | |
1865 | }; | |
1866 | ||
1867 | port@4 { | |
1868 | reg = <4>; | |
1869 | }; | |
1870 | }; | |
1871 | }; | |
1872 | ||
cfbf17e6 | 1873 | dss: dss@4a00000 { |
76921f15 TV |
1874 | compatible = "ti,j721e-dss"; |
1875 | reg = | |
1876 | <0x00 0x04a00000 0x00 0x10000>, /* common_m */ | |
1877 | <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ | |
1878 | <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ | |
1879 | <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ | |
1880 | ||
1881 | <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ | |
1882 | <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ | |
1883 | <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ | |
1884 | <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ | |
1885 | ||
1886 | <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ | |
1887 | <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ | |
1888 | <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ | |
1889 | <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ | |
1890 | ||
1891 | <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ | |
1892 | <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ | |
1893 | <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ | |
1894 | <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ | |
1895 | <0x00 0x04af0000 0x00 0x10000>; /* wb */ | |
1896 | ||
1897 | reg-names = "common_m", "common_s0", | |
1898 | "common_s1", "common_s2", | |
1899 | "vidl1", "vidl2","vid1","vid2", | |
1900 | "ovr1", "ovr2", "ovr3", "ovr4", | |
1901 | "vp1", "vp2", "vp3", "vp4", | |
1902 | "wb"; | |
1903 | ||
414772b8 KK |
1904 | clocks = <&k3_clks 152 0>, |
1905 | <&k3_clks 152 1>, | |
1906 | <&k3_clks 152 4>, | |
1907 | <&k3_clks 152 9>, | |
1908 | <&k3_clks 152 13>; | |
76921f15 TV |
1909 | clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; |
1910 | ||
1911 | power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; | |
1912 | ||
1913 | interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, | |
1914 | <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, | |
1915 | <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, | |
1916 | <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; | |
1917 | interrupt-names = "common_m", | |
1918 | "common_s0", | |
1919 | "common_s1", | |
1920 | "common_s2"; | |
1921 | ||
76921f15 | 1922 | dss_ports: ports { |
76921f15 TV |
1923 | }; |
1924 | }; | |
1925 | ||
1c4d3526 PU |
1926 | mcasp0: mcasp@2b00000 { |
1927 | compatible = "ti,am33xx-mcasp-audio"; | |
1928 | reg = <0x0 0x02b00000 0x0 0x2000>, | |
1929 | <0x0 0x02b08000 0x0 0x1000>; | |
1930 | reg-names = "mpu","dat"; | |
1931 | interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, | |
1932 | <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; | |
1933 | interrupt-names = "tx", "rx"; | |
1934 | ||
1935 | dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; | |
1936 | dma-names = "tx", "rx"; | |
1937 | ||
1938 | clocks = <&k3_clks 174 1>; | |
1939 | clock-names = "fck"; | |
1940 | power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; | |
256596ad | 1941 | status = "disabled"; |
1c4d3526 PU |
1942 | }; |
1943 | ||
1944 | mcasp1: mcasp@2b10000 { | |
1945 | compatible = "ti,am33xx-mcasp-audio"; | |
1946 | reg = <0x0 0x02b10000 0x0 0x2000>, | |
1947 | <0x0 0x02b18000 0x0 0x1000>; | |
1948 | reg-names = "mpu","dat"; | |
1949 | interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, | |
1950 | <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; | |
1951 | interrupt-names = "tx", "rx"; | |
1952 | ||
1953 | dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; | |
1954 | dma-names = "tx", "rx"; | |
1955 | ||
1956 | clocks = <&k3_clks 175 1>; | |
1957 | clock-names = "fck"; | |
1958 | power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; | |
256596ad | 1959 | status = "disabled"; |
1c4d3526 PU |
1960 | }; |
1961 | ||
1962 | mcasp2: mcasp@2b20000 { | |
1963 | compatible = "ti,am33xx-mcasp-audio"; | |
1964 | reg = <0x0 0x02b20000 0x0 0x2000>, | |
1965 | <0x0 0x02b28000 0x0 0x1000>; | |
1966 | reg-names = "mpu","dat"; | |
1967 | interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, | |
1968 | <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; | |
1969 | interrupt-names = "tx", "rx"; | |
1970 | ||
1971 | dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; | |
1972 | dma-names = "tx", "rx"; | |
1973 | ||
1974 | clocks = <&k3_clks 176 1>; | |
1975 | clock-names = "fck"; | |
1976 | power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; | |
256596ad | 1977 | status = "disabled"; |
1c4d3526 PU |
1978 | }; |
1979 | ||
1980 | mcasp3: mcasp@2b30000 { | |
1981 | compatible = "ti,am33xx-mcasp-audio"; | |
1982 | reg = <0x0 0x02b30000 0x0 0x2000>, | |
1983 | <0x0 0x02b38000 0x0 0x1000>; | |
1984 | reg-names = "mpu","dat"; | |
1985 | interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, | |
1986 | <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; | |
1987 | interrupt-names = "tx", "rx"; | |
1988 | ||
1989 | dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; | |
1990 | dma-names = "tx", "rx"; | |
1991 | ||
1992 | clocks = <&k3_clks 177 1>; | |
1993 | clock-names = "fck"; | |
1994 | power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; | |
256596ad | 1995 | status = "disabled"; |
1c4d3526 PU |
1996 | }; |
1997 | ||
1998 | mcasp4: mcasp@2b40000 { | |
1999 | compatible = "ti,am33xx-mcasp-audio"; | |
2000 | reg = <0x0 0x02b40000 0x0 0x2000>, | |
2001 | <0x0 0x02b48000 0x0 0x1000>; | |
2002 | reg-names = "mpu","dat"; | |
2003 | interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, | |
2004 | <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; | |
2005 | interrupt-names = "tx", "rx"; | |
2006 | ||
2007 | dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; | |
2008 | dma-names = "tx", "rx"; | |
2009 | ||
2010 | clocks = <&k3_clks 178 1>; | |
2011 | clock-names = "fck"; | |
2012 | power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; | |
256596ad | 2013 | status = "disabled"; |
1c4d3526 PU |
2014 | }; |
2015 | ||
2016 | mcasp5: mcasp@2b50000 { | |
2017 | compatible = "ti,am33xx-mcasp-audio"; | |
2018 | reg = <0x0 0x02b50000 0x0 0x2000>, | |
2019 | <0x0 0x02b58000 0x0 0x1000>; | |
2020 | reg-names = "mpu","dat"; | |
2021 | interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, | |
2022 | <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; | |
2023 | interrupt-names = "tx", "rx"; | |
2024 | ||
2025 | dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; | |
2026 | dma-names = "tx", "rx"; | |
2027 | ||
2028 | clocks = <&k3_clks 179 1>; | |
2029 | clock-names = "fck"; | |
2030 | power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; | |
256596ad | 2031 | status = "disabled"; |
1c4d3526 PU |
2032 | }; |
2033 | ||
2034 | mcasp6: mcasp@2b60000 { | |
2035 | compatible = "ti,am33xx-mcasp-audio"; | |
2036 | reg = <0x0 0x02b60000 0x0 0x2000>, | |
2037 | <0x0 0x02b68000 0x0 0x1000>; | |
2038 | reg-names = "mpu","dat"; | |
2039 | interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, | |
2040 | <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; | |
2041 | interrupt-names = "tx", "rx"; | |
2042 | ||
2043 | dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; | |
2044 | dma-names = "tx", "rx"; | |
2045 | ||
2046 | clocks = <&k3_clks 180 1>; | |
2047 | clock-names = "fck"; | |
2048 | power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; | |
256596ad | 2049 | status = "disabled"; |
1c4d3526 PU |
2050 | }; |
2051 | ||
2052 | mcasp7: mcasp@2b70000 { | |
2053 | compatible = "ti,am33xx-mcasp-audio"; | |
2054 | reg = <0x0 0x02b70000 0x0 0x2000>, | |
2055 | <0x0 0x02b78000 0x0 0x1000>; | |
2056 | reg-names = "mpu","dat"; | |
2057 | interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, | |
2058 | <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; | |
2059 | interrupt-names = "tx", "rx"; | |
2060 | ||
2061 | dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; | |
2062 | dma-names = "tx", "rx"; | |
2063 | ||
2064 | clocks = <&k3_clks 181 1>; | |
2065 | clock-names = "fck"; | |
2066 | power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; | |
256596ad | 2067 | status = "disabled"; |
1c4d3526 PU |
2068 | }; |
2069 | ||
2070 | mcasp8: mcasp@2b80000 { | |
2071 | compatible = "ti,am33xx-mcasp-audio"; | |
2072 | reg = <0x0 0x02b80000 0x0 0x2000>, | |
2073 | <0x0 0x02b88000 0x0 0x1000>; | |
2074 | reg-names = "mpu","dat"; | |
2075 | interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, | |
2076 | <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; | |
2077 | interrupt-names = "tx", "rx"; | |
2078 | ||
2079 | dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; | |
2080 | dma-names = "tx", "rx"; | |
2081 | ||
2082 | clocks = <&k3_clks 182 1>; | |
2083 | clock-names = "fck"; | |
2084 | power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; | |
256596ad | 2085 | status = "disabled"; |
1c4d3526 PU |
2086 | }; |
2087 | ||
2088 | mcasp9: mcasp@2b90000 { | |
2089 | compatible = "ti,am33xx-mcasp-audio"; | |
2090 | reg = <0x0 0x02b90000 0x0 0x2000>, | |
2091 | <0x0 0x02b98000 0x0 0x1000>; | |
2092 | reg-names = "mpu","dat"; | |
2093 | interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, | |
2094 | <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; | |
2095 | interrupt-names = "tx", "rx"; | |
2096 | ||
2097 | dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; | |
2098 | dma-names = "tx", "rx"; | |
2099 | ||
2100 | clocks = <&k3_clks 183 1>; | |
2101 | clock-names = "fck"; | |
2102 | power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; | |
256596ad | 2103 | status = "disabled"; |
1c4d3526 PU |
2104 | }; |
2105 | ||
2106 | mcasp10: mcasp@2ba0000 { | |
2107 | compatible = "ti,am33xx-mcasp-audio"; | |
2108 | reg = <0x0 0x02ba0000 0x0 0x2000>, | |
2109 | <0x0 0x02ba8000 0x0 0x1000>; | |
2110 | reg-names = "mpu","dat"; | |
2111 | interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, | |
2112 | <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; | |
2113 | interrupt-names = "tx", "rx"; | |
2114 | ||
2115 | dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; | |
2116 | dma-names = "tx", "rx"; | |
2117 | ||
2118 | clocks = <&k3_clks 184 1>; | |
2119 | clock-names = "fck"; | |
2120 | power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; | |
256596ad | 2121 | status = "disabled"; |
1c4d3526 PU |
2122 | }; |
2123 | ||
2124 | mcasp11: mcasp@2bb0000 { | |
2125 | compatible = "ti,am33xx-mcasp-audio"; | |
2126 | reg = <0x0 0x02bb0000 0x0 0x2000>, | |
2127 | <0x0 0x02bb8000 0x0 0x1000>; | |
2128 | reg-names = "mpu","dat"; | |
2129 | interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, | |
2130 | <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; | |
2131 | interrupt-names = "tx", "rx"; | |
2132 | ||
2133 | dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; | |
2134 | dma-names = "tx", "rx"; | |
2135 | ||
2136 | clocks = <&k3_clks 185 1>; | |
2137 | clock-names = "fck"; | |
2138 | power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; | |
256596ad | 2139 | status = "disabled"; |
1c4d3526 | 2140 | }; |
cae80943 TK |
2141 | |
2142 | watchdog0: watchdog@2200000 { | |
2143 | compatible = "ti,j7-rti-wdt"; | |
2144 | reg = <0x0 0x2200000 0x0 0x100>; | |
2145 | clocks = <&k3_clks 252 1>; | |
2146 | power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; | |
2147 | assigned-clocks = <&k3_clks 252 1>; | |
2148 | assigned-clock-parents = <&k3_clks 252 5>; | |
2149 | }; | |
2150 | ||
2151 | watchdog1: watchdog@2210000 { | |
2152 | compatible = "ti,j7-rti-wdt"; | |
2153 | reg = <0x0 0x2210000 0x0 0x100>; | |
2154 | clocks = <&k3_clks 253 1>; | |
2155 | power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; | |
2156 | assigned-clocks = <&k3_clks 253 1>; | |
2157 | assigned-clock-parents = <&k3_clks 253 5>; | |
2158 | }; | |
eb9a2a63 | 2159 | |
df445ff9 SA |
2160 | main_r5fss0: r5fss@5c00000 { |
2161 | compatible = "ti,j721e-r5fss"; | |
2162 | ti,cluster-mode = <1>; | |
2163 | #address-cells = <1>; | |
2164 | #size-cells = <1>; | |
2165 | ranges = <0x5c00000 0x00 0x5c00000 0x20000>, | |
2166 | <0x5d00000 0x00 0x5d00000 0x20000>; | |
2167 | power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; | |
2168 | ||
2169 | main_r5fss0_core0: r5f@5c00000 { | |
2170 | compatible = "ti,j721e-r5f"; | |
2171 | reg = <0x5c00000 0x00008000>, | |
2172 | <0x5c10000 0x00008000>; | |
2173 | reg-names = "atcm", "btcm"; | |
2174 | ti,sci = <&dmsc>; | |
2175 | ti,sci-dev-id = <245>; | |
2176 | ti,sci-proc-ids = <0x06 0xff>; | |
2177 | resets = <&k3_reset 245 1>; | |
2178 | firmware-name = "j7-main-r5f0_0-fw"; | |
2179 | ti,atcm-enable = <1>; | |
2180 | ti,btcm-enable = <1>; | |
2181 | ti,loczrama = <1>; | |
2182 | }; | |
2183 | ||
2184 | main_r5fss0_core1: r5f@5d00000 { | |
2185 | compatible = "ti,j721e-r5f"; | |
2186 | reg = <0x5d00000 0x00008000>, | |
2187 | <0x5d10000 0x00008000>; | |
2188 | reg-names = "atcm", "btcm"; | |
2189 | ti,sci = <&dmsc>; | |
2190 | ti,sci-dev-id = <246>; | |
2191 | ti,sci-proc-ids = <0x07 0xff>; | |
2192 | resets = <&k3_reset 246 1>; | |
2193 | firmware-name = "j7-main-r5f0_1-fw"; | |
2194 | ti,atcm-enable = <1>; | |
2195 | ti,btcm-enable = <1>; | |
2196 | ti,loczrama = <1>; | |
2197 | }; | |
2198 | }; | |
2199 | ||
2200 | main_r5fss1: r5fss@5e00000 { | |
2201 | compatible = "ti,j721e-r5fss"; | |
2202 | ti,cluster-mode = <1>; | |
2203 | #address-cells = <1>; | |
2204 | #size-cells = <1>; | |
2205 | ranges = <0x5e00000 0x00 0x5e00000 0x20000>, | |
2206 | <0x5f00000 0x00 0x5f00000 0x20000>; | |
2207 | power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; | |
2208 | ||
2209 | main_r5fss1_core0: r5f@5e00000 { | |
2210 | compatible = "ti,j721e-r5f"; | |
2211 | reg = <0x5e00000 0x00008000>, | |
2212 | <0x5e10000 0x00008000>; | |
2213 | reg-names = "atcm", "btcm"; | |
2214 | ti,sci = <&dmsc>; | |
2215 | ti,sci-dev-id = <247>; | |
2216 | ti,sci-proc-ids = <0x08 0xff>; | |
2217 | resets = <&k3_reset 247 1>; | |
2218 | firmware-name = "j7-main-r5f1_0-fw"; | |
2219 | ti,atcm-enable = <1>; | |
2220 | ti,btcm-enable = <1>; | |
2221 | ti,loczrama = <1>; | |
2222 | }; | |
2223 | ||
2224 | main_r5fss1_core1: r5f@5f00000 { | |
2225 | compatible = "ti,j721e-r5f"; | |
2226 | reg = <0x5f00000 0x00008000>, | |
2227 | <0x5f10000 0x00008000>; | |
2228 | reg-names = "atcm", "btcm"; | |
2229 | ti,sci = <&dmsc>; | |
2230 | ti,sci-dev-id = <248>; | |
2231 | ti,sci-proc-ids = <0x09 0xff>; | |
2232 | resets = <&k3_reset 248 1>; | |
2233 | firmware-name = "j7-main-r5f1_1-fw"; | |
2234 | ti,atcm-enable = <1>; | |
2235 | ti,btcm-enable = <1>; | |
2236 | ti,loczrama = <1>; | |
2237 | }; | |
2238 | }; | |
2239 | ||
eb9a2a63 SA |
2240 | c66_0: dsp@4d80800000 { |
2241 | compatible = "ti,j721e-c66-dsp"; | |
2242 | reg = <0x4d 0x80800000 0x00 0x00048000>, | |
2243 | <0x4d 0x80e00000 0x00 0x00008000>, | |
2244 | <0x4d 0x80f00000 0x00 0x00008000>; | |
2245 | reg-names = "l2sram", "l1pram", "l1dram"; | |
2246 | ti,sci = <&dmsc>; | |
2247 | ti,sci-dev-id = <142>; | |
2248 | ti,sci-proc-ids = <0x03 0xff>; | |
2249 | resets = <&k3_reset 142 1>; | |
2250 | firmware-name = "j7-c66_0-fw"; | |
00ae4c39 | 2251 | status = "disabled"; |
eb9a2a63 SA |
2252 | }; |
2253 | ||
2254 | c66_1: dsp@4d81800000 { | |
2255 | compatible = "ti,j721e-c66-dsp"; | |
2256 | reg = <0x4d 0x81800000 0x00 0x00048000>, | |
2257 | <0x4d 0x81e00000 0x00 0x00008000>, | |
2258 | <0x4d 0x81f00000 0x00 0x00008000>; | |
2259 | reg-names = "l2sram", "l1pram", "l1dram"; | |
2260 | ti,sci = <&dmsc>; | |
2261 | ti,sci-dev-id = <143>; | |
2262 | ti,sci-proc-ids = <0x04 0xff>; | |
2263 | resets = <&k3_reset 143 1>; | |
2264 | firmware-name = "j7-c66_1-fw"; | |
00ae4c39 | 2265 | status = "disabled"; |
eb9a2a63 | 2266 | }; |
804a4cc7 SA |
2267 | |
2268 | c71_0: dsp@64800000 { | |
2269 | compatible = "ti,j721e-c71-dsp"; | |
2270 | reg = <0x00 0x64800000 0x00 0x00080000>, | |
2271 | <0x00 0x64e00000 0x00 0x0000c000>; | |
2272 | reg-names = "l2sram", "l1dram"; | |
2273 | ti,sci = <&dmsc>; | |
2274 | ti,sci-dev-id = <15>; | |
2275 | ti,sci-proc-ids = <0x30 0xff>; | |
2276 | resets = <&k3_reset 15 1>; | |
2277 | firmware-name = "j7-c71_0-fw"; | |
35dba715 | 2278 | status = "disabled"; |
804a4cc7 | 2279 | }; |
4c842af3 SA |
2280 | |
2281 | icssg0: icssg@b000000 { | |
2282 | compatible = "ti,j721e-icssg"; | |
2283 | reg = <0x00 0xb000000 0x00 0x80000>; | |
2284 | power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; | |
2285 | #address-cells = <1>; | |
2286 | #size-cells = <1>; | |
2287 | ranges = <0x0 0x00 0x0b000000 0x100000>; | |
2288 | ||
2289 | icssg0_mem: memories@0 { | |
2290 | reg = <0x0 0x2000>, | |
2291 | <0x2000 0x2000>, | |
2292 | <0x10000 0x10000>; | |
2293 | reg-names = "dram0", "dram1", | |
2294 | "shrdram2"; | |
2295 | }; | |
2296 | ||
2297 | icssg0_cfg: cfg@26000 { | |
2298 | compatible = "ti,pruss-cfg", "syscon"; | |
2299 | reg = <0x26000 0x200>; | |
2300 | #address-cells = <1>; | |
2301 | #size-cells = <1>; | |
2302 | ranges = <0x0 0x26000 0x2000>; | |
2303 | ||
2304 | clocks { | |
2305 | #address-cells = <1>; | |
2306 | #size-cells = <0>; | |
2307 | ||
2308 | icssg0_coreclk_mux: coreclk-mux@3c { | |
2309 | reg = <0x3c>; | |
2310 | #clock-cells = <0>; | |
2311 | clocks = <&k3_clks 119 24>, /* icssg0_core_clk */ | |
2312 | <&k3_clks 119 1>; /* icssg0_iclk */ | |
2313 | assigned-clocks = <&icssg0_coreclk_mux>; | |
2314 | assigned-clock-parents = <&k3_clks 119 1>; | |
2315 | }; | |
2316 | ||
2317 | icssg0_iepclk_mux: iepclk-mux@30 { | |
2318 | reg = <0x30>; | |
2319 | #clock-cells = <0>; | |
2320 | clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */ | |
2321 | <&icssg0_coreclk_mux>; /* core_clk */ | |
2322 | assigned-clocks = <&icssg0_iepclk_mux>; | |
2323 | assigned-clock-parents = <&icssg0_coreclk_mux>; | |
2324 | }; | |
2325 | }; | |
2326 | }; | |
2327 | ||
2328 | icssg0_mii_rt: mii-rt@32000 { | |
2329 | compatible = "ti,pruss-mii", "syscon"; | |
2330 | reg = <0x32000 0x100>; | |
2331 | }; | |
2332 | ||
2333 | icssg0_mii_g_rt: mii-g-rt@33000 { | |
2334 | compatible = "ti,pruss-mii-g", "syscon"; | |
2335 | reg = <0x33000 0x1000>; | |
2336 | }; | |
2337 | ||
2338 | icssg0_intc: interrupt-controller@20000 { | |
2339 | compatible = "ti,icssg-intc"; | |
2340 | reg = <0x20000 0x2000>; | |
2341 | interrupt-controller; | |
2342 | #interrupt-cells = <3>; | |
2343 | interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, | |
2344 | <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, | |
2345 | <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, | |
2346 | <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, | |
2347 | <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, | |
2348 | <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, | |
2349 | <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, | |
2350 | <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; | |
2351 | interrupt-names = "host_intr0", "host_intr1", | |
2352 | "host_intr2", "host_intr3", | |
2353 | "host_intr4", "host_intr5", | |
2354 | "host_intr6", "host_intr7"; | |
2355 | }; | |
2356 | ||
2357 | pru0_0: pru@34000 { | |
2358 | compatible = "ti,j721e-pru"; | |
2359 | reg = <0x34000 0x3000>, | |
2360 | <0x22000 0x100>, | |
2361 | <0x22400 0x100>; | |
2362 | reg-names = "iram", "control", "debug"; | |
2363 | firmware-name = "j7-pru0_0-fw"; | |
2364 | }; | |
2365 | ||
2366 | rtu0_0: rtu@4000 { | |
2367 | compatible = "ti,j721e-rtu"; | |
2368 | reg = <0x4000 0x2000>, | |
2369 | <0x23000 0x100>, | |
2370 | <0x23400 0x100>; | |
2371 | reg-names = "iram", "control", "debug"; | |
2372 | firmware-name = "j7-rtu0_0-fw"; | |
2373 | }; | |
2374 | ||
2375 | tx_pru0_0: txpru@a000 { | |
2376 | compatible = "ti,j721e-tx-pru"; | |
2377 | reg = <0xa000 0x1800>, | |
2378 | <0x25000 0x100>, | |
2379 | <0x25400 0x100>; | |
2380 | reg-names = "iram", "control", "debug"; | |
2381 | firmware-name = "j7-txpru0_0-fw"; | |
2382 | }; | |
2383 | ||
2384 | pru0_1: pru@38000 { | |
2385 | compatible = "ti,j721e-pru"; | |
2386 | reg = <0x38000 0x3000>, | |
2387 | <0x24000 0x100>, | |
2388 | <0x24400 0x100>; | |
2389 | reg-names = "iram", "control", "debug"; | |
2390 | firmware-name = "j7-pru0_1-fw"; | |
2391 | }; | |
2392 | ||
2393 | rtu0_1: rtu@6000 { | |
2394 | compatible = "ti,j721e-rtu"; | |
2395 | reg = <0x6000 0x2000>, | |
2396 | <0x23800 0x100>, | |
2397 | <0x23c00 0x100>; | |
2398 | reg-names = "iram", "control", "debug"; | |
2399 | firmware-name = "j7-rtu0_1-fw"; | |
2400 | }; | |
2401 | ||
2402 | tx_pru0_1: txpru@c000 { | |
2403 | compatible = "ti,j721e-tx-pru"; | |
2404 | reg = <0xc000 0x1800>, | |
2405 | <0x25800 0x100>, | |
2406 | <0x25c00 0x100>; | |
2407 | reg-names = "iram", "control", "debug"; | |
2408 | firmware-name = "j7-txpru0_1-fw"; | |
2409 | }; | |
7ce11d47 SA |
2410 | |
2411 | icssg0_mdio: mdio@32400 { | |
2412 | compatible = "ti,davinci_mdio"; | |
2413 | reg = <0x32400 0x100>; | |
2414 | clocks = <&k3_clks 119 1>; | |
2415 | clock-names = "fck"; | |
2416 | #address-cells = <1>; | |
2417 | #size-cells = <0>; | |
2418 | bus_freq = <1000000>; | |
b0efb45d | 2419 | status = "disabled"; |
7ce11d47 | 2420 | }; |
4c842af3 SA |
2421 | }; |
2422 | ||
2423 | icssg1: icssg@b100000 { | |
2424 | compatible = "ti,j721e-icssg"; | |
2425 | reg = <0x00 0xb100000 0x00 0x80000>; | |
2426 | power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; | |
2427 | #address-cells = <1>; | |
2428 | #size-cells = <1>; | |
2429 | ranges = <0x0 0x00 0x0b100000 0x100000>; | |
2430 | ||
2431 | icssg1_mem: memories@b100000 { | |
2432 | reg = <0x0 0x2000>, | |
2433 | <0x2000 0x2000>, | |
2434 | <0x10000 0x10000>; | |
2435 | reg-names = "dram0", "dram1", | |
2436 | "shrdram2"; | |
2437 | }; | |
2438 | ||
2439 | icssg1_cfg: cfg@26000 { | |
2440 | compatible = "ti,pruss-cfg", "syscon"; | |
2441 | reg = <0x26000 0x200>; | |
2442 | #address-cells = <1>; | |
2443 | #size-cells = <1>; | |
2444 | ranges = <0x0 0x26000 0x2000>; | |
2445 | ||
2446 | clocks { | |
2447 | #address-cells = <1>; | |
2448 | #size-cells = <0>; | |
2449 | ||
2450 | icssg1_coreclk_mux: coreclk-mux@3c { | |
2451 | reg = <0x3c>; | |
2452 | #clock-cells = <0>; | |
2453 | clocks = <&k3_clks 120 54>, /* icssg1_core_clk */ | |
2454 | <&k3_clks 120 4>; /* icssg1_iclk */ | |
2455 | assigned-clocks = <&icssg1_coreclk_mux>; | |
2456 | assigned-clock-parents = <&k3_clks 120 4>; | |
2457 | }; | |
2458 | ||
2459 | icssg1_iepclk_mux: iepclk-mux@30 { | |
2460 | reg = <0x30>; | |
2461 | #clock-cells = <0>; | |
2462 | clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */ | |
2463 | <&icssg1_coreclk_mux>; /* core_clk */ | |
2464 | assigned-clocks = <&icssg1_iepclk_mux>; | |
2465 | assigned-clock-parents = <&icssg1_coreclk_mux>; | |
2466 | }; | |
2467 | }; | |
2468 | }; | |
2469 | ||
2470 | icssg1_mii_rt: mii-rt@32000 { | |
2471 | compatible = "ti,pruss-mii", "syscon"; | |
2472 | reg = <0x32000 0x100>; | |
2473 | }; | |
2474 | ||
2475 | icssg1_mii_g_rt: mii-g-rt@33000 { | |
2476 | compatible = "ti,pruss-mii-g", "syscon"; | |
2477 | reg = <0x33000 0x1000>; | |
2478 | }; | |
2479 | ||
2480 | icssg1_intc: interrupt-controller@20000 { | |
2481 | compatible = "ti,icssg-intc"; | |
2482 | reg = <0x20000 0x2000>; | |
2483 | interrupt-controller; | |
2484 | #interrupt-cells = <3>; | |
2485 | interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, | |
2486 | <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, | |
2487 | <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, | |
2488 | <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, | |
2489 | <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, | |
2490 | <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, | |
2491 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, | |
2492 | <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; | |
2493 | interrupt-names = "host_intr0", "host_intr1", | |
2494 | "host_intr2", "host_intr3", | |
2495 | "host_intr4", "host_intr5", | |
2496 | "host_intr6", "host_intr7"; | |
2497 | }; | |
2498 | ||
2499 | pru1_0: pru@34000 { | |
2500 | compatible = "ti,j721e-pru"; | |
2501 | reg = <0x34000 0x4000>, | |
2502 | <0x22000 0x100>, | |
2503 | <0x22400 0x100>; | |
2504 | reg-names = "iram", "control", "debug"; | |
2505 | firmware-name = "j7-pru1_0-fw"; | |
2506 | }; | |
2507 | ||
2508 | rtu1_0: rtu@4000 { | |
2509 | compatible = "ti,j721e-rtu"; | |
2510 | reg = <0x4000 0x2000>, | |
2511 | <0x23000 0x100>, | |
2512 | <0x23400 0x100>; | |
2513 | reg-names = "iram", "control", "debug"; | |
2514 | firmware-name = "j7-rtu1_0-fw"; | |
2515 | }; | |
2516 | ||
2517 | tx_pru1_0: txpru@a000 { | |
2518 | compatible = "ti,j721e-tx-pru"; | |
2519 | reg = <0xa000 0x1800>, | |
2520 | <0x25000 0x100>, | |
2521 | <0x25400 0x100>; | |
2522 | reg-names = "iram", "control", "debug"; | |
2523 | firmware-name = "j7-txpru1_0-fw"; | |
2524 | }; | |
2525 | ||
2526 | pru1_1: pru@38000 { | |
2527 | compatible = "ti,j721e-pru"; | |
2528 | reg = <0x38000 0x4000>, | |
2529 | <0x24000 0x100>, | |
2530 | <0x24400 0x100>; | |
2531 | reg-names = "iram", "control", "debug"; | |
2532 | firmware-name = "j7-pru1_1-fw"; | |
2533 | }; | |
2534 | ||
2535 | rtu1_1: rtu@6000 { | |
2536 | compatible = "ti,j721e-rtu"; | |
2537 | reg = <0x6000 0x2000>, | |
2538 | <0x23800 0x100>, | |
2539 | <0x23c00 0x100>; | |
2540 | reg-names = "iram", "control", "debug"; | |
2541 | firmware-name = "j7-rtu1_1-fw"; | |
2542 | }; | |
2543 | ||
2544 | tx_pru1_1: txpru@c000 { | |
2545 | compatible = "ti,j721e-tx-pru"; | |
2546 | reg = <0xc000 0x1800>, | |
2547 | <0x25800 0x100>, | |
2548 | <0x25c00 0x100>; | |
2549 | reg-names = "iram", "control", "debug"; | |
2550 | firmware-name = "j7-txpru1_1-fw"; | |
2551 | }; | |
7ce11d47 SA |
2552 | |
2553 | icssg1_mdio: mdio@32400 { | |
2554 | compatible = "ti,davinci_mdio"; | |
2555 | reg = <0x32400 0x100>; | |
2556 | clocks = <&k3_clks 120 4>; | |
2557 | clock-names = "fck"; | |
2558 | #address-cells = <1>; | |
2559 | #size-cells = <0>; | |
2560 | bus_freq = <1000000>; | |
b0efb45d | 2561 | status = "disabled"; |
7ce11d47 | 2562 | }; |
4c842af3 | 2563 | }; |
4688a4fc FA |
2564 | |
2565 | main_mcan0: can@2701000 { | |
2566 | compatible = "bosch,m_can"; | |
2567 | reg = <0x00 0x02701000 0x00 0x200>, | |
2568 | <0x00 0x02708000 0x00 0x8000>; | |
2569 | reg-names = "m_can", "message_ram"; | |
2570 | power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; | |
2571 | clocks = <&k3_clks 156 0>, <&k3_clks 156 1>; | |
2572 | clock-names = "hclk", "cclk"; | |
2573 | interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, | |
2574 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; | |
2575 | interrupt-names = "int0", "int1"; | |
2576 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | |
39e7758b | 2577 | status = "disabled"; |
4688a4fc FA |
2578 | }; |
2579 | ||
2580 | main_mcan1: can@2711000 { | |
2581 | compatible = "bosch,m_can"; | |
2582 | reg = <0x00 0x02711000 0x00 0x200>, | |
2583 | <0x00 0x02718000 0x00 0x8000>; | |
2584 | reg-names = "m_can", "message_ram"; | |
2585 | power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; | |
2586 | clocks = <&k3_clks 158 0>, <&k3_clks 158 1>; | |
2587 | clock-names = "hclk", "cclk"; | |
2588 | interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, | |
2589 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; | |
2590 | interrupt-names = "int0", "int1"; | |
2591 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | |
39e7758b | 2592 | status = "disabled"; |
4688a4fc FA |
2593 | }; |
2594 | ||
2595 | main_mcan2: can@2721000 { | |
2596 | compatible = "bosch,m_can"; | |
2597 | reg = <0x00 0x02721000 0x00 0x200>, | |
2598 | <0x00 0x02728000 0x00 0x8000>; | |
2599 | reg-names = "m_can", "message_ram"; | |
2600 | power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; | |
2601 | clocks = <&k3_clks 160 0>, <&k3_clks 160 1>; | |
2602 | clock-names = "hclk", "cclk"; | |
2603 | interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, | |
2604 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; | |
2605 | interrupt-names = "int0", "int1"; | |
2606 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | |
39e7758b | 2607 | status = "disabled"; |
4688a4fc FA |
2608 | }; |
2609 | ||
2610 | main_mcan3: can@2731000 { | |
2611 | compatible = "bosch,m_can"; | |
2612 | reg = <0x00 0x02731000 0x00 0x200>, | |
2613 | <0x00 0x02738000 0x00 0x8000>; | |
2614 | reg-names = "m_can", "message_ram"; | |
2615 | power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; | |
2616 | clocks = <&k3_clks 161 0>, <&k3_clks 161 1>; | |
2617 | clock-names = "hclk", "cclk"; | |
2618 | interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, | |
2619 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; | |
2620 | interrupt-names = "int0", "int1"; | |
2621 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | |
39e7758b | 2622 | status = "disabled"; |
4688a4fc FA |
2623 | }; |
2624 | ||
2625 | main_mcan4: can@2741000 { | |
2626 | compatible = "bosch,m_can"; | |
2627 | reg = <0x00 0x02741000 0x00 0x200>, | |
2628 | <0x00 0x02748000 0x00 0x8000>; | |
2629 | reg-names = "m_can", "message_ram"; | |
2630 | power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; | |
2631 | clocks = <&k3_clks 162 0>, <&k3_clks 162 1>; | |
2632 | clock-names = "hclk", "cclk"; | |
2633 | interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, | |
2634 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; | |
2635 | interrupt-names = "int0", "int1"; | |
2636 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | |
39e7758b | 2637 | status = "disabled"; |
4688a4fc FA |
2638 | }; |
2639 | ||
2640 | main_mcan5: can@2751000 { | |
2641 | compatible = "bosch,m_can"; | |
2642 | reg = <0x00 0x02751000 0x00 0x200>, | |
2643 | <0x00 0x02758000 0x00 0x8000>; | |
2644 | reg-names = "m_can", "message_ram"; | |
2645 | power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; | |
2646 | clocks = <&k3_clks 163 0>, <&k3_clks 163 1>; | |
2647 | clock-names = "hclk", "cclk"; | |
2648 | interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, | |
2649 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; | |
2650 | interrupt-names = "int0", "int1"; | |
2651 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | |
39e7758b | 2652 | status = "disabled"; |
4688a4fc FA |
2653 | }; |
2654 | ||
2655 | main_mcan6: can@2761000 { | |
2656 | compatible = "bosch,m_can"; | |
2657 | reg = <0x00 0x02761000 0x00 0x200>, | |
2658 | <0x00 0x02768000 0x00 0x8000>; | |
2659 | reg-names = "m_can", "message_ram"; | |
2660 | power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; | |
2661 | clocks = <&k3_clks 164 0>, <&k3_clks 164 1>; | |
2662 | clock-names = "hclk", "cclk"; | |
2663 | interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, | |
2664 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; | |
2665 | interrupt-names = "int0", "int1"; | |
2666 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | |
39e7758b | 2667 | status = "disabled"; |
4688a4fc FA |
2668 | }; |
2669 | ||
2670 | main_mcan7: can@2771000 { | |
2671 | compatible = "bosch,m_can"; | |
2672 | reg = <0x00 0x02771000 0x00 0x200>, | |
2673 | <0x00 0x02778000 0x00 0x8000>; | |
2674 | reg-names = "m_can", "message_ram"; | |
2675 | power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; | |
2676 | clocks = <&k3_clks 165 0>, <&k3_clks 165 1>; | |
2677 | clock-names = "hclk", "cclk"; | |
2678 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, | |
2679 | <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; | |
2680 | interrupt-names = "int0", "int1"; | |
2681 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | |
39e7758b | 2682 | status = "disabled"; |
4688a4fc FA |
2683 | }; |
2684 | ||
2685 | main_mcan8: can@2781000 { | |
2686 | compatible = "bosch,m_can"; | |
2687 | reg = <0x00 0x02781000 0x00 0x200>, | |
2688 | <0x00 0x02788000 0x00 0x8000>; | |
2689 | reg-names = "m_can", "message_ram"; | |
2690 | power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; | |
2691 | clocks = <&k3_clks 166 0>, <&k3_clks 166 1>; | |
2692 | clock-names = "hclk", "cclk"; | |
2693 | interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, | |
2694 | <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; | |
2695 | interrupt-names = "int0", "int1"; | |
2696 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | |
39e7758b | 2697 | status = "disabled"; |
4688a4fc FA |
2698 | }; |
2699 | ||
2700 | main_mcan9: can@2791000 { | |
2701 | compatible = "bosch,m_can"; | |
2702 | reg = <0x00 0x02791000 0x00 0x200>, | |
2703 | <0x00 0x02798000 0x00 0x8000>; | |
2704 | reg-names = "m_can", "message_ram"; | |
2705 | power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; | |
2706 | clocks = <&k3_clks 167 0>, <&k3_clks 167 1>; | |
2707 | clock-names = "hclk", "cclk"; | |
2708 | interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, | |
2709 | <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; | |
2710 | interrupt-names = "int0", "int1"; | |
2711 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | |
39e7758b | 2712 | status = "disabled"; |
4688a4fc FA |
2713 | }; |
2714 | ||
2715 | main_mcan10: can@27a1000 { | |
2716 | compatible = "bosch,m_can"; | |
2717 | reg = <0x00 0x027a1000 0x00 0x200>, | |
2718 | <0x00 0x027a8000 0x00 0x8000>; | |
2719 | reg-names = "m_can", "message_ram"; | |
2720 | power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; | |
2721 | clocks = <&k3_clks 168 0>, <&k3_clks 168 1>; | |
2722 | clock-names = "hclk", "cclk"; | |
2723 | interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, | |
2724 | <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; | |
2725 | interrupt-names = "int0", "int1"; | |
2726 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | |
39e7758b | 2727 | status = "disabled"; |
4688a4fc FA |
2728 | }; |
2729 | ||
2730 | main_mcan11: can@27b1000 { | |
2731 | compatible = "bosch,m_can"; | |
2732 | reg = <0x00 0x027b1000 0x00 0x200>, | |
2733 | <0x00 0x027b8000 0x00 0x8000>; | |
2734 | reg-names = "m_can", "message_ram"; | |
2735 | power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; | |
2736 | clocks = <&k3_clks 169 0>, <&k3_clks 169 1>; | |
2737 | clock-names = "hclk", "cclk"; | |
2738 | interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, | |
2739 | <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; | |
2740 | interrupt-names = "int0", "int1"; | |
2741 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | |
39e7758b | 2742 | status = "disabled"; |
4688a4fc FA |
2743 | }; |
2744 | ||
2745 | main_mcan12: can@27c1000 { | |
2746 | compatible = "bosch,m_can"; | |
2747 | reg = <0x00 0x027c1000 0x00 0x200>, | |
2748 | <0x00 0x027c8000 0x00 0x8000>; | |
2749 | reg-names = "m_can", "message_ram"; | |
2750 | power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; | |
2751 | clocks = <&k3_clks 170 0>, <&k3_clks 170 1>; | |
2752 | clock-names = "hclk", "cclk"; | |
2753 | interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, | |
2754 | <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; | |
2755 | interrupt-names = "int0", "int1"; | |
2756 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | |
39e7758b | 2757 | status = "disabled"; |
4688a4fc FA |
2758 | }; |
2759 | ||
2760 | main_mcan13: can@27d1000 { | |
2761 | compatible = "bosch,m_can"; | |
2762 | reg = <0x00 0x027d1000 0x00 0x200>, | |
2763 | <0x00 0x027d8000 0x00 0x8000>; | |
2764 | reg-names = "m_can", "message_ram"; | |
2765 | power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; | |
2766 | clocks = <&k3_clks 171 0>, <&k3_clks 171 1>; | |
2767 | clock-names = "hclk", "cclk"; | |
2768 | interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, | |
2769 | <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; | |
2770 | interrupt-names = "int0", "int1"; | |
2771 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | |
39e7758b | 2772 | status = "disabled"; |
4688a4fc | 2773 | }; |
76aa309f VA |
2774 | |
2775 | main_spi0: spi@2100000 { | |
2776 | compatible = "ti,am654-mcspi","ti,omap4-mcspi"; | |
2777 | reg = <0x00 0x02100000 0x00 0x400>; | |
2778 | interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; | |
2779 | #address-cells = <1>; | |
2780 | #size-cells = <0>; | |
2781 | power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; | |
2782 | clocks = <&k3_clks 266 1>; | |
2783 | status = "disabled"; | |
2784 | }; | |
2785 | ||
2786 | main_spi1: spi@2110000 { | |
2787 | compatible = "ti,am654-mcspi","ti,omap4-mcspi"; | |
2788 | reg = <0x00 0x02110000 0x00 0x400>; | |
2789 | interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; | |
2790 | #address-cells = <1>; | |
2791 | #size-cells = <0>; | |
2792 | power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; | |
2793 | clocks = <&k3_clks 267 1>; | |
2794 | status = "disabled"; | |
2795 | }; | |
2796 | ||
2797 | main_spi2: spi@2120000 { | |
2798 | compatible = "ti,am654-mcspi","ti,omap4-mcspi"; | |
2799 | reg = <0x00 0x02120000 0x00 0x400>; | |
2800 | interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; | |
2801 | #address-cells = <1>; | |
2802 | #size-cells = <0>; | |
2803 | power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; | |
2804 | clocks = <&k3_clks 268 1>; | |
2805 | status = "disabled"; | |
2806 | }; | |
2807 | ||
2808 | main_spi3: spi@2130000 { | |
2809 | compatible = "ti,am654-mcspi","ti,omap4-mcspi"; | |
2810 | reg = <0x00 0x02130000 0x00 0x400>; | |
2811 | interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; | |
2812 | #address-cells = <1>; | |
2813 | #size-cells = <0>; | |
2814 | power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; | |
2815 | clocks = <&k3_clks 269 1>; | |
2816 | status = "disabled"; | |
2817 | }; | |
2818 | ||
2819 | main_spi4: spi@2140000 { | |
2820 | compatible = "ti,am654-mcspi","ti,omap4-mcspi"; | |
2821 | reg = <0x00 0x02140000 0x00 0x400>; | |
2822 | interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; | |
2823 | #address-cells = <1>; | |
2824 | #size-cells = <0>; | |
2825 | power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; | |
2826 | clocks = <&k3_clks 270 1>; | |
2827 | status = "disabled"; | |
2828 | }; | |
2829 | ||
2830 | main_spi5: spi@2150000 { | |
2831 | compatible = "ti,am654-mcspi","ti,omap4-mcspi"; | |
2832 | reg = <0x00 0x02150000 0x00 0x400>; | |
2833 | interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; | |
2834 | #address-cells = <1>; | |
2835 | #size-cells = <0>; | |
2836 | power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; | |
2837 | clocks = <&k3_clks 271 1>; | |
2838 | status = "disabled"; | |
2839 | }; | |
2840 | ||
2841 | main_spi6: spi@2160000 { | |
2842 | compatible = "ti,am654-mcspi","ti,omap4-mcspi"; | |
2843 | reg = <0x00 0x02160000 0x00 0x400>; | |
2844 | interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; | |
2845 | #address-cells = <1>; | |
2846 | #size-cells = <0>; | |
2847 | power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; | |
2848 | clocks = <&k3_clks 272 1>; | |
2849 | status = "disabled"; | |
2850 | }; | |
2851 | ||
2852 | main_spi7: spi@2170000 { | |
2853 | compatible = "ti,am654-mcspi","ti,omap4-mcspi"; | |
2854 | reg = <0x00 0x02170000 0x00 0x400>; | |
2855 | interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; | |
2856 | #address-cells = <1>; | |
2857 | #size-cells = <0>; | |
2858 | power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; | |
2859 | clocks = <&k3_clks 273 1>; | |
2860 | status = "disabled"; | |
2861 | }; | |
19bfd518 NMF |
2862 | |
2863 | main_esm: esm@700000 { | |
2864 | compatible = "ti,j721e-esm"; | |
2865 | reg = <0x0 0x700000 0x0 0x1000>; | |
2866 | ti,esm-pins = <344>, <345>; | |
2867 | }; | |
2d87061e | 2868 | }; |