[linux-block.git] / arch / arm64 / boot / dts / ti / k3-am64-phycore-som.dtsi

// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * Copyright (C) 2021-2024 PHYTEC America, LLC - https://www.phytec.com
 * Author: Matt McKee <mmckee@phytec.com>
 *
 * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH
 * Author: Wadim Egorov <w.egorov@phytec.de>
 *
 * Product homepage:
 * https://www.phytec.com/product/phycore-am64x
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>

/ {
	model = "PHYTEC phyCORE-AM64x";
	compatible = "phytec,am64-phycore-som", "ti,am642";

	aliases {
		ethernet0 = &cpsw_port1;
		mmc0 = &sdhci0;
		rtc0 = &i2c_som_rtc;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
	};

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		secure_ddr: optee@9e800000 {
			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
			alignment = <0x1000>;
			no-map;
		};

		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa1000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa1100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa2000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa2100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa3000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa3100000 0x00 0xf00000>;
			no-map;
		};
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&leds_pins_default>;

		led-0 {
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
			function = LED_FUNCTION_HEARTBEAT;
		};
	};

	vcc_5v0_som: regulator-vcc-5v0-som {
		/* VIN / VCC_5V0_SOM */
		compatible = "regulator-fixed";
		regulator-name = "VCC_5V0_SOM";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
	};
};

&main_pmx0 {
	cpsw_mdio_pins_default: cpsw-mdio-default-pins {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x01f8, PIN_INPUT, 4)	/* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
			AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4)	/* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
			AM64X_IOPAD(0x0100, PIN_OUTPUT, 7)	/* (V7) PRG1_PRU0_GPO18.GPIO0_63 */
		>;
	};

	cpsw_rgmii1_pins_default: cpsw-rgmii1-default-pins {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0184, PIN_INPUT, 4)	/* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
			AM64X_IOPAD(0x0188, PIN_INPUT, 4)	/* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
			AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4)	/* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
			AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4)	/* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
			AM64X_IOPAD(0x01cc, PIN_INPUT, 4)	/* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
			AM64X_IOPAD(0x0124, PIN_OUTPUT, 4)	/* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
			AM64X_IOPAD(0x01d4, PIN_INPUT, 4)	/* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
			AM64X_IOPAD(0x012c, PIN_OUTPUT, 4)	/* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
			AM64X_IOPAD(0x01d8, PIN_INPUT, 4)	/* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
			AM64X_IOPAD(0x0130, PIN_OUTPUT, 4)	/* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
			AM64X_IOPAD(0x01f4, PIN_INPUT, 4)	/* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
			AM64X_IOPAD(0x014c, PIN_OUTPUT, 4)	/* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
			AM64X_IOPAD(0x0154, PIN_INPUT, 7)	/* (V12) PRG1_PRU1_GPO19.GPIO0_84 */
		>;
	};

	eeprom_wp_pins_default: eeprom-wp-default-pins {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0208, PIN_OUTPUT, 7)	/* (D12) SPI0_CS0.GPIO1_42 */
		>;
	};

	leds_pins_default: leds-default-pins {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0030, PIN_OUTPUT, 7)	/* (L18) OSPI0_CSn1.GPIO0_12 */
		>;
	};

	main_i2c0_pins_default: main-i2c0-default-pins {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0260, PIN_INPUT, 0)	/* (A18) I2C0_SCL */
			AM64X_IOPAD(0x0264, PIN_INPUT, 0)	/* (B18) I2C0_SDA */
		>;
	};

	ospi0_pins_default: ospi0-default-pins {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0000, PIN_OUTPUT, 0)	/* (N20) OSPI0_CLK */
			AM64X_IOPAD(0x0008, PIN_INPUT, 0)	/* (N19) OSPI0_DQS */
			AM64X_IOPAD(0x000c, PIN_INPUT, 0)	/* (M19) OSPI0_D0 */
			AM64X_IOPAD(0x0010, PIN_INPUT, 0)	/* (M18) OSPI0_D1 */
			AM64X_IOPAD(0x0014, PIN_INPUT, 0)	/* (M20) OSPI0_D2 */
			AM64X_IOPAD(0x0018, PIN_INPUT, 0)	/* (M21) OSPI0_D3 */
			AM64X_IOPAD(0x001c, PIN_INPUT, 0)	/* (P21) OSPI0_D4 */
			AM64X_IOPAD(0x0020, PIN_INPUT, 0)	/* (P20) OSPI0_D5 */
			AM64X_IOPAD(0x0024, PIN_INPUT, 0)	/* (N18) OSPI0_D6 */
			AM64X_IOPAD(0x0028, PIN_INPUT, 0)	/* (M17) OSPI0_D7 */
			AM64X_IOPAD(0x002c, PIN_OUTPUT, 0)	/* (L19) OSPI0_CSn0 */
		>;
	};

	rtc_pins_default: rtc-defaults-pins {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0278, PIN_INPUT, 7)	/* (C19) EXTINTn.GPIO1_70 */
		>;
	};
};

&cpsw3g {
	pinctrl-names = "default";
	pinctrl-0 = <&cpsw_rgmii1_pins_default>;
};

&cpsw3g_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&cpsw_mdio_pins_default>;

	cpsw3g_phy1: ethernet-phy@1 {
		compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
		reg = <1>;
		interrupt-parent = <&main_gpio0>;
		interrupts = <84 IRQ_TYPE_EDGE_FALLING>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		reset-gpios = <&main_gpio0 63 GPIO_ACTIVE_LOW>;
		reset-assert-us = <1000>;
		reset-deassert-us = <1000>;
	};
};

&cpsw_port1 {
	phy-mode = "rgmii-rxid";
	phy-handle = <&cpsw3g_phy1>;
};

&cpsw_port2 {
	status = "disabled";
};

&mailbox0_cluster2 {
	status = "okay";

	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
		ti,mbox-rx = <0 0 2>;
		ti,mbox-tx = <1 0 2>;
	};

	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
		ti,mbox-rx = <2 0 2>;
		ti,mbox-tx = <3 0 2>;
	};
};

&mailbox0_cluster4 {
	status = "okay";

	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
		ti,mbox-rx = <0 0 2>;
		ti,mbox-tx = <1 0 2>;
	};

	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
		ti,mbox-rx = <2 0 2>;
		ti,mbox-tx = <3 0 2>;
	};
};

&main_i2c0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;
	clock-frequency = <400000>;

	eeprom@50 {
		compatible = "atmel,24c32";
		pinctrl-names = "default";
		pinctrl-0 = <&eeprom_wp_pins_default>;
		pagesize = <32>;
		reg = <0x50>;
	};

	i2c_som_rtc: rtc@52 {
		compatible = "microcrystal,rv3028";
		reg = <0x52>;
		pinctrl-names = "default";
		pinctrl-0 = <&rtc_pins_default>;
		interrupt-parent = <&main_gpio1>;
		interrupts = <70 IRQ_TYPE_EDGE_FALLING>;
		wakeup-source;
	};
};

&main_r5fss0_core0 {
	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
	memory-region = <&main_r5fss0_core0_dma_memory_region>,
			<&main_r5fss0_core0_memory_region>;
};

&main_r5fss0_core1 {
	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
	memory-region = <&main_r5fss0_core1_dma_memory_region>,
			<&main_r5fss0_core1_memory_region>;
};

&main_r5fss1_core0 {
	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
	memory-region = <&main_r5fss1_core0_dma_memory_region>,
			<&main_r5fss1_core0_memory_region>;
};

&main_r5fss1_core1 {
	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
	memory-region = <&main_r5fss1_core1_dma_memory_region>,
			<&main_r5fss1_core1_memory_region>;
};

&ospi0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&ospi0_pins_default>;

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <8>;
		spi-rx-bus-width = <8>;
		spi-max-frequency = <25000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <0>;
	};
};

&sdhci0 {
	status = "okay";
	bus-width = <8>;
	non-removable;
	ti,driver-strength-ohm = <50>;
	disable-wp;
	keep-power-in-suspend;
};

&tscadc0 {
	status = "okay";
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};
Commit	Line	Data
049010c9	1	// SPDX-License-Identifier: GPL-2.0-only OR MIT
c48ac0ef	2	/*
049010c9	3	* Copyright (C) 2021-2024 PHYTEC America, LLC - https://www.phytec.com
c48ac0ef WE	4	* Author: Matt McKee <mmckee@phytec.com>
c48ac0ef WE	5	*
049010c9	6	* Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH
c48ac0ef WE	7	* Author: Wadim Egorov <w.egorov@phytec.de>
	8	*
	9	* Product homepage:
	10	* https://www.phytec.com/product/phycore-am64x
	11	*/
	12
	13	#include <dt-bindings/gpio/gpio.h>
	14	#include <dt-bindings/leds/common.h>
	15	#include <dt-bindings/net/ti-dp83867.h>
	16
	17	/ {
	18	model = "PHYTEC phyCORE-AM64x";
	19	compatible = "phytec,am64-phycore-som", "ti,am642";
	20
	21	aliases {
	22	ethernet0 = &cpsw_port1;
	23	mmc0 = &sdhci0;
	24	rtc0 = &i2c_som_rtc;
	25	};
	26
	27	memory@80000000 {
	28	device_type = "memory";
	29	reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
	30	};
	31
5709a680	32	reserved_memory: reserved-memory {
c48ac0ef WE	33	#address-cells = <2>;
	34	#size-cells = <2>;
	35	ranges;
	36
	37	secure_ddr: optee@9e800000 {
	38	reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
	39	alignment = <0x1000>;
	40	no-map;
	41	};
5709a680 GG	42
	43	main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
	44	compatible = "shared-dma-pool";
	45	reg = <0x00 0xa0000000 0x00 0x100000>;
	46	no-map;
	47	};
	48
	49	main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
	50	compatible = "shared-dma-pool";
	51	reg = <0x00 0xa0100000 0x00 0xf00000>;
	52	no-map;
	53	};
	54
	55	main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
	56	compatible = "shared-dma-pool";
	57	reg = <0x00 0xa1000000 0x00 0x100000>;
	58	no-map;
	59	};
	60
	61	main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
	62	compatible = "shared-dma-pool";
	63	reg = <0x00 0xa1100000 0x00 0xf00000>;
	64	no-map;
	65	};
	66
	67	main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
	68	compatible = "shared-dma-pool";
	69	reg = <0x00 0xa2000000 0x00 0x100000>;
	70	no-map;
	71	};
	72
	73	main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
	74	compatible = "shared-dma-pool";
	75	reg = <0x00 0xa2100000 0x00 0xf00000>;
	76	no-map;
	77	};
	78
	79	main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
	80	compatible = "shared-dma-pool";
	81	reg = <0x00 0xa3000000 0x00 0x100000>;
	82	no-map;
	83	};
	84
	85	main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
	86	compatible = "shared-dma-pool";
	87	reg = <0x00 0xa3100000 0x00 0xf00000>;
	88	no-map;
	89	};
c48ac0ef WE	90	};
	91
	92	leds {
	93	compatible = "gpio-leds";
	94	pinctrl-names = "default";
	95	pinctrl-0 = <&leds_pins_default>;
	96
	97	led-0 {
	98	color = <LED_COLOR_ID_GREEN>;
	99	gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
	100	linux,default-trigger = "heartbeat";
	101	function = LED_FUNCTION_HEARTBEAT;
	102	};
	103	};
	104
	105	vcc_5v0_som: regulator-vcc-5v0-som {
	106	/* VIN / VCC_5V0_SOM */
	107	compatible = "regulator-fixed";
	108	regulator-name = "VCC_5V0_SOM";
	109	regulator-min-microvolt = <5000000>;
	110	regulator-max-microvolt = <5000000>;
	111	regulator-always-on;
	112	regulator-boot-on;
	113	};
	114	};
	115
	116	&main_pmx0 {
a4956811	117	cpsw_mdio_pins_default: cpsw-mdio-default-pins {
c48ac0ef WE	118	pinctrl-single,pins = <
	119	AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
	120	AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
	121	AM64X_IOPAD(0x0100, PIN_OUTPUT, 7) /* (V7) PRG1_PRU0_GPO18.GPIO0_63 */
	122	>;
	123	};
	124
a4956811	125	cpsw_rgmii1_pins_default: cpsw-rgmii1-default-pins {
c48ac0ef WE	126	pinctrl-single,pins = <
	127	AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
	128	AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
	129	AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
	130	AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
	131	AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
	132	AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
	133	AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
	134	AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
	135	AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
	136	AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
	137	AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
	138	AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
	139	AM64X_IOPAD(0x0154, PIN_INPUT, 7) /* (V12) PRG1_PRU1_GPO19.GPIO0_84 */
	140	>;
	141	};
	142
a4956811	143	eeprom_wp_pins_default: eeprom-wp-default-pins {
c48ac0ef WE	144	pinctrl-single,pins = <
	145	AM64X_IOPAD(0x0208, PIN_OUTPUT, 7) /* (D12) SPI0_CS0.GPIO1_42 */
	146	>;
	147	};
	148
a4956811	149	leds_pins_default: leds-default-pins {
c48ac0ef WE	150	pinctrl-single,pins = <
	151	AM64X_IOPAD(0x0030, PIN_OUTPUT, 7) /* (L18) OSPI0_CSn1.GPIO0_12 */
	152	>;
	153	};
	154
a4956811	155	main_i2c0_pins_default: main-i2c0-default-pins {
c48ac0ef WE	156	pinctrl-single,pins = <
	157	AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* (A18) I2C0_SCL */
	158	AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* (B18) I2C0_SDA */
	159	>;
	160	};
	161
a4956811	162	ospi0_pins_default: ospi0-default-pins {
c48ac0ef WE	163	pinctrl-single,pins = <
	164	AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
	165	AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
	166	AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
	167	AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
	168	AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
	169	AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
	170	AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
	171	AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
	172	AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
	173	AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
	174	AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
	175	>;
	176	};
a1cd710f WE	177
	178	rtc_pins_default: rtc-defaults-pins {
	179	pinctrl-single,pins = <
	180	AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* (C19) EXTINTn.GPIO1_70 */
	181	>;
	182	};
c48ac0ef WE	183	};
	184
	185	&cpsw3g {
	186	pinctrl-names = "default";
	187	pinctrl-0 = <&cpsw_rgmii1_pins_default>;
	188	};
	189
	190	&cpsw3g_mdio {
	191	status = "okay";
	192	pinctrl-names = "default";
	193	pinctrl-0 = <&cpsw_mdio_pins_default>;
	194
	195	cpsw3g_phy1: ethernet-phy@1 {
	196	compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
	197	reg = <1>;
	198	interrupt-parent = <&main_gpio0>;
	199	interrupts = <84 IRQ_TYPE_EDGE_FALLING>;
	200	ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
	201	ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	202	reset-gpios = <&main_gpio0 63 GPIO_ACTIVE_LOW>;
	203	reset-assert-us = <1000>;
	204	reset-deassert-us = <1000>;
	205	};
	206	};
	207
	208	&cpsw_port1 {
	209	phy-mode = "rgmii-rxid";
	210	phy-handle = <&cpsw3g_phy1>;
	211	};
	212
	213	&cpsw_port2 {
	214	status = "disabled";
	215	};
	216
5709a680 GG	217	&mailbox0_cluster2 {
	218	status = "okay";
	219
	220	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
	221	ti,mbox-rx = <0 0 2>;
	222	ti,mbox-tx = <1 0 2>;
	223	};
	224
	225	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
	226	ti,mbox-rx = <2 0 2>;
	227	ti,mbox-tx = <3 0 2>;
	228	};
	229	};
	230
	231	&mailbox0_cluster4 {
	232	status = "okay";
	233
	234	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
	235	ti,mbox-rx = <0 0 2>;
	236	ti,mbox-tx = <1 0 2>;
	237	};
	238
	239	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
	240	ti,mbox-rx = <2 0 2>;
	241	ti,mbox-tx = <3 0 2>;
	242	};
	243	};
	244
c48ac0ef WE	245	&main_i2c0 {
	246	status = "okay";
	247	pinctrl-names = "default";
	248	pinctrl-0 = <&main_i2c0_pins_default>;
	249	clock-frequency = <400000>;
	250
	251	eeprom@50 {
	252	compatible = "atmel,24c32";
	253	pinctrl-names = "default";
	254	pinctrl-0 = <&eeprom_wp_pins_default>;
	255	pagesize = <32>;
	256	reg = <0x50>;
	257	};
	258
	259	i2c_som_rtc: rtc@52 {
	260	compatible = "microcrystal,rv3028";
	261	reg = <0x52>;
a1cd710f WE	262	pinctrl-names = "default";
	263	pinctrl-0 = <&rtc_pins_default>;
	264	interrupt-parent = <&main_gpio1>;
	265	interrupts = <70 IRQ_TYPE_EDGE_FALLING>;
	266	wakeup-source;
c48ac0ef WE	267	};
	268	};
	269
5709a680 GG	270	&main_r5fss0_core0 {
	271	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
	272	memory-region = <&main_r5fss0_core0_dma_memory_region>,
	273	<&main_r5fss0_core0_memory_region>;
	274	};
	275
	276	&main_r5fss0_core1 {
	277	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
	278	memory-region = <&main_r5fss0_core1_dma_memory_region>,
	279	<&main_r5fss0_core1_memory_region>;
	280	};
	281
	282	&main_r5fss1_core0 {
	283	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
	284	memory-region = <&main_r5fss1_core0_dma_memory_region>,
	285	<&main_r5fss1_core0_memory_region>;
	286	};
	287
	288	&main_r5fss1_core1 {
	289	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
	290	memory-region = <&main_r5fss1_core1_dma_memory_region>,
	291	<&main_r5fss1_core1_memory_region>;
	292	};
	293
c48ac0ef	294	&ospi0 {
cd9f6b32	295	status = "okay";
c48ac0ef WE	296	pinctrl-names = "default";
	297	pinctrl-0 = <&ospi0_pins_default>;
	298
	299	flash@0 {
	300	compatible = "jedec,spi-nor";
	301	reg = <0x0>;
	302	spi-tx-bus-width = <8>;
	303	spi-rx-bus-width = <8>;
	304	spi-max-frequency = <25000000>;
	305	cdns,tshsl-ns = <60>;
	306	cdns,tsd2d-ns = <60>;
	307	cdns,tchsh-ns = <60>;
	308	cdns,tslch-ns = <60>;
	309	cdns,read-delay = <0>;
	310	};
	311	};
	312
	313	&sdhci0 {
3b6345e3	314	status = "okay";
c48ac0ef WE	315	bus-width = <8>;
	316	non-removable;
	317	ti,driver-strength-ohm = <50>;
	318	disable-wp;
	319	keep-power-in-suspend;
	320	};
61fc6b43 NM	321
	322	&tscadc0 {
	323	status = "okay";
	324	adc {
	325	ti,adc-channels = <0 1 2 3 4 5 6 7>;
	326	};
	327	};