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arm64: dts: uniphier: Add L2 cache node
[linux-block.git] / arch / arm64 / boot / dts / socionext / uniphier-pxs3.dtsi
CommitLineData
05f7e3d1
MY		 1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Device Tree Source for UniPhier PXs3 SoC
4//
5// Copyright (C) 2017 Socionext Inc.
6// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
c28adcb5 7
b6e5ec20 8#include <dt-bindings/gpio/gpio.h>
8311ca57 9#include <dt-bindings/gpio/uniphier-gpio.h>
5ba95e8e 10#include <dt-bindings/interrupt-controller/arm-gic.h>
4b7d3743 11#include <dt-bindings/thermal/thermal.h>
b6e5ec20 12
c28adcb5
MY		 13/ {
14 compatible = "socionext,uniphier-pxs3";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
18
19 cpus {
20 #address-cells = <2>;
21 #size-cells = <0>;
22
23 cpu-map {
24 cluster0 {
25 core0 {
26 cpu = <&cpu0>;
27 };
28 core1 {
29 cpu = <&cpu1>;
30 };
31 core2 {
32 cpu = <&cpu2>;
33 };
34 core3 {
35 cpu = <&cpu3>;
36 };
37 };
38 };
39
40 cpu0: cpu@0 {
41 device_type = "cpu";
31af04cd 42 compatible = "arm,cortex-a53";
c28adcb5
MY		 43 reg = <0 0x000>;
44 clocks = <&sys_clk 33>;
45 enable-method = "psci";
5381a96c 46 next-level-cache = <&l2>;
c28adcb5 47 operating-points-v2 = <&cluster0_opp>;
4b7d3743 48 #cooling-cells = <2>;
c28adcb5
MY		 49 };
50
51 cpu1: cpu@1 {
52 device_type = "cpu";
31af04cd 53 compatible = "arm,cortex-a53";
c28adcb5
MY		 54 reg = <0 0x001>;
55 clocks = <&sys_clk 33>;
56 enable-method = "psci";
5381a96c 57 next-level-cache = <&l2>;
c28adcb5 58 operating-points-v2 = <&cluster0_opp>;
4b7d3743 59 #cooling-cells = <2>;
c28adcb5
MY		 60 };
61
62 cpu2: cpu@2 {
63 device_type = "cpu";
31af04cd 64 compatible = "arm,cortex-a53";
c28adcb5
MY		 65 reg = <0 0x002>;
66 clocks = <&sys_clk 33>;
67 enable-method = "psci";
5381a96c 68 next-level-cache = <&l2>;
c28adcb5 69 operating-points-v2 = <&cluster0_opp>;
4b7d3743 70 #cooling-cells = <2>;
c28adcb5
MY		 71 };
72
73 cpu3: cpu@3 {
74 device_type = "cpu";
31af04cd 75 compatible = "arm,cortex-a53";
c28adcb5
MY		 76 reg = <0 0x003>;
77 clocks = <&sys_clk 33>;
78 enable-method = "psci";
5381a96c 79 next-level-cache = <&l2>;
c28adcb5 80 operating-points-v2 = <&cluster0_opp>;
4b7d3743 81 #cooling-cells = <2>;
c28adcb5 82 };
5381a96c
KH		 83
84 l2: l2-cache {
85 compatible = "cache";
86 };
c28adcb5
MY		 87 };
88
9cd7d03f 89 cluster0_opp: opp-table {
c28adcb5
MY		 90 compatible = "operating-points-v2";
91 opp-shared;
92
93 opp-250000000 {
94 opp-hz = /bits/ 64 <250000000>;
95 clock-latency-ns = <300>;
96 };
97 opp-325000000 {
98 opp-hz = /bits/ 64 <325000000>;
99 clock-latency-ns = <300>;
100 };
101 opp-500000000 {
102 opp-hz = /bits/ 64 <500000000>;
103 clock-latency-ns = <300>;
104 };
105 opp-650000000 {
106 opp-hz = /bits/ 64 <650000000>;
107 clock-latency-ns = <300>;
108 };
109 opp-666667000 {
110 opp-hz = /bits/ 64 <666667000>;
111 clock-latency-ns = <300>;
112 };
113 opp-866667000 {
114 opp-hz = /bits/ 64 <866667000>;
115 clock-latency-ns = <300>;
116 };
117 opp-1000000000 {
118 opp-hz = /bits/ 64 <1000000000>;
119 clock-latency-ns = <300>;
120 };
121 opp-1300000000 {
122 opp-hz = /bits/ 64 <1300000000>;
123 clock-latency-ns = <300>;
124 };
125 };
126
127 psci {
128 compatible = "arm,psci-1.0";
129 method = "smc";
130 };
131
132 clocks {
133 refclk: ref {
134 compatible = "fixed-clock";
135 #clock-cells = <0>;
136 clock-frequency = <25000000>;
137 };
138 };
139
b6e5ec20
MY		 140 emmc_pwrseq: emmc-pwrseq {
141 compatible = "mmc-pwrseq-emmc";
8311ca57 142 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
b6e5ec20
MY		 143 };
144
c28adcb5
MY		 145 timer {
146 compatible = "arm,armv8-timer";
5ba95e8e
KH		 147 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
c28adcb5
MY		 151 };
152
4b7d3743
KH		 153 thermal-zones {
154 cpu-thermal {
155 polling-delay-passive = <250>; /* 250ms */
156 polling-delay = <1000>; /* 1000ms */
157 thermal-sensors = <&pvtctl>;
158
159 trips {
160 cpu_crit: cpu-crit {
161 temperature = <110000>; /* 110C */
162 hysteresis = <2000>;
163 type = "critical";
164 };
165 cpu_alert: cpu-alert {
166 temperature = <100000>; /* 100C */
167 hysteresis = <2000>;
168 type = "passive";
169 };
170 };
171
172 cooling-maps {
173 map0 {
174 trip = <&cpu_alert>;
175 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
176 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
177 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
178 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
179 };
180 };
181 };
182 };
183
aa385712
MY		 184 reserved-memory {
185 #address-cells = <2>;
186 #size-cells = <2>;
187 ranges;
188
189 secure-memory@81000000 {
190 reg = <0x0 0x81000000 0x0 0x01000000>;
191 no-map;
192 };
193 };
194
c28adcb5
MY		 195 soc@0 {
196 compatible = "simple-bus";
197 #address-cells = <1>;
198 #size-cells = <1>;
199 ranges = <0 0 0 0xffffffff>;
200
925c5c32
KH		 201 spi0: spi@54006000 {
202 compatible = "socionext,uniphier-scssi";
203 status = "disabled";
204 reg = <0x54006000 0x100>;
1a13827b
MY		 205 #address-cells = <1>;
206 #size-cells = <0>;
5ba95e8e 207 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
925c5c32
KH		 208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_spi0>;
210 clocks = <&peri_clk 11>;
211 resets = <&peri_rst 11>;
212 };
213
214 spi1: spi@54006100 {
215 compatible = "socionext,uniphier-scssi";
216 status = "disabled";
217 reg = <0x54006100 0x100>;
1a13827b
MY		 218 #address-cells = <1>;
219 #size-cells = <0>;
5ba95e8e 220 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
925c5c32
KH		 221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_spi1>;
fdf9c17b
KH		 223 clocks = <&peri_clk 12>;
224 resets = <&peri_rst 12>;
925c5c32
KH		 225 };
226
c28adcb5
MY		 227 serial0: serial@54006800 {
228 compatible = "socionext,uniphier-uart";
229 status = "disabled";
230 reg = <0x54006800 0x40>;
5ba95e8e 231 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
c28adcb5
MY		 232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_uart0>;
234 clocks = <&peri_clk 0>;
76c48e1e 235 resets = <&peri_rst 0>;
c28adcb5
MY		 236 };
237
238 serial1: serial@54006900 {
239 compatible = "socionext,uniphier-uart";
240 status = "disabled";
241 reg = <0x54006900 0x40>;
5ba95e8e 242 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
c28adcb5
MY		 243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_uart1>;
245 clocks = <&peri_clk 1>;
76c48e1e 246 resets = <&peri_rst 1>;
c28adcb5
MY		 247 };
248
249 serial2: serial@54006a00 {
250 compatible = "socionext,uniphier-uart";
251 status = "disabled";
252 reg = <0x54006a00 0x40>;
5ba95e8e 253 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
c28adcb5
MY		 254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_uart2>;
256 clocks = <&peri_clk 2>;
76c48e1e 257 resets = <&peri_rst 2>;
c28adcb5
MY		 258 };
259
260 serial3: serial@54006b00 {
261 compatible = "socionext,uniphier-uart";
262 status = "disabled";
263 reg = <0x54006b00 0x40>;
5ba95e8e 264 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
c28adcb5
MY		 265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_uart3>;
267 clocks = <&peri_clk 3>;
76c48e1e 268 resets = <&peri_rst 3>;
c28adcb5
MY		 269 };
270
277b51e7
MY		 271 gpio: gpio@55000000 {
272 compatible = "socionext,uniphier-gpio";
273 reg = <0x55000000 0x200>;
274 interrupt-parent = <&aidet>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
277 gpio-controller;
278 #gpio-cells = <2>;
279 gpio-ranges = <&pinctrl 0 0 0>,
abb62c46
MY		 280 <&pinctrl 104 0 0>,
281 <&pinctrl 168 0 0>;
277b51e7
MY		 282 gpio-ranges-group-names = "gpio_range0",
283 "gpio_range1",
284 "gpio_range2";
285 ngpios = <286>;
286 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
287 <21 217 3>;
288 };
289
c28adcb5
MY		 290 i2c0: i2c@58780000 {
291 compatible = "socionext,uniphier-fi2c";
292 status = "disabled";
293 reg = <0x58780000 0x80>;
294 #address-cells = <1>;
295 #size-cells = <0>;
5ba95e8e 296 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
c28adcb5
MY		 297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_i2c0>;
299 clocks = <&peri_clk 4>;
76c48e1e 300 resets = <&peri_rst 4>;
c28adcb5
MY		 301 clock-frequency = <100000>;
302 };
303
304 i2c1: i2c@58781000 {
305 compatible = "socionext,uniphier-fi2c";
306 status = "disabled";
307 reg = <0x58781000 0x80>;
308 #address-cells = <1>;
309 #size-cells = <0>;
5ba95e8e 310 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
c28adcb5
MY		 311 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_i2c1>;
313 clocks = <&peri_clk 5>;
76c48e1e 314 resets = <&peri_rst 5>;
c28adcb5
MY		 315 clock-frequency = <100000>;
316 };
317
318 i2c2: i2c@58782000 {
319 compatible = "socionext,uniphier-fi2c";
320 status = "disabled";
321 reg = <0x58782000 0x80>;
322 #address-cells = <1>;
323 #size-cells = <0>;
5ba95e8e 324 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
c28adcb5
MY		 325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_i2c2>;
327 clocks = <&peri_clk 6>;
76c48e1e 328 resets = <&peri_rst 6>;
c28adcb5
MY		 329 clock-frequency = <100000>;
330 };
331
332 i2c3: i2c@58783000 {
333 compatible = "socionext,uniphier-fi2c";
334 status = "disabled";
335 reg = <0x58783000 0x80>;
336 #address-cells = <1>;
337 #size-cells = <0>;
5ba95e8e 338 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
c28adcb5
MY		 339 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_i2c3>;
341 clocks = <&peri_clk 7>;
76c48e1e 342 resets = <&peri_rst 7>;
c28adcb5
MY		 343 clock-frequency = <100000>;
344 };
345
346 /* chip-internal connection for HDMI */
347 i2c6: i2c@58786000 {
348 compatible = "socionext,uniphier-fi2c";
349 reg = <0x58786000 0x80>;
350 #address-cells = <1>;
351 #size-cells = <0>;
5ba95e8e 352 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
c28adcb5 353 clocks = <&peri_clk 10>;
76c48e1e 354 resets = <&peri_rst 10>;
c28adcb5
MY		 355 clock-frequency = <400000>;
356 };
357
358 system_bus: system-bus@58c00000 {
359 compatible = "socionext,uniphier-system-bus";
360 status = "disabled";
361 reg = <0x58c00000 0x400>;
362 #address-cells = <2>;
363 #size-cells = <1>;
364 pinctrl-names = "default";
365 pinctrl-0 = <&pinctrl_system_bus>;
366 };
367
368 smpctrl@59801000 {
369 compatible = "socionext,uniphier-smpctrl";
370 reg = <0x59801000 0x400>;
371 };
372
373 sdctrl@59810000 {
374 compatible = "socionext,uniphier-pxs3-sdctrl",
375 "simple-mfd", "syscon";
376 reg = <0x59810000 0x400>;
377
378 sd_clk: clock {
379 compatible = "socionext,uniphier-pxs3-sd-clock";
380 #clock-cells = <1>;
381 };
382
383 sd_rst: reset {
384 compatible = "socionext,uniphier-pxs3-sd-reset";
385 #reset-cells = <1>;
386 };
387 };
388
389 perictrl@59820000 {
390 compatible = "socionext,uniphier-pxs3-perictrl",
391 "simple-mfd", "syscon";
392 reg = <0x59820000 0x200>;
393
394 peri_clk: clock {
395 compatible = "socionext,uniphier-pxs3-peri-clock";
396 #clock-cells = <1>;
397 };
398
399 peri_rst: reset {
400 compatible = "socionext,uniphier-pxs3-peri-reset";
401 #reset-cells = <1>;
402 };
403 };
404
bb3f4672 405 emmc: mmc@5a000000 {
c28adcb5
MY		 406 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
407 reg = <0x5a000000 0x400>;
5ba95e8e 408 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
c28adcb5
MY		 409 pinctrl-names = "default";
410 pinctrl-0 = <&pinctrl_emmc>;
411 clocks = <&sys_clk 4>;
76c48e1e 412 resets = <&sys_rst 4>;
c28adcb5
MY		 413 bus-width = <8>;
414 mmc-ddr-1_8v;
415 mmc-hs200-1_8v;
b6e5ec20 416 mmc-pwrseq = <&emmc_pwrseq>;
f4e5200f 417 cdns,phy-input-delay-legacy = <9>;
c28adcb5
MY		 418 cdns,phy-input-delay-mmc-highspeed = <2>;
419 cdns,phy-input-delay-mmc-ddr = <3>;
420 cdns,phy-dll-delay-sdclk = <21>;
421 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
422 };
423
bb3f4672 424 sd: mmc@5a400000 {
84a9c4d5
MY		 425 compatible = "socionext,uniphier-sd-v3.1.1";
426 status = "disabled";
427 reg = <0x5a400000 0x800>;
5ba95e8e 428 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
84a9c4d5
MY		 429 pinctrl-names = "default", "uhs";
430 pinctrl-0 = <&pinctrl_sd>;
431 pinctrl-1 = <&pinctrl_sd_uhs>;
432 clocks = <&sd_clk 0>;
433 reset-names = "host";
434 resets = <&sd_rst 0>;
435 bus-width = <4>;
436 cap-sd-highspeed;
437 sd-uhs-sdr12;
438 sd-uhs-sdr25;
439 sd-uhs-sdr50;
440 };
441
b076ff8b 442 soc_glue: soc-glue@5f800000 {
c28adcb5
MY		 443 compatible = "socionext,uniphier-pxs3-soc-glue",
444 "simple-mfd", "syscon";
445 reg = <0x5f800000 0x2000>;
446
447 pinctrl: pinctrl {
448 compatible = "socionext,uniphier-pxs3-pinctrl";
449 };
450 };
451
f05851e1
KH		 452 soc-glue@5f900000 {
453 compatible = "socionext,uniphier-pxs3-soc-glue-debug",
454 "simple-mfd";
455 #address-cells = <1>;
456 #size-cells = <1>;
457 ranges = <0 0x5f900000 0x2000>;
458
459 efuse@100 {
460 compatible = "socionext,uniphier-efuse";
461 reg = <0x100 0x28>;
462 };
463
464 efuse@200 {
465 compatible = "socionext,uniphier-efuse";
466 reg = <0x200 0x68>;
d7b9beb8
KH		 467 #address-cells = <1>;
468 #size-cells = <1>;
469
470 /* USB cells */
471 usb_rterm0: trim@54,4 {
472 reg = <0x54 1>;
473 bits = <4 2>;
474 };
475 usb_rterm1: trim@55,4 {
476 reg = <0x55 1>;
477 bits = <4 2>;
478 };
479 usb_rterm2: trim@58,4 {
480 reg = <0x58 1>;
481 bits = <4 2>;
482 };
483 usb_rterm3: trim@59,4 {
484 reg = <0x59 1>;
485 bits = <4 2>;
486 };
487 usb_sel_t0: trim@54,0 {
488 reg = <0x54 1>;
489 bits = <0 4>;
490 };
491 usb_sel_t1: trim@55,0 {
492 reg = <0x55 1>;
493 bits = <0 4>;
494 };
495 usb_sel_t2: trim@58,0 {
496 reg = <0x58 1>;
497 bits = <0 4>;
498 };
499 usb_sel_t3: trim@59,0 {
500 reg = <0x59 1>;
501 bits = <0 4>;
502 };
503 usb_hs_i0: trim@56,0 {
504 reg = <0x56 1>;
505 bits = <0 4>;
506 };
507 usb_hs_i2: trim@5a,0 {
508 reg = <0x5a 1>;
509 bits = <0 4>;
510 };
f05851e1
KH		 511 };
512 };
513
f03b998d
KH		 514 xdmac: dma-controller@5fc10000 {
515 compatible = "socionext,uniphier-xdmac";
516 reg = <0x5fc10000 0x5300>;
5ba95e8e 517 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
f03b998d
KH		 518 dma-channels = <16>;
519 #dma-cells = <2>;
520 };
521
9ddc285b 522 aidet: interrupt-controller@5fc20000 {
c28adcb5
MY		 523 compatible = "socionext,uniphier-pxs3-aidet";
524 reg = <0x5fc20000 0x200>;
525 interrupt-controller;
526 #interrupt-cells = <2>;
527 };
528
529 gic: interrupt-controller@5fe00000 {
530 compatible = "arm,gic-v3";
531 reg = <0x5fe00000 0x10000>, /* GICD */
532 <0x5fe80000 0x80000>; /* GICR */
533 interrupt-controller;
534 #interrupt-cells = <3>;
5ba95e8e 535 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
c28adcb5
MY		 536 };
537
538 sysctrl@61840000 {
539 compatible = "socionext,uniphier-pxs3-sysctrl",
540 "simple-mfd", "syscon";
541 reg = <0x61840000 0x10000>;
542
543 sys_clk: clock {
544 compatible = "socionext,uniphier-pxs3-clock";
545 #clock-cells = <1>;
546 };
547
548 sys_rst: reset {
549 compatible = "socionext,uniphier-pxs3-reset";
550 #reset-cells = <1>;
551 };
552
553 watchdog {
554 compatible = "socionext,uniphier-wdt";
555 };
4b7d3743 556
2dfb62d6 557 pvtctl: thermal-sensor {
4b7d3743 558 compatible = "socionext,uniphier-pxs3-thermal";
5ba95e8e 559 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
4b7d3743
KH		 560 #thermal-sensor-cells = <0>;
561 socionext,tmod-calibration = <0x0f22 0x68ee>;
562 };
c28adcb5
MY		 563 };
564
aba054a1
KH		 565 eth0: ethernet@65000000 {
566 compatible = "socionext,uniphier-pxs3-ave4";
567 status = "disabled";
568 reg = <0x65000000 0x8500>;
5ba95e8e 569 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
aba054a1
KH		 570 pinctrl-names = "default";
571 pinctrl-0 = <&pinctrl_ether_rgmii>;
a34a464d 572 clock-names = "ether";
aba054a1 573 clocks = <&sys_clk 6>;
a34a464d 574 reset-names = "ether";
aba054a1 575 resets = <&sys_rst 6>;
dcabb06b 576 phy-mode = "rgmii-id";
aba054a1 577 local-mac-address = [00 00 00 00 00 00];
b076ff8b 578 socionext,syscon-phy-mode = <&soc_glue 0>;
aba054a1
KH		 579
580 mdio0: mdio {
581 #address-cells = <1>;
582 #size-cells = <0>;
583 };
584 };
585
586 eth1: ethernet@65200000 {
587 compatible = "socionext,uniphier-pxs3-ave4";
588 status = "disabled";
589 reg = <0x65200000 0x8500>;
5ba95e8e 590 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
aba054a1
KH		 591 pinctrl-names = "default";
592 pinctrl-0 = <&pinctrl_ether1_rgmii>;
a34a464d 593 clock-names = "ether";
aba054a1 594 clocks = <&sys_clk 7>;
a34a464d 595 reset-names = "ether";
aba054a1 596 resets = <&sys_rst 7>;
dcabb06b 597 phy-mode = "rgmii-id";
aba054a1 598 local-mac-address = [00 00 00 00 00 00];
b076ff8b 599 socionext,syscon-phy-mode = <&soc_glue 1>;
aba054a1
KH		 600
601 mdio1: mdio {
602 #address-cells = <1>;
603 #size-cells = <0>;
604 };
605 };
606
23e001e7
KH		 607 ahci0: sata@65600000 {
608 compatible = "socionext,uniphier-pxs3-ahci",
609 "generic-ahci";
610 status = "disabled";
611 reg = <0x65600000 0x10000>;
612 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&sys_clk 28>;
614 resets = <&sys_rst 28>, <&ahci0_rst 0>;
615 ports-implemented = <1>;
616 phys = <&ahci0_phy>;
617 };
618
619 sata-controller@65700000 {
620 compatible = "socionext,uniphier-pxs3-ahci-glue",
621 "simple-mfd";
622 #address-cells = <1>;
623 #size-cells = <1>;
624 ranges = <0 0x65700000 0x100>;
625
626 ahci0_rst: reset-controller@0 {
627 compatible = "socionext,uniphier-pxs3-ahci-reset";
628 reg = <0x0 0x4>;
629 clock-names = "link";
630 clocks = <&sys_clk 28>;
631 reset-names = "link";
632 resets = <&sys_rst 28>;
633 #reset-cells = <1>;
634 };
635
636 ahci0_phy: sata-phy@10 {
637 compatible = "socionext,uniphier-pxs3-ahci-phy";
638 reg = <0x10 0x10>;
639 clock-names = "link", "phy";
640 clocks = <&sys_clk 28>, <&sys_clk 30>;
641 reset-names = "link", "phy";
642 resets = <&sys_rst 28>, <&sys_rst 30>;
643 #phy-cells = <0>;
644 };
645 };
646
647 ahci1: sata@65800000 {
648 compatible = "socionext,uniphier-pxs3-ahci",
649 "generic-ahci";
650 status = "disabled";
651 reg = <0x65800000 0x10000>;
652 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&sys_clk 29>;
654 resets = <&sys_rst 29>, <&ahci1_rst 0>;
655 ports-implemented = <1>;
656 phys = <&ahci1_phy>;
657 };
658
659 sata-controller@65900000 {
660 compatible = "socionext,uniphier-pxs3-ahci-glue",
661 "simple-mfd";
662 #address-cells = <1>;
663 #size-cells = <1>;
664 ranges = <0 0x65900000 0x100>;
665
666 ahci1_rst: reset-controller@0 {
667 compatible = "socionext,uniphier-pxs3-ahci-reset";
668 reg = <0x0 0x4>;
669 clock-names = "link";
670 clocks = <&sys_clk 29>;
671 reset-names = "link";
672 resets = <&sys_rst 29>;
673 #reset-cells = <1>;
674 };
675
676 ahci1_phy: sata-phy@10 {
677 compatible = "socionext,uniphier-pxs3-ahci-phy";
678 reg = <0x10 0x10>;
679 clock-names = "link", "phy";
680 clocks = <&sys_clk 29>, <&sys_clk 30>;
681 reset-names = "link", "phy";
682 resets = <&sys_rst 29>, <&sys_rst 30>;
683 #phy-cells = <0>;
684 };
685 };
686
d7b9beb8
KH		 687 usb0: usb@65a00000 {
688 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
689 status = "disabled";
690 reg = <0x65a00000 0xcd00>;
fe17b91a 691 interrupt-names = "dwc_usb3";
5ba95e8e 692 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
d7b9beb8
KH		 693 pinctrl-names = "default";
694 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
695 clock-names = "ref", "bus_early", "suspend";
696 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
697 resets = <&usb0_rst 15>;
698 phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
699 <&usb0_ssphy0>, <&usb0_ssphy1>;
700 dr_mode = "host";
701 };
702
4cc752a8 703 usb-controller@65b00000 {
d7b9beb8
KH		 704 compatible = "socionext,uniphier-pxs3-dwc3-glue",
705 "simple-mfd";
706 #address-cells = <1>;
707 #size-cells = <1>;
708 ranges = <0 0x65b00000 0x400>;
709
710 usb0_rst: reset@0 {
711 compatible = "socionext,uniphier-pxs3-usb3-reset";
712 reg = <0x0 0x4>;
713 #reset-cells = <1>;
714 clock-names = "link";
715 clocks = <&sys_clk 12>;
716 reset-names = "link";
717 resets = <&sys_rst 12>;
718 };
719
720 usb0_vbus0: regulator@100 {
721 compatible = "socionext,uniphier-pxs3-usb3-regulator";
722 reg = <0x100 0x10>;
723 clock-names = "link";
724 clocks = <&sys_clk 12>;
725 reset-names = "link";
726 resets = <&sys_rst 12>;
727 };
728
729 usb0_vbus1: regulator@110 {
730 compatible = "socionext,uniphier-pxs3-usb3-regulator";
731 reg = <0x110 0x10>;
732 clock-names = "link";
733 clocks = <&sys_clk 12>;
734 reset-names = "link";
735 resets = <&sys_rst 12>;
736 };
737
738 usb0_hsphy0: hs-phy@200 {
739 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
740 reg = <0x200 0x10>;
741 #phy-cells = <0>;
742 clock-names = "link", "phy";
743 clocks = <&sys_clk 12>, <&sys_clk 16>;
744 reset-names = "link", "phy";
745 resets = <&sys_rst 12>, <&sys_rst 16>;
746 vbus-supply = <&usb0_vbus0>;
747 nvmem-cell-names = "rterm", "sel_t", "hs_i";
748 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
749 <&usb_hs_i0>;
750 };
751
752 usb0_hsphy1: hs-phy@210 {
753 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
754 reg = <0x210 0x10>;
755 #phy-cells = <0>;
756 clock-names = "link", "phy";
757 clocks = <&sys_clk 12>, <&sys_clk 16>;
758 reset-names = "link", "phy";
759 resets = <&sys_rst 12>, <&sys_rst 16>;
760 vbus-supply = <&usb0_vbus1>;
761 nvmem-cell-names = "rterm", "sel_t", "hs_i";
762 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
763 <&usb_hs_i0>;
764 };
765
766 usb0_ssphy0: ss-phy@300 {
767 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
768 reg = <0x300 0x10>;
769 #phy-cells = <0>;
770 clock-names = "link", "phy";
771 clocks = <&sys_clk 12>, <&sys_clk 17>;
772 reset-names = "link", "phy";
773 resets = <&sys_rst 12>, <&sys_rst 17>;
774 vbus-supply = <&usb0_vbus0>;
775 };
776
777 usb0_ssphy1: ss-phy@310 {
778 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
779 reg = <0x310 0x10>;
780 #phy-cells = <0>;
781 clock-names = "link", "phy";
782 clocks = <&sys_clk 12>, <&sys_clk 18>;
783 reset-names = "link", "phy";
784 resets = <&sys_rst 12>, <&sys_rst 18>;
785 vbus-supply = <&usb0_vbus1>;
786 };
787 };
788
789 usb1: usb@65c00000 {
790 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
791 status = "disabled";
792 reg = <0x65c00000 0xcd00>;
fe17b91a 793 interrupt-names = "dwc_usb3";
5ba95e8e 794 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
d7b9beb8
KH		 795 pinctrl-names = "default";
796 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
797 clock-names = "ref", "bus_early", "suspend";
798 clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>;
799 resets = <&usb1_rst 15>;
800 phys = <&usb1_hsphy0>, <&usb1_hsphy1>,
801 <&usb1_ssphy0>;
802 dr_mode = "host";
803 };
804
4cc752a8 805 usb-controller@65d00000 {
d7b9beb8
KH		 806 compatible = "socionext,uniphier-pxs3-dwc3-glue",
807 "simple-mfd";
808 #address-cells = <1>;
809 #size-cells = <1>;
810 ranges = <0 0x65d00000 0x400>;
811
812 usb1_rst: reset@0 {
813 compatible = "socionext,uniphier-pxs3-usb3-reset";
814 reg = <0x0 0x4>;
815 #reset-cells = <1>;
816 clock-names = "link";
817 clocks = <&sys_clk 13>;
818 reset-names = "link";
819 resets = <&sys_rst 13>;
820 };
821
822 usb1_vbus0: regulator@100 {
823 compatible = "socionext,uniphier-pxs3-usb3-regulator";
824 reg = <0x100 0x10>;
825 clock-names = "link";
826 clocks = <&sys_clk 13>;
827 reset-names = "link";
828 resets = <&sys_rst 13>;
829 };
830
831 usb1_vbus1: regulator@110 {
832 compatible = "socionext,uniphier-pxs3-usb3-regulator";
833 reg = <0x110 0x10>;
834 clock-names = "link";
835 clocks = <&sys_clk 13>;
836 reset-names = "link";
837 resets = <&sys_rst 13>;
838 };
839
840 usb1_hsphy0: hs-phy@200 {
841 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
842 reg = <0x200 0x10>;
843 #phy-cells = <0>;
844 clock-names = "link", "phy", "phy-ext";
845 clocks = <&sys_clk 13>, <&sys_clk 20>,
846 <&sys_clk 14>;
847 reset-names = "link", "phy";
848 resets = <&sys_rst 13>, <&sys_rst 20>;
849 vbus-supply = <&usb1_vbus0>;
850 nvmem-cell-names = "rterm", "sel_t", "hs_i";
851 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
852 <&usb_hs_i2>;
853 };
854
855 usb1_hsphy1: hs-phy@210 {
856 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
857 reg = <0x210 0x10>;
858 #phy-cells = <0>;
859 clock-names = "link", "phy", "phy-ext";
860 clocks = <&sys_clk 13>, <&sys_clk 20>,
861 <&sys_clk 14>;
862 reset-names = "link", "phy";
863 resets = <&sys_rst 13>, <&sys_rst 20>;
864 vbus-supply = <&usb1_vbus1>;
865 nvmem-cell-names = "rterm", "sel_t", "hs_i";
866 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
867 <&usb_hs_i2>;
868 };
869
870 usb1_ssphy0: ss-phy@300 {
871 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
872 reg = <0x300 0x10>;
873 #phy-cells = <0>;
874 clock-names = "link", "phy", "phy-ext";
875 clocks = <&sys_clk 13>, <&sys_clk 21>,
876 <&sys_clk 14>;
877 reset-names = "link", "phy";
878 resets = <&sys_rst 13>, <&sys_rst 21>;
879 vbus-supply = <&usb1_vbus0>;
880 };
881 };
882
32dfc773 883 pcie: pcie@66000000 {
d93ecbf5 884 compatible = "socionext,uniphier-pcie";
32dfc773
KH		 885 status = "disabled";
886 reg-names = "dbi", "link", "config";
887 reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
888 <0x2fff0000 0x10000>;
889 #address-cells = <3>;
890 #size-cells = <2>;
891 clocks = <&sys_clk 24>;
892 resets = <&sys_rst 24>;
893 num-lanes = <1>;
894 num-viewport = <1>;
895 bus-range = <0x0 0xff>;
896 device_type = "pci";
897 ranges =
898 /* downstream I/O */
899 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
900 /* non-prefetchable memory */
901 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
902 #interrupt-cells = <1>;
903 interrupt-names = "dma", "msi";
5ba95e8e
KH		 904 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
905 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
32dfc773
KH		 906 interrupt-map-mask = <0 0 0 7>;
907 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
908 <0 0 0 2 &pcie_intc 1>, /* INTB */
909 <0 0 0 3 &pcie_intc 2>, /* INTC */
910 <0 0 0 4 &pcie_intc 3>; /* INTD */
911 phy-names = "pcie-phy";
912 phys = <&pcie_phy>;
913
914 pcie_intc: legacy-interrupt-controller {
915 interrupt-controller;
916 #interrupt-cells = <1>;
917 interrupt-parent = <&gic>;
5ba95e8e 918 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
32dfc773
KH		 919 };
920 };
921
922 pcie_phy: phy@66038000 {
923 compatible = "socionext,uniphier-pxs3-pcie-phy";
924 reg = <0x66038000 0x4000>;
925 #phy-cells = <0>;
e6bd81a2 926 clock-names = "link";
32dfc773 927 clocks = <&sys_clk 24>;
e6bd81a2 928 reset-names = "link";
32dfc773
KH		 929 resets = <&sys_rst 24>;
930 socionext,syscon = <&soc_glue>;
931 };
932
fcb0e53c 933 nand: nand-controller@68000000 {
c28adcb5
MY		 934 compatible = "socionext,uniphier-denali-nand-v5b";
935 status = "disabled";
936 reg-names = "nand_data", "denali_reg";
937 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
53c580c1
MY		 938 #address-cells = <1>;
939 #size-cells = <0>;
5ba95e8e 940 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
c28adcb5
MY		 941 pinctrl-names = "default";
942 pinctrl-0 = <&pinctrl_nand>;
bae120f8
MY		 943 clock-names = "nand", "nand_x", "ecc";
944 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
e98d5023
MY		 945 reset-names = "nand", "reg";
946 resets = <&sys_rst 2>, <&sys_rst 2>;
c28adcb5
MY		 947 };
948 };
949};
950
951#include "uniphier-pinctrl.dtsi"
Linux 6.x block layer and io_uring tree(s)