[linux-2.6-block.git] / arch / arm64 / boot / dts / socionext / uniphier-ld20.dtsi

// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier LD20 SoC
//
// Copyright (C) 2015-2016 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
#include <dt-bindings/thermal/thermal.h>

/memreserve/ 0x80000000 0x02000000;

/ {
	compatible = "socionext,uniphier-ld20";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu2>;
				};
				core1 {
					cpu = <&cpu3>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0 0x000>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			operating-points-v2 = <&cluster0_opp>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0 0x001>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0 0x100>;
			clocks = <&sys_clk 33>;
			enable-method = "psci";
			operating-points-v2 = <&cluster1_opp>;
			#cooling-cells = <2>;
		};

		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0 0x101>;
			clocks = <&sys_clk 33>;
			enable-method = "psci";
			operating-points-v2 = <&cluster1_opp>;
		};
	};

	cluster0_opp: opp-table0 {
		compatible = "operating-points-v2";
		opp-shared;

		opp-250000000 {
			opp-hz = /bits/ 64 <250000000>;
			clock-latency-ns = <300>;
		};
		opp-275000000 {
			opp-hz = /bits/ 64 <275000000>;
			clock-latency-ns = <300>;
		};
		opp-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			clock-latency-ns = <300>;
		};
		opp-550000000 {
			opp-hz = /bits/ 64 <550000000>;
			clock-latency-ns = <300>;
		};
		opp-666667000 {
			opp-hz = /bits/ 64 <666667000>;
			clock-latency-ns = <300>;
		};
		opp-733334000 {
			opp-hz = /bits/ 64 <733334000>;
			clock-latency-ns = <300>;
		};
		opp-1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			clock-latency-ns = <300>;
		};
		opp-1100000000 {
			opp-hz = /bits/ 64 <1100000000>;
			clock-latency-ns = <300>;
		};
	};

	cluster1_opp: opp-table1 {
		compatible = "operating-points-v2";
		opp-shared;

		opp-250000000 {
			opp-hz = /bits/ 64 <250000000>;
			clock-latency-ns = <300>;
		};
		opp-275000000 {
			opp-hz = /bits/ 64 <275000000>;
			clock-latency-ns = <300>;
		};
		opp-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			clock-latency-ns = <300>;
		};
		opp-550000000 {
			opp-hz = /bits/ 64 <550000000>;
			clock-latency-ns = <300>;
		};
		opp-666667000 {
			opp-hz = /bits/ 64 <666667000>;
			clock-latency-ns = <300>;
		};
		opp-733334000 {
			opp-hz = /bits/ 64 <733334000>;
			clock-latency-ns = <300>;
		};
		opp-1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			clock-latency-ns = <300>;
		};
		opp-1100000000 {
			opp-hz = /bits/ 64 <1100000000>;
			clock-latency-ns = <300>;
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	clocks {
		refclk: ref {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
	};

	emmc_pwrseq: emmc-pwrseq {
		compatible = "mmc-pwrseq-emmc";
		reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 4>,
			     <1 14 4>,
			     <1 11 4>,
			     <1 10 4>;
	};

	thermal-zones {
		cpu-thermal {
			polling-delay-passive = <250>;	/* 250ms */
			polling-delay = <1000>;		/* 1000ms */
			thermal-sensors = <&pvtctl>;

			trips {
				cpu_crit: cpu-crit {
					temperature = <110000>;	/* 110C */
					hysteresis = <2000>;
					type = "critical";
				};
				cpu_alert: cpu-alert {
					temperature = <100000>;	/* 100C */
					hysteresis = <2000>;
					type = "passive";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert>;
					cooling-device = <&cpu0
					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
				map1 {
					trip = <&cpu_alert>;
					cooling-device = <&cpu2
					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <0 33 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&peri_clk 0>;
			resets = <&peri_rst 0>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <0 35 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			clocks = <&peri_clk 1>;
			resets = <&peri_rst 1>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <0 37 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			clocks = <&peri_clk 2>;
			resets = <&peri_rst 2>;
		};

		serial3: serial@54006b00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006b00 0x40>;
			interrupts = <0 177 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			clocks = <&peri_clk 3>;
			resets = <&peri_rst 3>;
		};

		gpio: gpio@55000000 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000000 0x200>;
			interrupt-parent = <&aidet>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 0>,
				      <&pinctrl 96 0 0>,
				      <&pinctrl 160 0 0>;
			gpio-ranges-group-names = "gpio_range0",
						  "gpio_range1",
						  "gpio_range2";
			ngpios = <205>;
			socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
						     <21 217 3>;
		};

		audio@56000000 {
			compatible = "socionext,uniphier-ld20-aio";
			reg = <0x56000000 0x80000>;
			interrupts = <0 144 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_aout1>,
				    <&pinctrl_aoutiec1>;
			clock-names = "aio";
			clocks = <&sys_clk 40>;
			reset-names = "aio";
			resets = <&sys_rst 40>;
			#sound-dai-cells = <1>;
			socionext,syscon = <&soc_glue>;

			i2s_port0: port@0 {
				i2s_hdmi: endpoint {
				};
			};

			i2s_port1: port@1 {
				i2s_pcmin2: endpoint {
				};
			};

			i2s_port2: port@2 {
				i2s_line: endpoint {
					dai-format = "i2s";
					remote-endpoint = <&evea_line>;
				};
			};

			i2s_port3: port@3 {
				i2s_hpcmout1: endpoint {
				};
			};

			i2s_port4: port@4 {
				i2s_hp: endpoint {
					dai-format = "i2s";
					remote-endpoint = <&evea_hp>;
				};
			};

			spdif_port0: port@5 {
				spdif_hiecout1: endpoint {
				};
			};

			src_port0: port@6 {
				i2s_epcmout2: endpoint {
				};
			};

			src_port1: port@7 {
				i2s_epcmout3: endpoint {
				};
			};

			comp_spdif_port0: port@8 {
				comp_spdif_hiecout1: endpoint {
				};
			};
		};

		codec@57900000 {
			compatible = "socionext,uniphier-evea";
			reg = <0x57900000 0x1000>;
			clock-names = "evea", "exiv";
			clocks = <&sys_clk 41>, <&sys_clk 42>;
			reset-names = "evea", "exiv", "adamv";
			resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
			#sound-dai-cells = <1>;

			port@0 {
				evea_line: endpoint {
					remote-endpoint = <&i2s_line>;
				};
			};

			port@1 {
				evea_hp: endpoint {
					remote-endpoint = <&i2s_hp>;
				};
			};
		};

		adamv@57920000 {
			compatible = "socionext,uniphier-ld20-adamv",
				     "simple-mfd", "syscon";
			reg = <0x57920000 0x1000>;

			adamv_rst: reset {
				compatible = "socionext,uniphier-ld20-adamv-reset";
				#reset-cells = <1>;
			};
		};

		i2c0: i2c@58780000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58780000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 41 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			clocks = <&peri_clk 4>;
			resets = <&peri_rst 4>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58781000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58781000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 42 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1>;
			clocks = <&peri_clk 5>;
			resets = <&peri_rst 5>;
			clock-frequency = <100000>;
		};

		i2c2: i2c@58782000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58782000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 43 4>;
			clocks = <&peri_clk 6>;
			resets = <&peri_rst 6>;
			clock-frequency = <400000>;
		};

		i2c3: i2c@58783000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58783000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 44 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3>;
			clocks = <&peri_clk 7>;
			resets = <&peri_rst 7>;
			clock-frequency = <100000>;
		};

		i2c4: i2c@58784000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58784000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 45 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c4>;
			clocks = <&peri_clk 8>;
			resets = <&peri_rst 8>;
			clock-frequency = <100000>;
		};

		i2c5: i2c@58785000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58785000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 25 4>;
			clocks = <&peri_clk 9>;
			resets = <&peri_rst 9>;
			clock-frequency = <400000>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			status = "disabled";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_system_bus>;
		};

		smpctrl@59801000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		sdctrl@59810000 {
			compatible = "socionext,uniphier-ld20-sdctrl",
				     "simple-mfd", "syscon";
			reg = <0x59810000 0x400>;

			sd_clk: clock {
				compatible = "socionext,uniphier-ld20-sd-clock";
				#clock-cells = <1>;
			};

			sd_rst: reset {
				compatible = "socionext,uniphier-ld20-sd-reset";
				#reset-cells = <1>;
			};
		};

		perictrl@59820000 {
			compatible = "socionext,uniphier-ld20-perictrl",
				     "simple-mfd", "syscon";
			reg = <0x59820000 0x200>;

			peri_clk: clock {
				compatible = "socionext,uniphier-ld20-peri-clock";
				#clock-cells = <1>;
			};

			peri_rst: reset {
				compatible = "socionext,uniphier-ld20-peri-reset";
				#reset-cells = <1>;
			};
		};

		emmc: sdhc@5a000000 {
			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
			reg = <0x5a000000 0x400>;
			interrupts = <0 78 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_emmc>;
			clocks = <&sys_clk 4>;
			resets = <&sys_rst 4>;
			bus-width = <8>;
			mmc-ddr-1_8v;
			mmc-hs200-1_8v;
			mmc-pwrseq = <&emmc_pwrseq>;
			cdns,phy-input-delay-legacy = <9>;
			cdns,phy-input-delay-mmc-highspeed = <2>;
			cdns,phy-input-delay-mmc-ddr = <3>;
			cdns,phy-dll-delay-sdclk = <21>;
			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
		};

		soc_glue: soc-glue@5f800000 {
			compatible = "socionext,uniphier-ld20-soc-glue",
				     "simple-mfd", "syscon";
			reg = <0x5f800000 0x2000>;

			pinctrl: pinctrl {
				compatible = "socionext,uniphier-ld20-pinctrl";
			};
		};

		soc-glue@5f900000 {
			compatible = "socionext,uniphier-ld20-soc-glue-debug",
				     "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x5f900000 0x2000>;

			efuse@100 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x100 0x28>;
			};

			efuse@200 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x200 0x68>;
			};
		};

		aidet: aidet@5fc20000 {
			compatible = "socionext,uniphier-ld20-aidet";
			reg = <0x5fc20000 0x200>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gic: interrupt-controller@5fe00000 {
			compatible = "arm,gic-v3";
			reg = <0x5fe00000 0x10000>,	/* GICD */
			      <0x5fe80000 0x80000>;	/* GICR */
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <1 9 4>;
		};

		sysctrl@61840000 {
			compatible = "socionext,uniphier-ld20-sysctrl",
				     "simple-mfd", "syscon";
			reg = <0x61840000 0x10000>;

			sys_clk: clock {
				compatible = "socionext,uniphier-ld20-clock";
				#clock-cells = <1>;
			};

			sys_rst: reset {
				compatible = "socionext,uniphier-ld20-reset";
				#reset-cells = <1>;
			};

			watchdog {
				compatible = "socionext,uniphier-wdt";
			};

			pvtctl: pvtctl {
				compatible = "socionext,uniphier-ld20-thermal";
				interrupts = <0 3 4>;
				#thermal-sensor-cells = <0>;
				socionext,tmod-calibration = <0x0f22 0x68ee>;
			};
		};

		eth: ethernet@65000000 {
			compatible = "socionext,uniphier-ld20-ave4";
			status = "disabled";
			reg = <0x65000000 0x8500>;
			interrupts = <0 66 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_ether_rgmii>;
			clocks = <&sys_clk 6>;
			resets = <&sys_rst 6>;
			phy-mode = "rgmii";
			local-mac-address = [00 00 00 00 00 00];

			mdio: mdio {
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		nand: nand@68000000 {
			compatible = "socionext,uniphier-denali-nand-v5b";
			status = "disabled";
			reg-names = "nand_data", "denali_reg";
			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
			interrupts = <0 65 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand>;
			clocks = <&sys_clk 2>;
			resets = <&sys_rst 2>;
		};
	};
};

#include "uniphier-pinctrl.dtsi"

&pinctrl_aout1 {
	drive-strength = <4>;	/* default: 3.5mA */

	ao1dacck {
		pins = "AO1DACCK";
		drive-strength = <5>;	/* 5mA */
	};
};

&pinctrl_aoutiec1 {
	drive-strength = <4>;	/* default: 3.5mA */

	ao1arc {
		pins = "AO1ARC";
		drive-strength = <11>;	/* 11mA */
	};
};
Commit	Line	Data
05f7e3d1 MY	1	// SPDX-License-Identifier: GPL-2.0+ OR MIT
	2	//
	3	// Device Tree Source for UniPhier LD20 SoC
	4	//
	5	// Copyright (C) 2015-2016 Socionext Inc.
	6	// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
e1a0ebc8	7
b6e5ec20	8	#include <dt-bindings/gpio/gpio.h>
8311ca57	9	#include <dt-bindings/gpio/uniphier-gpio.h>
dba74980 KH	10	#include <dt-bindings/thermal/thermal.h>
dba74980 KH	11
79d4be39	12	/memreserve/ 0x80000000 0x02000000;
ffd8a5ed	13
e1a0ebc8	14	/ {
cea59bd0	15	compatible = "socionext,uniphier-ld20";
e1a0ebc8 MY	16	#address-cells = <2>;
	17	#size-cells = <2>;
	18	interrupt-parent = <&gic>;
	19
	20	cpus {
	21	#address-cells = <2>;
	22	#size-cells = <0>;
	23
	24	cpu-map {
	25	cluster0 {
	26	core0 {
	27	cpu = <&cpu0>;
	28	};
	29	core1 {
	30	cpu = <&cpu1>;
	31	};
	32	};
	33
	34	cluster1 {
	35	core0 {
	36	cpu = <&cpu2>;
	37	};
	38	core1 {
	39	cpu = <&cpu3>;
	40	};
	41	};
	42	};
	43
	44	cpu0: cpu@0 {
	45	device_type = "cpu";
	46	compatible = "arm,cortex-a72", "arm,armv8";
	47	reg = <0 0x000>;
183ad366	48	clocks = <&sys_clk 32>;
2f81137f	49	enable-method = "psci";
183ad366	50	operating-points-v2 = <&cluster0_opp>;
dba74980	51	#cooling-cells = <2>;
e1a0ebc8 MY	52	};
	53
	54	cpu1: cpu@1 {
	55	device_type = "cpu";
	56	compatible = "arm,cortex-a72", "arm,armv8";
	57	reg = <0 0x001>;
183ad366	58	clocks = <&sys_clk 32>;
2f81137f	59	enable-method = "psci";
183ad366	60	operating-points-v2 = <&cluster0_opp>;
e1a0ebc8 MY	61	};
	62
	63	cpu2: cpu@100 {
	64	device_type = "cpu";
	65	compatible = "arm,cortex-a53", "arm,armv8";
	66	reg = <0 0x100>;
183ad366	67	clocks = <&sys_clk 33>;
2f81137f	68	enable-method = "psci";
183ad366	69	operating-points-v2 = <&cluster1_opp>;
dba74980	70	#cooling-cells = <2>;
e1a0ebc8 MY	71	};
	72
	73	cpu3: cpu@101 {
	74	device_type = "cpu";
	75	compatible = "arm,cortex-a53", "arm,armv8";
	76	reg = <0 0x101>;
183ad366	77	clocks = <&sys_clk 33>;
2f81137f	78	enable-method = "psci";
183ad366 MY	79	operating-points-v2 = <&cluster1_opp>;
	80	};
	81	};
	82
9cd7d03f	83	cluster0_opp: opp-table0 {
183ad366 MY	84	compatible = "operating-points-v2";
	85	opp-shared;
	86
3fc9a121	87	opp-250000000 {
183ad366 MY	88	opp-hz = /bits/ 64 <250000000>;
	89	clock-latency-ns = <300>;
	90	};
3fc9a121	91	opp-275000000 {
183ad366 MY	92	opp-hz = /bits/ 64 <275000000>;
	93	clock-latency-ns = <300>;
	94	};
3fc9a121	95	opp-500000000 {
183ad366 MY	96	opp-hz = /bits/ 64 <500000000>;
	97	clock-latency-ns = <300>;
	98	};
3fc9a121	99	opp-550000000 {
183ad366 MY	100	opp-hz = /bits/ 64 <550000000>;
	101	clock-latency-ns = <300>;
	102	};
3fc9a121	103	opp-666667000 {
183ad366 MY	104	opp-hz = /bits/ 64 <666667000>;
	105	clock-latency-ns = <300>;
	106	};
3fc9a121	107	opp-733334000 {
183ad366 MY	108	opp-hz = /bits/ 64 <733334000>;
	109	clock-latency-ns = <300>;
	110	};
3fc9a121	111	opp-1000000000 {
183ad366 MY	112	opp-hz = /bits/ 64 <1000000000>;
	113	clock-latency-ns = <300>;
	114	};
3fc9a121	115	opp-1100000000 {
183ad366 MY	116	opp-hz = /bits/ 64 <1100000000>;
	117	clock-latency-ns = <300>;
	118	};
	119	};
	120
9cd7d03f	121	cluster1_opp: opp-table1 {
183ad366 MY	122	compatible = "operating-points-v2";
	123	opp-shared;
	124
3fc9a121	125	opp-250000000 {
183ad366 MY	126	opp-hz = /bits/ 64 <250000000>;
	127	clock-latency-ns = <300>;
	128	};
3fc9a121	129	opp-275000000 {
183ad366 MY	130	opp-hz = /bits/ 64 <275000000>;
	131	clock-latency-ns = <300>;
	132	};
3fc9a121	133	opp-500000000 {
183ad366 MY	134	opp-hz = /bits/ 64 <500000000>;
	135	clock-latency-ns = <300>;
	136	};
3fc9a121	137	opp-550000000 {
183ad366 MY	138	opp-hz = /bits/ 64 <550000000>;
	139	clock-latency-ns = <300>;
	140	};
3fc9a121	141	opp-666667000 {
183ad366 MY	142	opp-hz = /bits/ 64 <666667000>;
	143	clock-latency-ns = <300>;
	144	};
3fc9a121	145	opp-733334000 {
183ad366 MY	146	opp-hz = /bits/ 64 <733334000>;
	147	clock-latency-ns = <300>;
	148	};
3fc9a121	149	opp-1000000000 {
183ad366 MY	150	opp-hz = /bits/ 64 <1000000000>;
	151	clock-latency-ns = <300>;
	152	};
3fc9a121	153	opp-1100000000 {
183ad366 MY	154	opp-hz = /bits/ 64 <1100000000>;
183ad366 MY	155	clock-latency-ns = <300>;
e1a0ebc8 MY	156	};
	157	};
	158
2f81137f MY	159	psci {
	160	compatible = "arm,psci-1.0";
	161	method = "smc";
	162	};
	163
e1a0ebc8	164	clocks {
fb89cf36 MY	165	refclk: ref {
	166	compatible = "fixed-clock";
	167	#clock-cells = <0>;
	168	clock-frequency = <25000000>;
	169	};
e1a0ebc8 MY	170	};
e1a0ebc8 MY	171
b6e5ec20 MY	172	emmc_pwrseq: emmc-pwrseq {
b6e5ec20 MY	173	compatible = "mmc-pwrseq-emmc";
8311ca57	174	reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
b6e5ec20 MY	175	};
b6e5ec20 MY	176
e1a0ebc8 MY	177	timer {
e1a0ebc8 MY	178	compatible = "arm,armv8-timer";
f2a89d3b MZ	179	interrupts = <1 13 4>,
	180	<1 14 4>,
	181	<1 11 4>,
	182	<1 10 4>;
e1a0ebc8 MY	183	};
e1a0ebc8 MY	184
dba74980 KH	185	thermal-zones {
	186	cpu-thermal {
	187	polling-delay-passive = <250>; /* 250ms */
	188	polling-delay = <1000>; /* 1000ms */
	189	thermal-sensors = <&pvtctl>;
	190
	191	trips {
	192	cpu_crit: cpu-crit {
	193	temperature = <110000>; /* 110C */
	194	hysteresis = <2000>;
	195	type = "critical";
	196	};
	197	cpu_alert: cpu-alert {
	198	temperature = <100000>; /* 100C */
	199	hysteresis = <2000>;
	200	type = "passive";
	201	};
	202	};
	203
	204	cooling-maps {
	205	map0 {
	206	trip = <&cpu_alert>;
	207	cooling-device = <&cpu0
	208	THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	209	};
	210	map1 {
	211	trip = <&cpu_alert>;
	212	cooling-device = <&cpu2
	213	THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	214	};
	215	};
	216	};
	217	};
	218
b5027603	219	soc@0 {
e1a0ebc8 MY	220	compatible = "simple-bus";
	221	#address-cells = <1>;
	222	#size-cells = <1>;
	223	ranges = <0 0 0 0xffffffff>;
	224
e1a0ebc8 MY	225	serial0: serial@54006800 {
	226	compatible = "socionext,uniphier-uart";
	227	status = "disabled";
	228	reg = <0x54006800 0x40>;
	229	interrupts = <0 33 4>;
	230	pinctrl-names = "default";
	231	pinctrl-0 = <&pinctrl_uart0>;
42aee275	232	clocks = <&peri_clk 0>;
76c48e1e	233	resets = <&peri_rst 0>;
e1a0ebc8 MY	234	};
	235
	236	serial1: serial@54006900 {
	237	compatible = "socionext,uniphier-uart";
	238	status = "disabled";
	239	reg = <0x54006900 0x40>;
	240	interrupts = <0 35 4>;
	241	pinctrl-names = "default";
	242	pinctrl-0 = <&pinctrl_uart1>;
42aee275	243	clocks = <&peri_clk 1>;
76c48e1e	244	resets = <&peri_rst 1>;
e1a0ebc8 MY	245	};
	246
	247	serial2: serial@54006a00 {
	248	compatible = "socionext,uniphier-uart";
	249	status = "disabled";
	250	reg = <0x54006a00 0x40>;
	251	interrupts = <0 37 4>;
	252	pinctrl-names = "default";
	253	pinctrl-0 = <&pinctrl_uart2>;
42aee275	254	clocks = <&peri_clk 2>;
76c48e1e	255	resets = <&peri_rst 2>;
e1a0ebc8 MY	256	};
	257
	258	serial3: serial@54006b00 {
	259	compatible = "socionext,uniphier-uart";
	260	status = "disabled";
	261	reg = <0x54006b00 0x40>;
	262	interrupts = <0 177 4>;
	263	pinctrl-names = "default";
	264	pinctrl-0 = <&pinctrl_uart3>;
42aee275	265	clocks = <&peri_clk 3>;
76c48e1e	266	resets = <&peri_rst 3>;
e1a0ebc8 MY	267	};
e1a0ebc8 MY	268
277b51e7 MY	269	gpio: gpio@55000000 {
	270	compatible = "socionext,uniphier-gpio";
	271	reg = <0x55000000 0x200>;
	272	interrupt-parent = <&aidet>;
	273	interrupt-controller;
	274	#interrupt-cells = <2>;
	275	gpio-controller;
	276	#gpio-cells = <2>;
	277	gpio-ranges = <&pinctrl 0 0 0>,
	278	<&pinctrl 96 0 0>,
	279	<&pinctrl 160 0 0>;
	280	gpio-ranges-group-names = "gpio_range0",
	281	"gpio_range1",
	282	"gpio_range2";
	283	ngpios = <205>;
	284	socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
	285	<21 217 3>;
	286	};
	287
fb21a0ac KS	288	audio@56000000 {
	289	compatible = "socionext,uniphier-ld20-aio";
	290	reg = <0x56000000 0x80000>;
	291	interrupts = <0 144 4>;
	292	pinctrl-names = "default";
	293	pinctrl-0 = <&pinctrl_aout1>,
	294	<&pinctrl_aoutiec1>;
	295	clock-names = "aio";
	296	clocks = <&sys_clk 40>;
	297	reset-names = "aio";
	298	resets = <&sys_rst 40>;
	299	#sound-dai-cells = <1>;
6c35921d	300	socionext,syscon = <&soc_glue>;
fb21a0ac KS	301
	302	i2s_port0: port@0 {
	303	i2s_hdmi: endpoint {
	304	};
	305	};
	306
	307	i2s_port1: port@1 {
	308	i2s_pcmin2: endpoint {
	309	};
	310	};
	311
	312	i2s_port2: port@2 {
	313	i2s_line: endpoint {
	314	dai-format = "i2s";
	315	remote-endpoint = <&evea_line>;
	316	};
	317	};
	318
	319	i2s_port3: port@3 {
	320	i2s_hpcmout1: endpoint {
	321	};
	322	};
	323
	324	i2s_port4: port@4 {
	325	i2s_hp: endpoint {
	326	dai-format = "i2s";
	327	remote-endpoint = <&evea_hp>;
	328	};
	329	};
	330
	331	spdif_port0: port@5 {
	332	spdif_hiecout1: endpoint {
	333	};
	334	};
	335
	336	src_port0: port@6 {
	337	i2s_epcmout2: endpoint {
	338	};
	339	};
	340
	341	src_port1: port@7 {
	342	i2s_epcmout3: endpoint {
	343	};
	344	};
	345
	346	comp_spdif_port0: port@8 {
	347	comp_spdif_hiecout1: endpoint {
	348	};
	349	};
	350	};
	351
	352	codec@57900000 {
	353	compatible = "socionext,uniphier-evea";
	354	reg = <0x57900000 0x1000>;
	355	clock-names = "evea", "exiv";
	356	clocks = <&sys_clk 41>, <&sys_clk 42>;
	357	reset-names = "evea", "exiv", "adamv";
	358	resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
	359	#sound-dai-cells = <1>;
	360
	361	port@0 {
	362	evea_line: endpoint {
	363	remote-endpoint = <&i2s_line>;
	364	};
365	};
366
367	port@1 {
368	evea_hp: endpoint {
369	remote-endpoint = <&i2s_hp>;
370	};
371	};
372	};
373
178b3568 KS	374	adamv@57920000 {
	375	compatible = "socionext,uniphier-ld20-adamv",
	376	"simple-mfd", "syscon";
	377	reg = <0x57920000 0x1000>;
	378
	379	adamv_rst: reset {
	380	compatible = "socionext,uniphier-ld20-adamv-reset";
	381	#reset-cells = <1>;
	382	};
	383	};
	384
e1a0ebc8 MY	385	i2c0: i2c@58780000 {
	386	compatible = "socionext,uniphier-fi2c";
	387	status = "disabled";
	388	reg = <0x58780000 0x80>;
	389	#address-cells = <1>;
	390	#size-cells = <0>;
	391	interrupts = <0 41 4>;
	392	pinctrl-names = "default";
	393	pinctrl-0 = <&pinctrl_i2c0>;
42aee275	394	clocks = <&peri_clk 4>;
76c48e1e	395	resets = <&peri_rst 4>;
e1a0ebc8 MY	396	clock-frequency = <100000>;
	397	};
	398
	399	i2c1: i2c@58781000 {
	400	compatible = "socionext,uniphier-fi2c";
	401	status = "disabled";
	402	reg = <0x58781000 0x80>;
	403	#address-cells = <1>;
	404	#size-cells = <0>;
	405	interrupts = <0 42 4>;
	406	pinctrl-names = "default";
	407	pinctrl-0 = <&pinctrl_i2c1>;
42aee275	408	clocks = <&peri_clk 5>;
76c48e1e	409	resets = <&peri_rst 5>;
e1a0ebc8 MY	410	clock-frequency = <100000>;
	411	};
	412
	413	i2c2: i2c@58782000 {
	414	compatible = "socionext,uniphier-fi2c";
e1a0ebc8 MY	415	reg = <0x58782000 0x80>;
	416	#address-cells = <1>;
	417	#size-cells = <0>;
	418	interrupts = <0 43 4>;
42aee275	419	clocks = <&peri_clk 6>;
76c48e1e	420	resets = <&peri_rst 6>;
56896ef5	421	clock-frequency = <400000>;
e1a0ebc8 MY	422	};
	423
	424	i2c3: i2c@58783000 {
	425	compatible = "socionext,uniphier-fi2c";
	426	status = "disabled";
	427	reg = <0x58783000 0x80>;
	428	#address-cells = <1>;
	429	#size-cells = <0>;
	430	interrupts = <0 44 4>;
	431	pinctrl-names = "default";
	432	pinctrl-0 = <&pinctrl_i2c3>;
42aee275	433	clocks = <&peri_clk 7>;
76c48e1e	434	resets = <&peri_rst 7>;
e1a0ebc8 MY	435	clock-frequency = <100000>;
	436	};
	437
	438	i2c4: i2c@58784000 {
	439	compatible = "socionext,uniphier-fi2c";
56896ef5	440	status = "disabled";
e1a0ebc8 MY	441	reg = <0x58784000 0x80>;
	442	#address-cells = <1>;
	443	#size-cells = <0>;
	444	interrupts = <0 45 4>;
56896ef5 MY	445	pinctrl-names = "default";
56896ef5 MY	446	pinctrl-0 = <&pinctrl_i2c4>;
42aee275	447	clocks = <&peri_clk 8>;
76c48e1e	448	resets = <&peri_rst 8>;
56896ef5	449	clock-frequency = <100000>;
e1a0ebc8 MY	450	};
	451
	452	i2c5: i2c@58785000 {
	453	compatible = "socionext,uniphier-fi2c";
	454	reg = <0x58785000 0x80>;
	455	#address-cells = <1>;
	456	#size-cells = <0>;
	457	interrupts = <0 25 4>;
42aee275	458	clocks = <&peri_clk 9>;
76c48e1e	459	resets = <&peri_rst 9>;
e1a0ebc8 MY	460	clock-frequency = <400000>;
	461	};
	462
14bae133 MY	463	system_bus: system-bus@58c00000 {
	464	compatible = "socionext,uniphier-system-bus";
	465	status = "disabled";
	466	reg = <0x58c00000 0x400>;
	467	#address-cells = <2>;
	468	#size-cells = <1>;
5d9a83c9 MY	469	pinctrl-names = "default";
5d9a83c9 MY	470	pinctrl-0 = <&pinctrl_system_bus>;
14bae133 MY	471	};
14bae133 MY	472
b10ee7e3	473	smpctrl@59801000 {
14bae133 MY	474	compatible = "socionext,uniphier-smpctrl";
	475	reg = <0x59801000 0x400>;
	476	};
	477
8e68c65d MY	478	sdctrl@59810000 {
8e68c65d MY	479	compatible = "socionext,uniphier-ld20-sdctrl",
42aee275	480	"simple-mfd", "syscon";
555861fb	481	reg = <0x59810000 0x400>;
42aee275	482
8e68c65d MY	483	sd_clk: clock {
8e68c65d MY	484	compatible = "socionext,uniphier-ld20-sd-clock";
42aee275 MY	485	#clock-cells = <1>;
	486	};
	487
8e68c65d MY	488	sd_rst: reset {
8e68c65d MY	489	compatible = "socionext,uniphier-ld20-sd-reset";
42aee275 MY	490	#reset-cells = <1>;
	491	};
	492	};
	493
	494	perictrl@59820000 {
fb28cef0	495	compatible = "socionext,uniphier-ld20-perictrl",
42aee275 MY	496	"simple-mfd", "syscon";
	497	reg = <0x59820000 0x200>;
	498
	499	peri_clk: clock {
	500	compatible = "socionext,uniphier-ld20-peri-clock";
	501	#clock-cells = <1>;
	502	};
	503
	504	peri_rst: reset {
	505	compatible = "socionext,uniphier-ld20-peri-reset";
	506	#reset-cells = <1>;
	507	};
	508	};
	509
3a93cc26 MY	510	emmc: sdhc@5a000000 {
	511	compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
	512	reg = <0x5a000000 0x400>;
	513	interrupts = <0 78 4>;
9c0a9700 MY	514	pinctrl-names = "default";
9c0a9700 MY	515	pinctrl-0 = <&pinctrl_emmc>;
3a93cc26	516	clocks = <&sys_clk 4>;
76c48e1e	517	resets = <&sys_rst 4>;
3a93cc26 MY	518	bus-width = <8>;
	519	mmc-ddr-1_8v;
	520	mmc-hs200-1_8v;
b6e5ec20	521	mmc-pwrseq = <&emmc_pwrseq>;
f4e5200f	522	cdns,phy-input-delay-legacy = <9>;
ba6f7011 MY	523	cdns,phy-input-delay-mmc-highspeed = <2>;
ba6f7011 MY	524	cdns,phy-input-delay-mmc-ddr = <3>;
e345eded MY	525	cdns,phy-dll-delay-sdclk = <21>;
e345eded MY	526	cdns,phy-dll-delay-sdclk-hsmmc = <21>;
3a93cc26 MY	527	};
3a93cc26 MY	528
6c35921d	529	soc_glue: soc-glue@5f800000 {
fb28cef0	530	compatible = "socionext,uniphier-ld20-soc-glue",
9d4f5505	531	"simple-mfd", "syscon";
ed6cca5f MY	532	reg = <0x5f800000 0x2000>;
	533
	534	pinctrl: pinctrl {
cea59bd0	535	compatible = "socionext,uniphier-ld20-pinctrl";
ed6cca5f	536	};
e1a0ebc8 MY	537	};
e1a0ebc8 MY	538
f05851e1 KH	539	soc-glue@5f900000 {
	540	compatible = "socionext,uniphier-ld20-soc-glue-debug",
	541	"simple-mfd";
	542	#address-cells = <1>;
	543	#size-cells = <1>;
	544	ranges = <0 0x5f900000 0x2000>;
	545
	546	efuse@100 {
	547	compatible = "socionext,uniphier-efuse";
	548	reg = <0x100 0x28>;
	549	};
	550
	551	efuse@200 {
	552	compatible = "socionext,uniphier-efuse";
	553	reg = <0x200 0x68>;
	554	};
	555	};
	556
3dfc6e98 MY	557	aidet: aidet@5fc20000 {
	558	compatible = "socionext,uniphier-ld20-aidet";
	559	reg = <0x5fc20000 0x200>;
	560	interrupt-controller;
	561	#interrupt-cells = <2>;
	562	};
	563
e1a0ebc8 MY	564	gic: interrupt-controller@5fe00000 {
	565	compatible = "arm,gic-v3";
	566	reg = <0x5fe00000 0x10000>, /* GICD */
	567	<0x5fe80000 0x80000>; /* GICR */
	568	interrupt-controller;
	569	#interrupt-cells = <3>;
	570	interrupts = <1 9 4>;
	571	};
42aee275 MY	572
42aee275 MY	573	sysctrl@61840000 {
fb28cef0	574	compatible = "socionext,uniphier-ld20-sysctrl",
42aee275	575	"simple-mfd", "syscon";
1ef64af8	576	reg = <0x61840000 0x10000>;
42aee275 MY	577
	578	sys_clk: clock {
	579	compatible = "socionext,uniphier-ld20-clock";
	580	#clock-cells = <1>;
	581	};
	582
	583	sys_rst: reset {
	584	compatible = "socionext,uniphier-ld20-reset";
	585	#reset-cells = <1>;
	586	};
4c4c960a KH	587
	588	watchdog {
	589	compatible = "socionext,uniphier-wdt";
	590	};
dba74980 KH	591
	592	pvtctl: pvtctl {
	593	compatible = "socionext,uniphier-ld20-thermal";
	594	interrupts = <0 3 4>;
	595	#thermal-sensor-cells = <0>;
	596	socionext,tmod-calibration = <0x0f22 0x68ee>;
	597	};
42aee275	598	};
e5aefb38	599
c73730ee KH	600	eth: ethernet@65000000 {
	601	compatible = "socionext,uniphier-ld20-ave4";
	602	status = "disabled";
	603	reg = <0x65000000 0x8500>;
	604	interrupts = <0 66 4>;
	605	pinctrl-names = "default";
	606	pinctrl-0 = <&pinctrl_ether_rgmii>;
	607	clocks = <&sys_clk 6>;
	608	resets = <&sys_rst 6>;
	609	phy-mode = "rgmii";
	610	local-mac-address = [00 00 00 00 00 00];
	611
	612	mdio: mdio {
	613	#address-cells = <1>;
	614	#size-cells = <0>;
	615	};
	616	};
	617
e5aefb38 MY	618	nand: nand@68000000 {
	619	compatible = "socionext,uniphier-denali-nand-v5b";
	620	status = "disabled";
	621	reg-names = "nand_data", "denali_reg";
	622	reg = <0x68000000 0x20>, <0x68100000 0x1000>;
	623	interrupts = <0 65 4>;
	624	pinctrl-names = "default";
	625	pinctrl-0 = <&pinctrl_nand>;
	626	clocks = <&sys_clk 2>;
76c48e1e	627	resets = <&sys_rst 2>;
e5aefb38	628	};
e1a0ebc8 MY	629	};
	630	};
	631
5740ea4e	632	#include "uniphier-pinctrl.dtsi"
fb21a0ac KS	633
	634	&pinctrl_aout1 {
	635	drive-strength = <4>; /* default: 3.5mA */
	636
	637	ao1dacck {
	638	pins = "AO1DACCK";
	639	drive-strength = <5>; /* 5mA */
	640	};
	641	};
	642
	643	&pinctrl_aoutiec1 {
	644	drive-strength = <4>; /* default: 3.5mA */
	645
	646	ao1arc {
	647	pins = "AO1ARC";
	648	drive-strength = <11>; /* 11mA */
	649	};
	650	};