[linux-block.git] / arch / arm64 / boot / dts / rockchip / rk3568-radxa-e25.dts

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/dts-v1/;
#include "rk3568-radxa-cm3i.dtsi"

/ {
	model = "Radxa E25 Carrier Board";
	compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568";

	aliases {
		mmc1 = &sdmmc0;
	};

	pwm-leds {
		compatible = "pwm-leds-multicolor";

		multi-led {
			color = <LED_COLOR_ID_RGB>;
			max-brightness = <255>;

			led-red {
				color = <LED_COLOR_ID_RED>;
				pwms = <&pwm1 0 1000000 0>;
			};

			led-green {
				color = <LED_COLOR_ID_GREEN>;
				pwms = <&pwm2 0 1000000 0>;
			};

			led-blue {
				color = <LED_COLOR_ID_BLUE>;
				pwms = <&pwm12 0 1000000 0>;
			};
		};
	};

	vbus_typec: vbus-typec-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&vbus_typec_en>;
		regulator-name = "vbus_typec";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&vcc5v0_sys>;
	};

	vcc3v3_minipcie: vcc3v3-minipcie-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&minipcie_enable_h>;
		regulator-name = "vcc3v3_minipcie";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&vcc5v0_sys>;
	};

	vcc3v3_ngff: vcc3v3-ngff-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&ngffpcie_enable_h>;
		regulator-name = "vcc3v3_ngff";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vcc5v0_sys>;
	};

	/* actually fed by vcc5v0_sys, dependent
	 * on pi6c clock generator
	 */
	vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pcie30x1_enable_h>;
		regulator-name = "vcc3v3_pcie30x1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vcc3v3_pi6c_05>;
	};

	vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pcie_enable_h>;
		regulator-name = "vcc3v3_pcie";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vcc5v0_sys>;
	};
};

&pcie2x1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie20_reset_h>;
	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
	vpcie3v3-supply = <&vcc3v3_pi6c_05>;
	status = "okay";
};

&pcie30phy {
	data-lanes = <1 2>;
	status = "okay";
};

&pcie3x1 {
	num-lanes = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pcie30x1m0_pins>;
	reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
	vpcie3v3-supply = <&vcc3v3_pcie30x1>;
	status = "okay";
};

&pcie3x2 {
	num-lanes = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pcie30x2_reset_h>;
	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
	vpcie3v3-supply = <&vcc3v3_pi6c_05>;
	status = "okay";
};

&pinctrl {
	pcie {
		pcie20_reset_h: pcie20-reset-h {
			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		pcie30x1_enable_h: pcie30x1-enable-h {
			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		pcie30x2_reset_h: pcie30x2-reset-h {
			rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		pcie_enable_h: pcie-enable-h {
			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	usb {
		minipcie_enable_h: minipcie-enable-h {
			rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		ngffpcie_enable_h: ngffpcie-enable-h {
			rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		vbus_typec_en: vbus_typec_en {
			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};

&pwm1 {
	status = "okay";
};

&pwm2 {
	status = "okay";
};

&pwm12 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm12m1_pins>;
	status = "okay";
};

&sdmmc0 {
	bus-width = <4>;
	cap-sd-highspeed;
	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
	/* Also used in pcie30x1_clkreqnm0 */
	disable-wp;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
	sd-uhs-sdr104;
	vmmc-supply = <&vcc3v3_sd>;
	vqmmc-supply = <&vccio_sd>;
	status = "okay";
};

&usb_host0_ehci {
	status = "okay";
};

&usb_host0_ohci {
	status = "okay";
};

&usb_host0_xhci {
	status = "okay";
};

&usb_host1_ehci {
	status = "okay";
};

&usb_host1_ohci {
	status = "okay";
};

&usb2phy0_otg {
	phy-supply = <&vbus_typec>;
	status = "okay";
};

&usb2phy1_host {
	phy-supply = <&vcc3v3_minipcie>;
	status = "okay";
};

&usb2phy1_otg {
	phy-supply = <&vcc3v3_ngff>;
	status = "okay";
};
Commit	Line	Data
2bf2f4d9 CP	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2
	3	/dts-v1/;
	4	#include "rk3568-radxa-cm3i.dtsi"
	5
	6	/ {
ef9134d9	7	model = "Radxa E25 Carrier Board";
c4d2b02d	8	compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568";
2bf2f4d9 CP	9
2bf2f4d9 CP	10	aliases {
c80992ab	11	mmc1 = &sdmmc0;
2bf2f4d9 CP	12	};
	13
	14	pwm-leds {
	15	compatible = "pwm-leds-multicolor";
	16
	17	multi-led {
	18	color = <LED_COLOR_ID_RGB>;
	19	max-brightness = <255>;
	20
	21	led-red {
	22	color = <LED_COLOR_ID_RED>;
	23	pwms = <&pwm1 0 1000000 0>;
	24	};
	25
	26	led-green {
	27	color = <LED_COLOR_ID_GREEN>;
	28	pwms = <&pwm2 0 1000000 0>;
	29	};
	30
	31	led-blue {
	32	color = <LED_COLOR_ID_BLUE>;
	33	pwms = <&pwm12 0 1000000 0>;
	34	};
	35	};
	36	};
	37
	38	vbus_typec: vbus-typec-regulator {
	39	compatible = "regulator-fixed";
	40	enable-active-high;
	41	gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
	42	pinctrl-names = "default";
	43	pinctrl-0 = <&vbus_typec_en>;
	44	regulator-name = "vbus_typec";
	45	regulator-min-microvolt = <5000000>;
	46	regulator-max-microvolt = <5000000>;
	47	vin-supply = <&vcc5v0_sys>;
	48	};
	49
	50	vcc3v3_minipcie: vcc3v3-minipcie-regulator {
	51	compatible = "regulator-fixed";
	52	enable-active-high;
	53	gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
	54	pinctrl-names = "default";
	55	pinctrl-0 = <&minipcie_enable_h>;
	56	regulator-name = "vcc3v3_minipcie";
	57	regulator-min-microvolt = <5000000>;
	58	regulator-max-microvolt = <5000000>;
	59	vin-supply = <&vcc5v0_sys>;
	60	};
	61
	62	vcc3v3_ngff: vcc3v3-ngff-regulator {
	63	compatible = "regulator-fixed";
	64	enable-active-high;
	65	gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
	66	pinctrl-names = "default";
	67	pinctrl-0 = <&ngffpcie_enable_h>;
	68	regulator-name = "vcc3v3_ngff";
	69	regulator-min-microvolt = <3300000>;
	70	regulator-max-microvolt = <3300000>;
	71	vin-supply = <&vcc5v0_sys>;
	72	};
	73
	74	/* actually fed by vcc5v0_sys, dependent
	75	* on pi6c clock generator
76	*/
77	vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator {
78	compatible = "regulator-fixed";
79	enable-active-high;
80	gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
81	pinctrl-names = "default";
82	pinctrl-0 = <&pcie30x1_enable_h>;
83	regulator-name = "vcc3v3_pcie30x1";
84	regulator-min-microvolt = <3300000>;
85	regulator-max-microvolt = <3300000>;
86	vin-supply = <&vcc3v3_pi6c_05>;
87	};
88
89	vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
90	compatible = "regulator-fixed";
91	enable-active-high;
92	gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
93	pinctrl-names = "default";
94	pinctrl-0 = <&pcie_enable_h>;
95	regulator-name = "vcc3v3_pcie";
96	regulator-min-microvolt = <3300000>;
97	regulator-max-microvolt = <3300000>;
98	vin-supply = <&vcc5v0_sys>;
99	};
100	};
101
102	&pcie2x1 {
103	pinctrl-names = "default";
104	pinctrl-0 = <&pcie20_reset_h>;
105	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
106	vpcie3v3-supply = <&vcc3v3_pi6c_05>;
107	status = "okay";
108	};
109
110	&pcie30phy {
111	data-lanes = <1 2>;
112	status = "okay";
113	};
114
115	&pcie3x1 {
116	num-lanes = <1>;
117	pinctrl-names = "default";
118	pinctrl-0 = <&pcie30x1m0_pins>;
119	reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
120	vpcie3v3-supply = <&vcc3v3_pcie30x1>;
121	status = "okay";
122	};
123
124	&pcie3x2 {
125	num-lanes = <1>;
126	pinctrl-names = "default";
127	pinctrl-0 = <&pcie30x2_reset_h>;
128	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
129	vpcie3v3-supply = <&vcc3v3_pi6c_05>;
130	status = "okay";
131	};
132
133	&pinctrl {
134	pcie {
135	pcie20_reset_h: pcie20-reset-h {
136	rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
137	};
138
139	pcie30x1_enable_h: pcie30x1-enable-h {
140	rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
141	};
142
143	pcie30x2_reset_h: pcie30x2-reset-h {
144	rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
145	};
146
147	pcie_enable_h: pcie-enable-h {
148	rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
149	};
150	};
151
152	usb {
153	minipcie_enable_h: minipcie-enable-h {
154	rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
155	};
156
157	ngffpcie_enable_h: ngffpcie-enable-h {
158	rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
159	};
160
161	vbus_typec_en: vbus_typec_en {
162	rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
163	};
164	};
165	};
166
167	&pwm1 {
168	status = "okay";
169	};
170
171	&pwm2 {
172	status = "okay";
173	};
174
175	&pwm12 {
176	pinctrl-names = "default";
177	pinctrl-0 = <&pwm12m1_pins>;
178	status = "okay";
179	};
180
181	&sdmmc0 {
182	bus-width = <4>;
183	cap-sd-highspeed;
184	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
185	/* Also used in pcie30x1_clkreqnm0 */
186	disable-wp;
187	pinctrl-names = "default";
188	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
189	sd-uhs-sdr104;
190	vmmc-supply = <&vcc3v3_sd>;
191	vqmmc-supply = <&vccio_sd>;
192	status = "okay";
193	};
194
195	&usb_host0_ehci {
196	status = "okay";
197	};
198
199	&usb_host0_ohci {
200	status = "okay";
201	};
202
203	&usb_host0_xhci {
204	status = "okay";
205	};
206
207	&usb_host1_ehci {
208	status = "okay";
209	};
210
211	&usb_host1_ohci {
212	status = "okay";
213	};
214
215	&usb2phy0_otg {
216	phy-supply = <&vbus_typec>;
217	status = "okay";
218	};
219
220	&usb2phy1_host {
221	phy-supply = <&vcc3v3_minipcie>;
222	status = "okay";
223	};
224
225	&usb2phy1_otg {
226	phy-supply = <&vcc3v3_ngff>;
227	status = "okay";
228	};