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arm64: dts: rockchip: add usb3-phy otg-port support for rk3399
[linux-block.git] / arch / arm64 / boot / dts / rockchip / rk3399.dtsi
CommitLineData
f048b9a4
JX		 1/*
2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include <dt-bindings/clock/rk3399-cru.h>
44#include <dt-bindings/gpio/gpio.h>
45#include <dt-bindings/interrupt-controller/arm-gic.h>
46#include <dt-bindings/interrupt-controller/irq.h>
47#include <dt-bindings/pinctrl/rockchip.h>
807a2371 48#include <dt-bindings/power/rk3399-power.h>
95c27ba7 49#include <dt-bindings/thermal/thermal.h>
f048b9a4
JX		 50
51/ {
52 compatible = "rockchip,rk3399";
53
54 interrupt-parent = <&gic>;
55 #address-cells = <2>;
56 #size-cells = <2>;
57
58 aliases {
2eca8411 59 ethernet0 = &gmac;
69e5a8fe
DW		 60 i2c0 = &i2c0;
61 i2c1 = &i2c1;
62 i2c2 = &i2c2;
63 i2c3 = &i2c3;
64 i2c4 = &i2c4;
65 i2c5 = &i2c5;
66 i2c6 = &i2c6;
67 i2c7 = &i2c7;
68 i2c8 = &i2c8;
f048b9a4
JX		 69 serial0 = &uart0;
70 serial1 = &uart1;
71 serial2 = &uart2;
72 serial3 = &uart3;
73 serial4 = &uart4;
74 };
75
76 cpus {
77 #address-cells = <2>;
78 #size-cells = <0>;
79
80 cpu-map {
81 cluster0 {
82 core0 {
83 cpu = <&cpu_l0>;
84 };
85 core1 {
86 cpu = <&cpu_l1>;
87 };
88 core2 {
89 cpu = <&cpu_l2>;
90 };
91 core3 {
92 cpu = <&cpu_l3>;
93 };
94 };
95
96 cluster1 {
97 core0 {
98 cpu = <&cpu_b0>;
99 };
100 core1 {
101 cpu = <&cpu_b1>;
102 };
103 };
104 };
105
106 cpu_l0: cpu@0 {
107 device_type = "cpu";
108 compatible = "arm,cortex-a53", "arm,armv8";
109 reg = <0x0 0x0>;
110 enable-method = "psci";
111 #cooling-cells = <2>; /* min followed by max */
112 clocks = <&cru ARMCLKL>;
f4697bd7 113 dynamic-power-coefficient = <100>;
f048b9a4
JX		 114 };
115
116 cpu_l1: cpu@1 {
117 device_type = "cpu";
118 compatible = "arm,cortex-a53", "arm,armv8";
119 reg = <0x0 0x1>;
120 enable-method = "psci";
121 clocks = <&cru ARMCLKL>;
f4697bd7 122 dynamic-power-coefficient = <100>;
f048b9a4
JX		 123 };
124
125 cpu_l2: cpu@2 {
126 device_type = "cpu";
127 compatible = "arm,cortex-a53", "arm,armv8";
128 reg = <0x0 0x2>;
129 enable-method = "psci";
130 clocks = <&cru ARMCLKL>;
f4697bd7 131 dynamic-power-coefficient = <100>;
f048b9a4
JX		 132 };
133
134 cpu_l3: cpu@3 {
135 device_type = "cpu";
136 compatible = "arm,cortex-a53", "arm,armv8";
137 reg = <0x0 0x3>;
138 enable-method = "psci";
139 clocks = <&cru ARMCLKL>;
f4697bd7 140 dynamic-power-coefficient = <100>;
f048b9a4
JX		 141 };
142
143 cpu_b0: cpu@100 {
144 device_type = "cpu";
145 compatible = "arm,cortex-a72", "arm,armv8";
146 reg = <0x0 0x100>;
147 enable-method = "psci";
148 #cooling-cells = <2>; /* min followed by max */
149 clocks = <&cru ARMCLKB>;
45a995c0 150 dynamic-power-coefficient = <436>;
f048b9a4
JX		 151 };
152
153 cpu_b1: cpu@101 {
154 device_type = "cpu";
155 compatible = "arm,cortex-a72", "arm,armv8";
156 reg = <0x0 0x101>;
157 enable-method = "psci";
158 clocks = <&cru ARMCLKB>;
45a995c0 159 dynamic-power-coefficient = <436>;
f048b9a4
JX		 160 };
161 };
162
fbd4cc0e
MY		 163 display-subsystem {
164 compatible = "rockchip,display-subsystem";
165 ports = <&vopl_out>, <&vopb_out>;
166 };
167
6840eb0d
CW		 168 pmu_a53 {
169 compatible = "arm,cortex-a53-pmu";
170 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
171 };
172
173 pmu_a72 {
174 compatible = "arm,cortex-a72-pmu";
175 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
176 };
177
f048b9a4
JX		 178 psci {
179 compatible = "arm,psci-1.0";
180 method = "smc";
181 };
182
183 timer {
184 compatible = "arm,armv8-timer";
210bbd38
CW		 185 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
186 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
187 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
188 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
e6186820 189 arm,no-tick-in-suspend;
f048b9a4
JX		 190 };
191
192 xin24m: xin24m {
193 compatible = "fixed-clock";
194 clock-frequency = <24000000>;
195 clock-output-names = "xin24m";
196 #clock-cells = <0>;
197 };
198
199 amba {
15b7cc78 200 compatible = "simple-bus";
f048b9a4
JX		 201 #address-cells = <2>;
202 #size-cells = <2>;
203 ranges;
204
205 dmac_bus: dma-controller@ff6d0000 {
206 compatible = "arm,pl330", "arm,primecell";
207 reg = <0x0 0xff6d0000 0x0 0x4000>;
210bbd38
CW		 208 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
209 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 210 #dma-cells = <1>;
211 clocks = <&cru ACLK_DMAC0_PERILP>;
212 clock-names = "apb_pclk";
213 };
214
215 dmac_peri: dma-controller@ff6e0000 {
216 compatible = "arm,pl330", "arm,primecell";
217 reg = <0x0 0xff6e0000 0x0 0x4000>;
210bbd38
CW		 218 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
219 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 220 #dma-cells = <1>;
221 clocks = <&cru ACLK_DMAC1_PERILP>;
222 clock-names = "apb_pclk";
223 };
224 };
225
66aef3cb
BN		 226 pcie0: pcie@f8000000 {
227 compatible = "rockchip,rk3399-pcie";
228 reg = <0x0 0xf8000000 0x0 0x2000000>,
229 <0x0 0xfd000000 0x0 0x1000000>;
230 reg-names = "axi-base", "apb-base";
231 #address-cells = <3>;
232 #size-cells = <2>;
233 #interrupt-cells = <1>;
234 aspm-no-l0s;
d633becc 235 bus-range = <0x0 0x1f>;
66aef3cb
BN		 236 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
237 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
238 clock-names = "aclk", "aclk-perf",
239 "hclk", "pm";
240 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
241 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
242 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
243 interrupt-names = "sys", "legacy", "client";
244 interrupt-map-mask = <0 0 0 7>;
245 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
246 <0 0 0 2 &pcie0_intc 1>,
247 <0 0 0 3 &pcie0_intc 2>,
248 <0 0 0 4 &pcie0_intc 3>;
41b464ef 249 linux,pci-domain = <0>;
66aef3cb
BN		 250 max-link-speed = <1>;
251 msi-map = <0x0 &its 0x0 0x1000>;
e9a60cac
SL		 252 phys = <&pcie_phy 0>, <&pcie_phy 1>,
253 <&pcie_phy 2>, <&pcie_phy 3>;
254 phy-names = "pcie-phy-0", "pcie-phy-1",
255 "pcie-phy-2", "pcie-phy-3";
81f66606
SL		 256 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
257 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
66aef3cb
BN		 258 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
259 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
260 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
261 <&cru SRST_A_PCIE>;
262 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
263 "pm", "pclk", "aclk";
264 status = "disabled";
265
266 pcie0_intc: interrupt-controller {
267 interrupt-controller;
268 #address-cells = <0>;
269 #interrupt-cells = <1>;
270 };
271 };
272
eb3a6a6a
RC		 273 gmac: ethernet@fe300000 {
274 compatible = "rockchip,rk3399-gmac";
275 reg = <0x0 0xfe300000 0x0 0x10000>;
276 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
277 interrupt-names = "macirq";
278 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
279 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
280 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
281 <&cru PCLK_GMAC>;
282 clock-names = "stmmaceth", "mac_clk_rx",
283 "mac_clk_tx", "clk_mac_ref",
284 "clk_mac_refout", "aclk_mac",
285 "pclk_mac";
286 power-domains = <&power RK3399_PD_GMAC>;
287 resets = <&cru SRST_A_GMAC>;
288 reset-names = "stmmaceth";
289 rockchip,grf = <&grf>;
290 status = "disabled";
291 };
292
f048b9a4
JX		 293 sdio0: dwmmc@fe310000 {
294 compatible = "rockchip,rk3399-dw-mshc",
295 "rockchip,rk3288-dw-mshc";
296 reg = <0x0 0xfe310000 0x0 0x4000>;
210bbd38 297 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
c4959069 298 max-frequency = <150000000>;
f048b9a4
JX		 299 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
300 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
301 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
302 fifo-depth = <0x100>;
b0f2110a 303 power-domains = <&power RK3399_PD_SDIOAUDIO>;
04dc7f62
HS		 304 resets = <&cru SRST_SDIO0>;
305 reset-names = "reset";
f048b9a4
JX		 306 status = "disabled";
307 };
308
309 sdmmc: dwmmc@fe320000 {
310 compatible = "rockchip,rk3399-dw-mshc",
311 "rockchip,rk3288-dw-mshc";
312 reg = <0x0 0xfe320000 0x0 0x4000>;
210bbd38 313 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
c4959069 314 max-frequency = <150000000>;
e702e13f
LH		 315 assigned-clocks = <&cru HCLK_SD>;
316 assigned-clock-rates = <200000000>;
f048b9a4
JX		 317 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
318 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
319 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
320 fifo-depth = <0x100>;
1bc60bee 321 power-domains = <&power RK3399_PD_SD>;
04dc7f62
HS		 322 resets = <&cru SRST_SDMMC>;
323 reset-names = "reset";
f048b9a4
JX		 324 status = "disabled";
325 };
326
b4e87c09
BN		 327 sdhci: sdhci@fe330000 {
328 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
329 reg = <0x0 0xfe330000 0x0 0x10000>;
210bbd38 330 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
64e3481c 331 arasan,soc-ctl-syscon = <&grf>;
b4e87c09
BN		 332 assigned-clocks = <&cru SCLK_EMMC>;
333 assigned-clock-rates = <200000000>;
334 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
335 clock-names = "clk_xin", "clk_ahb";
ed388cdd
DA		 336 clock-output-names = "emmc_cardclock";
337 #clock-cells = <0>;
b4e87c09
BN		 338 phys = <&emmc_phy>;
339 phy-names = "phy_arasan";
a1907df2 340 power-domains = <&power RK3399_PD_EMMC>;
b4e87c09
BN		 341 status = "disabled";
342 };
343
f048b9a4
JX		 344 usb_host0_ehci: usb@fe380000 {
345 compatible = "generic-ehci";
346 reg = <0x0 0xfe380000 0x0 0x20000>;
210bbd38 347 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
b5d1c572
W		 348 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
349 <&u2phy0>;
350 clock-names = "usbhost", "arbiter",
351 "utmi";
103e9f85
FW		 352 phys = <&u2phy0_host>;
353 phy-names = "usb";
f048b9a4
JX		 354 status = "disabled";
355 };
356
357 usb_host0_ohci: usb@fe3a0000 {
358 compatible = "generic-ohci";
359 reg = <0x0 0xfe3a0000 0x0 0x20000>;
210bbd38 360 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
b5d1c572
W		 361 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
362 <&u2phy0>;
363 clock-names = "usbhost", "arbiter",
364 "utmi";
365 phys = <&u2phy0_host>;
366 phy-names = "usb";
f048b9a4
JX		 367 status = "disabled";
368 };
369
370 usb_host1_ehci: usb@fe3c0000 {
371 compatible = "generic-ehci";
372 reg = <0x0 0xfe3c0000 0x0 0x20000>;
210bbd38 373 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
b5d1c572
W		 374 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
375 <&u2phy1>;
376 clock-names = "usbhost", "arbiter",
377 "utmi";
103e9f85
FW		 378 phys = <&u2phy1_host>;
379 phy-names = "usb";
f048b9a4
JX		 380 status = "disabled";
381 };
382
383 usb_host1_ohci: usb@fe3e0000 {
384 compatible = "generic-ohci";
385 reg = <0x0 0xfe3e0000 0x0 0x20000>;
210bbd38 386 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
b5d1c572
W		 387 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
388 <&u2phy1>;
389 clock-names = "usbhost", "arbiter",
390 "utmi";
391 phys = <&u2phy1_host>;
392 phy-names = "usb";
f048b9a4
JX		 393 status = "disabled";
394 };
395
7144224f
BN		 396 usbdrd3_0: usb@fe800000 {
397 compatible = "rockchip,rk3399-dwc3";
398 #address-cells = <2>;
399 #size-cells = <2>;
400 ranges;
401 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
9df8a2d9
EBS		 402 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
403 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
7144224f 404 clock-names = "ref_clk", "suspend_clk",
9df8a2d9
EBS		 405 "bus_clk", "aclk_usb3_rksoc_axi_perf",
406 "aclk_usb3", "grf_clk";
b7e63d95
EBS		 407 resets = <&cru SRST_A_USB3_OTG0>;
408 reset-names = "usb3-otg";
7144224f
BN		 409 status = "disabled";
410
411 usbdrd_dwc3_0: dwc3 {
412 compatible = "snps,dwc3";
413 reg = <0x0 0xfe800000 0x0 0x100000>;
414 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
415 dr_mode = "otg";
bfdca173
EBS		 416 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
417 phy-names = "usb2-phy", "usb3-phy";
7144224f
BN		 418 phy_type = "utmi_wide";
419 snps,dis_enblslpm_quirk;
420 snps,dis-u2-freeclk-exists-quirk;
421 snps,dis_u2_susphy_quirk;
422 snps,dis-del-phy-power-chg-quirk;
1d5bcbbd 423 snps,dis-tx-ipgap-linecheck-quirk;
a1bbaaa4 424 power-domains = <&power RK3399_PD_USB3>;
7144224f
BN		 425 status = "disabled";
426 };
427 };
428
429 usbdrd3_1: usb@fe900000 {
430 compatible = "rockchip,rk3399-dwc3";
431 #address-cells = <2>;
432 #size-cells = <2>;
433 ranges;
434 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
9df8a2d9
EBS		 435 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
436 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
7144224f 437 clock-names = "ref_clk", "suspend_clk",
9df8a2d9
EBS		 438 "bus_clk", "aclk_usb3_rksoc_axi_perf",
439 "aclk_usb3", "grf_clk";
b7e63d95
EBS		 440 resets = <&cru SRST_A_USB3_OTG1>;
441 reset-names = "usb3-otg";
7144224f
BN		 442 status = "disabled";
443
444 usbdrd_dwc3_1: dwc3 {
445 compatible = "snps,dwc3";
446 reg = <0x0 0xfe900000 0x0 0x100000>;
447 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
448 dr_mode = "otg";
bfdca173
EBS		 449 phys = <&u2phy1_otg>, <&tcphy1_usb3>;
450 phy-names = "usb2-phy", "usb3-phy";
7144224f
BN		 451 phy_type = "utmi_wide";
452 snps,dis_enblslpm_quirk;
453 snps,dis-u2-freeclk-exists-quirk;
454 snps,dis_u2_susphy_quirk;
455 snps,dis-del-phy-power-chg-quirk;
1d5bcbbd 456 snps,dis-tx-ipgap-linecheck-quirk;
a1bbaaa4 457 power-domains = <&power RK3399_PD_USB3>;
7144224f
BN		 458 status = "disabled";
459 };
460 };
461
2d3c2d56
CZ		 462 cdn_dp: dp@fec00000 {
463 compatible = "rockchip,rk3399-cdn-dp";
464 reg = <0x0 0xfec00000 0x0 0x100000>;
465 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
e702e13f
LH		 466 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
467 assigned-clock-rates = <100000000>, <200000000>;
2d3c2d56
CZ		 468 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
469 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
470 clock-names = "core-clk", "pclk", "spdif", "grf";
471 phys = <&tcphy0_dp>, <&tcphy1_dp>;
472 power-domains = <&power RK3399_PD_HDCP>;
473 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
474 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
475 reset-names = "spdif", "dptx", "apb", "core";
476 rockchip,grf = <&grf>;
477 #sound-dai-cells = <1>;
478 status = "disabled";
479
480 ports {
481 dp_in: port {
482 #address-cells = <1>;
483 #size-cells = <0>;
484
485 dp_in_vopb: endpoint@0 {
486 reg = <0>;
487 remote-endpoint = <&vopb_out_dp>;
488 };
489
490 dp_in_vopl: endpoint@1 {
491 reg = <1>;
492 remote-endpoint = <&vopl_out_dp>;
493 };
494 };
495 };
496 };
497
f048b9a4
JX		 498 gic: interrupt-controller@fee00000 {
499 compatible = "arm,gic-v3";
210bbd38 500 #interrupt-cells = <4>;
f048b9a4
JX		 501 #address-cells = <2>;
502 #size-cells = <2>;
503 ranges;
504 interrupt-controller;
505
506 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
507 <0x0 0xfef00000 0 0xc0000>, /* GICR */
508 <0x0 0xfff00000 0 0x10000>, /* GICC */
509 <0x0 0xfff10000 0 0x10000>, /* GICH */
510 <0x0 0xfff20000 0 0x10000>; /* GICV */
210bbd38 511 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 512 its: interrupt-controller@fee20000 {
513 compatible = "arm,gic-v3-its";
514 msi-controller;
515 reg = <0x0 0xfee20000 0x0 0x20000>;
516 };
6840eb0d
CW		 517
518 ppi-partitions {
519 ppi_cluster0: interrupt-partition-0 {
520 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
521 };
522
523 ppi_cluster1: interrupt-partition-1 {
524 affinity = <&cpu_b0 &cpu_b1>;
525 };
526 };
f048b9a4
JX		 527 };
528
fe996215
CW		 529 saradc: saradc@ff100000 {
530 compatible = "rockchip,rk3399-saradc";
531 reg = <0x0 0xff100000 0x0 0x100>;
210bbd38 532 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
fe996215
CW		 533 #io-channel-cells = <1>;
534 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
535 clock-names = "saradc", "apb_pclk";
536 resets = <&cru SRST_P_SARADC>;
537 reset-names = "saradc-apb";
538 status = "disabled";
539 };
540
69e5a8fe
DW		 541 i2c1: i2c@ff110000 {
542 compatible = "rockchip,rk3399-i2c";
543 reg = <0x0 0xff110000 0x0 0x1000>;
544 assigned-clocks = <&cru SCLK_I2C1>;
545 assigned-clock-rates = <200000000>;
546 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
547 clock-names = "i2c", "pclk";
210bbd38 548 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 549 pinctrl-names = "default";
550 pinctrl-0 = <&i2c1_xfer>;
551 #address-cells = <1>;
552 #size-cells = <0>;
553 status = "disabled";
554 };
555
556 i2c2: i2c@ff120000 {
557 compatible = "rockchip,rk3399-i2c";
558 reg = <0x0 0xff120000 0x0 0x1000>;
559 assigned-clocks = <&cru SCLK_I2C2>;
560 assigned-clock-rates = <200000000>;
561 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
562 clock-names = "i2c", "pclk";
210bbd38 563 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 564 pinctrl-names = "default";
565 pinctrl-0 = <&i2c2_xfer>;
566 #address-cells = <1>;
567 #size-cells = <0>;
568 status = "disabled";
569 };
570
571 i2c3: i2c@ff130000 {
572 compatible = "rockchip,rk3399-i2c";
573 reg = <0x0 0xff130000 0x0 0x1000>;
574 assigned-clocks = <&cru SCLK_I2C3>;
575 assigned-clock-rates = <200000000>;
576 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
577 clock-names = "i2c", "pclk";
210bbd38 578 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 579 pinctrl-names = "default";
580 pinctrl-0 = <&i2c3_xfer>;
581 #address-cells = <1>;
582 #size-cells = <0>;
583 status = "disabled";
584 };
585
586 i2c5: i2c@ff140000 {
587 compatible = "rockchip,rk3399-i2c";
588 reg = <0x0 0xff140000 0x0 0x1000>;
589 assigned-clocks = <&cru SCLK_I2C5>;
590 assigned-clock-rates = <200000000>;
591 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
592 clock-names = "i2c", "pclk";
210bbd38 593 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 594 pinctrl-names = "default";
595 pinctrl-0 = <&i2c5_xfer>;
596 #address-cells = <1>;
597 #size-cells = <0>;
598 status = "disabled";
599 };
600
601 i2c6: i2c@ff150000 {
602 compatible = "rockchip,rk3399-i2c";
603 reg = <0x0 0xff150000 0x0 0x1000>;
604 assigned-clocks = <&cru SCLK_I2C6>;
605 assigned-clock-rates = <200000000>;
606 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
607 clock-names = "i2c", "pclk";
210bbd38 608 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 609 pinctrl-names = "default";
610 pinctrl-0 = <&i2c6_xfer>;
611 #address-cells = <1>;
612 #size-cells = <0>;
613 status = "disabled";
614 };
615
616 i2c7: i2c@ff160000 {
617 compatible = "rockchip,rk3399-i2c";
618 reg = <0x0 0xff160000 0x0 0x1000>;
619 assigned-clocks = <&cru SCLK_I2C7>;
620 assigned-clock-rates = <200000000>;
621 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
622 clock-names = "i2c", "pclk";
210bbd38 623 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 624 pinctrl-names = "default";
625 pinctrl-0 = <&i2c7_xfer>;
626 #address-cells = <1>;
627 #size-cells = <0>;
628 status = "disabled";
629 };
630
f048b9a4
JX		 631 uart0: serial@ff180000 {
632 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
633 reg = <0x0 0xff180000 0x0 0x100>;
634 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
635 clock-names = "baudclk", "apb_pclk";
210bbd38 636 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 637 reg-shift = <2>;
638 reg-io-width = <4>;
639 pinctrl-names = "default";
640 pinctrl-0 = <&uart0_xfer>;
641 status = "disabled";
642 };
643
644 uart1: serial@ff190000 {
645 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
646 reg = <0x0 0xff190000 0x0 0x100>;
647 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
648 clock-names = "baudclk", "apb_pclk";
210bbd38 649 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 650 reg-shift = <2>;
651 reg-io-width = <4>;
652 pinctrl-names = "default";
653 pinctrl-0 = <&uart1_xfer>;
654 status = "disabled";
655 };
656
657 uart2: serial@ff1a0000 {
658 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
659 reg = <0x0 0xff1a0000 0x0 0x100>;
660 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
661 clock-names = "baudclk", "apb_pclk";
210bbd38 662 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 663 reg-shift = <2>;
664 reg-io-width = <4>;
665 pinctrl-names = "default";
666 pinctrl-0 = <&uart2c_xfer>;
667 status = "disabled";
668 };
669
670 uart3: serial@ff1b0000 {
671 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
672 reg = <0x0 0xff1b0000 0x0 0x100>;
673 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
674 clock-names = "baudclk", "apb_pclk";
210bbd38 675 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 676 reg-shift = <2>;
677 reg-io-width = <4>;
678 pinctrl-names = "default";
679 pinctrl-0 = <&uart3_xfer>;
680 status = "disabled";
681 };
682
683 spi0: spi@ff1c0000 {
684 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
685 reg = <0x0 0xff1c0000 0x0 0x1000>;
686 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
687 clock-names = "spiclk", "apb_pclk";
210bbd38 688 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 689 pinctrl-names = "default";
690 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
691 #address-cells = <1>;
692 #size-cells = <0>;
693 status = "disabled";
694 };
695
696 spi1: spi@ff1d0000 {
697 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
698 reg = <0x0 0xff1d0000 0x0 0x1000>;
699 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
700 clock-names = "spiclk", "apb_pclk";
210bbd38 701 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 702 pinctrl-names = "default";
703 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
704 #address-cells = <1>;
705 #size-cells = <0>;
706 status = "disabled";
707 };
708
709 spi2: spi@ff1e0000 {
710 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
711 reg = <0x0 0xff1e0000 0x0 0x1000>;
712 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
713 clock-names = "spiclk", "apb_pclk";
210bbd38 714 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 715 pinctrl-names = "default";
716 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
717 #address-cells = <1>;
718 #size-cells = <0>;
719 status = "disabled";
720 };
721
722 spi4: spi@ff1f0000 {
723 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
724 reg = <0x0 0xff1f0000 0x0 0x1000>;
725 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
726 clock-names = "spiclk", "apb_pclk";
210bbd38 727 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 728 pinctrl-names = "default";
729 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
730 #address-cells = <1>;
731 #size-cells = <0>;
732 status = "disabled";
733 };
734
735 spi5: spi@ff200000 {
736 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
737 reg = <0x0 0xff200000 0x0 0x1000>;
738 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
739 clock-names = "spiclk", "apb_pclk";
210bbd38 740 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 741 pinctrl-names = "default";
742 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
b0f2110a 743 power-domains = <&power RK3399_PD_SDIOAUDIO>;
f048b9a4
JX		 744 #address-cells = <1>;
745 #size-cells = <0>;
746 status = "disabled";
747 };
748
647cea2e 749 thermal_zones: thermal-zones {
95c27ba7
CW		 750 cpu_thermal: cpu {
751 polling-delay-passive = <100>;
752 polling-delay = <1000>;
753
754 thermal-sensors = <&tsadc 0>;
755
756 trips {
757 cpu_alert0: cpu_alert0 {
758 temperature = <70000>;
759 hysteresis = <2000>;
760 type = "passive";
761 };
762 cpu_alert1: cpu_alert1 {
763 temperature = <75000>;
764 hysteresis = <2000>;
765 type = "passive";
766 };
767 cpu_crit: cpu_crit {
768 temperature = <95000>;
769 hysteresis = <2000>;
770 type = "critical";
771 };
772 };
773
774 cooling-maps {
775 map0 {
776 trip = <&cpu_alert0>;
777 cooling-device =
778 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
779 };
780 map1 {
781 trip = <&cpu_alert1>;
782 cooling-device =
783 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
784 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
785 };
786 };
787 };
788
789 gpu_thermal: gpu {
790 polling-delay-passive = <100>;
791 polling-delay = <1000>;
792
793 thermal-sensors = <&tsadc 1>;
794
795 trips {
796 gpu_alert0: gpu_alert0 {
797 temperature = <75000>;
798 hysteresis = <2000>;
799 type = "passive";
800 };
801 gpu_crit: gpu_crit {
802 temperature = <95000>;
803 hysteresis = <2000>;
804 type = "critical";
805 };
806 };
807
808 cooling-maps {
809 map0 {
810 trip = <&gpu_alert0>;
811 cooling-device =
812 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
813 };
814 };
815 };
816 };
817
818 tsadc: tsadc@ff260000 {
819 compatible = "rockchip,rk3399-tsadc";
820 reg = <0x0 0xff260000 0x0 0x100>;
210bbd38 821 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
95c27ba7
CW		 822 assigned-clocks = <&cru SCLK_TSADC>;
823 assigned-clock-rates = <750000>;
824 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
825 clock-names = "tsadc", "apb_pclk";
826 resets = <&cru SRST_TSADC>;
827 reset-names = "tsadc-apb";
828 rockchip,grf = <&grf>;
829 rockchip,hw-tshut-temp = <95000>;
830 pinctrl-names = "init", "default", "sleep";
831 pinctrl-0 = <&otp_gpio>;
832 pinctrl-1 = <&otp_out>;
833 pinctrl-2 = <&otp_gpio>;
834 #thermal-sensor-cells = <1>;
835 status = "disabled";
836 };
837
a1907df2
EZ		 838 qos_emmc: qos@ffa58000 {
839 compatible = "syscon";
840 reg = <0x0 0xffa58000 0x0 0x20>;
841 };
842
d43c97a5
CW		 843 qos_gmac: qos@ffa5c000 {
844 compatible = "syscon";
845 reg = <0x0 0xffa5c000 0x0 0x20>;
846 };
847
65f1e902
KY		 848 qos_pcie: qos@ffa60080 {
849 compatible = "syscon";
850 reg = <0x0 0xffa60080 0x0 0x20>;
851 };
852
853 qos_usb_host0: qos@ffa60100 {
854 compatible = "syscon";
855 reg = <0x0 0xffa60100 0x0 0x20>;
856 };
857
858 qos_usb_host1: qos@ffa60180 {
859 compatible = "syscon";
860 reg = <0x0 0xffa60180 0x0 0x20>;
861 };
862
863 qos_usb_otg0: qos@ffa70000 {
864 compatible = "syscon";
865 reg = <0x0 0xffa70000 0x0 0x20>;
866 };
867
868 qos_usb_otg1: qos@ffa70080 {
869 compatible = "syscon";
870 reg = <0x0 0xffa70080 0x0 0x20>;
871 };
872
873 qos_sd: qos@ffa74000 {
874 compatible = "syscon";
875 reg = <0x0 0xffa74000 0x0 0x20>;
876 };
877
878 qos_sdioaudio: qos@ffa76000 {
879 compatible = "syscon";
880 reg = <0x0 0xffa76000 0x0 0x20>;
881 };
882
807a2371
EZ		 883 qos_hdcp: qos@ffa90000 {
884 compatible = "syscon";
885 reg = <0x0 0xffa90000 0x0 0x20>;
886 };
887
888 qos_iep: qos@ffa98000 {
889 compatible = "syscon";
890 reg = <0x0 0xffa98000 0x0 0x20>;
891 };
892
893 qos_isp0_m0: qos@ffaa0000 {
894 compatible = "syscon";
895 reg = <0x0 0xffaa0000 0x0 0x20>;
896 };
897
898 qos_isp0_m1: qos@ffaa0080 {
899 compatible = "syscon";
900 reg = <0x0 0xffaa0080 0x0 0x20>;
901 };
902
903 qos_isp1_m0: qos@ffaa8000 {
904 compatible = "syscon";
905 reg = <0x0 0xffaa8000 0x0 0x20>;
906 };
907
908 qos_isp1_m1: qos@ffaa8080 {
909 compatible = "syscon";
910 reg = <0x0 0xffaa8080 0x0 0x20>;
911 };
912
913 qos_rga_r: qos@ffab0000 {
914 compatible = "syscon";
915 reg = <0x0 0xffab0000 0x0 0x20>;
916 };
917
918 qos_rga_w: qos@ffab0080 {
919 compatible = "syscon";
920 reg = <0x0 0xffab0080 0x0 0x20>;
921 };
922
923 qos_video_m0: qos@ffab8000 {
924 compatible = "syscon";
925 reg = <0x0 0xffab8000 0x0 0x20>;
926 };
927
928 qos_video_m1_r: qos@ffac0000 {
929 compatible = "syscon";
930 reg = <0x0 0xffac0000 0x0 0x20>;
931 };
932
933 qos_video_m1_w: qos@ffac0080 {
934 compatible = "syscon";
935 reg = <0x0 0xffac0080 0x0 0x20>;
936 };
937
938 qos_vop_big_r: qos@ffac8000 {
939 compatible = "syscon";
940 reg = <0x0 0xffac8000 0x0 0x20>;
941 };
942
943 qos_vop_big_w: qos@ffac8080 {
944 compatible = "syscon";
945 reg = <0x0 0xffac8080 0x0 0x20>;
946 };
947
948 qos_vop_little: qos@ffad0000 {
949 compatible = "syscon";
950 reg = <0x0 0xffad0000 0x0 0x20>;
951 };
952
65f1e902
KY		 953 qos_perihp: qos@ffad8080 {
954 compatible = "syscon";
955 reg = <0x0 0xffad8080 0x0 0x20>;
956 };
957
807a2371
EZ		 958 qos_gpu: qos@ffae0000 {
959 compatible = "syscon";
960 reg = <0x0 0xffae0000 0x0 0x20>;
961 };
962
963 pmu: power-management@ff310000 {
964 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
965 reg = <0x0 0xff310000 0x0 0x1000>;
966
967 /*
968 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
969 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
970 * Some of the power domains are grouped together for every
971 * voltage domain.
972 * The detail contents as below.
973 */
974 power: power-controller {
975 compatible = "rockchip,rk3399-power-controller";
976 #power-domain-cells = <1>;
977 #address-cells = <1>;
978 #size-cells = <0>;
979
980 /* These power domains are grouped by VD_CENTER */
981 pd_iep@RK3399_PD_IEP {
982 reg = <RK3399_PD_IEP>;
983 clocks = <&cru ACLK_IEP>,
984 <&cru HCLK_IEP>;
985 pm_qos = <&qos_iep>;
986 };
987 pd_rga@RK3399_PD_RGA {
988 reg = <RK3399_PD_RGA>;
989 clocks = <&cru ACLK_RGA>,
990 <&cru HCLK_RGA>;
991 pm_qos = <&qos_rga_r>,
992 <&qos_rga_w>;
993 };
994 pd_vcodec@RK3399_PD_VCODEC {
995 reg = <RK3399_PD_VCODEC>;
996 clocks = <&cru ACLK_VCODEC>,
997 <&cru HCLK_VCODEC>;
998 pm_qos = <&qos_video_m0>;
999 };
1000 pd_vdu@RK3399_PD_VDU {
1001 reg = <RK3399_PD_VDU>;
1002 clocks = <&cru ACLK_VDU>,
1003 <&cru HCLK_VDU>;
1004 pm_qos = <&qos_video_m1_r>,
1005 <&qos_video_m1_w>;
1006 };
1007
1008 /* These power domains are grouped by VD_GPU */
1009 pd_gpu@RK3399_PD_GPU {
1010 reg = <RK3399_PD_GPU>;
1011 clocks = <&cru ACLK_GPU>;
1012 pm_qos = <&qos_gpu>;
1013 };
1014
1015 /* These power domains are grouped by VD_LOGIC */
3cf04a4e
EZ		 1016 pd_edp@RK3399_PD_EDP {
1017 reg = <RK3399_PD_EDP>;
1018 clocks = <&cru PCLK_EDP_CTRL>;
1019 };
a1907df2
EZ		 1020 pd_emmc@RK3399_PD_EMMC {
1021 reg = <RK3399_PD_EMMC>;
1022 clocks = <&cru ACLK_EMMC>;
1023 pm_qos = <&qos_emmc>;
1024 };
d43c97a5
CW		 1025 pd_gmac@RK3399_PD_GMAC {
1026 reg = <RK3399_PD_GMAC>;
2afc1db0
JC		 1027 clocks = <&cru ACLK_GMAC>,
1028 <&cru PCLK_GMAC>;
d43c97a5
CW		 1029 pm_qos = <&qos_gmac>;
1030 };
1bc60bee
EZ		 1031 pd_sd@RK3399_PD_SD {
1032 reg = <RK3399_PD_SD>;
1033 clocks = <&cru HCLK_SDMMC>,
1034 <&cru SCLK_SDMMC>;
1035 pm_qos = <&qos_sd>;
1036 };
b0f2110a
CW		 1037 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1038 reg = <RK3399_PD_SDIOAUDIO>;
1039 clocks = <&cru HCLK_SDIO>;
1040 pm_qos = <&qos_sdioaudio>;
1041 };
a1bbaaa4
EBS		 1042 pd_usb3@RK3399_PD_USB3 {
1043 reg = <RK3399_PD_USB3>;
1044 clocks = <&cru ACLK_USB3>;
1045 pm_qos = <&qos_usb_otg0>,
1046 <&qos_usb_otg1>;
1047 };
807a2371
EZ		 1048 pd_vio@RK3399_PD_VIO {
1049 reg = <RK3399_PD_VIO>;
1050 #address-cells = <1>;
1051 #size-cells = <0>;
1052
1053 pd_hdcp@RK3399_PD_HDCP {
1054 reg = <RK3399_PD_HDCP>;
1055 clocks = <&cru ACLK_HDCP>,
1056 <&cru HCLK_HDCP>,
1057 <&cru PCLK_HDCP>;
1058 pm_qos = <&qos_hdcp>;
1059 };
1060 pd_isp0@RK3399_PD_ISP0 {
1061 reg = <RK3399_PD_ISP0>;
1062 clocks = <&cru ACLK_ISP0>,
1063 <&cru HCLK_ISP0>;
1064 pm_qos = <&qos_isp0_m0>,
1065 <&qos_isp0_m1>;
1066 };
1067 pd_isp1@RK3399_PD_ISP1 {
1068 reg = <RK3399_PD_ISP1>;
1069 clocks = <&cru ACLK_ISP1>,
1070 <&cru HCLK_ISP1>;
1071 pm_qos = <&qos_isp1_m0>,
1072 <&qos_isp1_m1>;
1073 };
4a3a3d32
CW		 1074 pd_tcpc0@RK3399_PD_TCPC0 {
1075 reg = <RK3399_PD_TCPD0>;
1076 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1077 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1078 };
1079 pd_tcpc1@RK3399_PD_TCPC1 {
1080 reg = <RK3399_PD_TCPD1>;
1081 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1082 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1083 };
807a2371
EZ		 1084 pd_vo@RK3399_PD_VO {
1085 reg = <RK3399_PD_VO>;
1086 #address-cells = <1>;
1087 #size-cells = <0>;
1088
1089 pd_vopb@RK3399_PD_VOPB {
1090 reg = <RK3399_PD_VOPB>;
1091 clocks = <&cru ACLK_VOP0>,
1092 <&cru HCLK_VOP0>;
1093 pm_qos = <&qos_vop_big_r>,
1094 <&qos_vop_big_w>;
1095 };
1096 pd_vopl@RK3399_PD_VOPL {
1097 reg = <RK3399_PD_VOPL>;
1098 clocks = <&cru ACLK_VOP1>,
1099 <&cru HCLK_VOP1>;
1100 pm_qos = <&qos_vop_little>;
1101 };
1102 };
1103 };
1104 };
1105 };
1106
f048b9a4 1107 pmugrf: syscon@ff320000 {
16759262 1108 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
f048b9a4 1109 reg = <0x0 0xff320000 0x0 0x1000>;
16759262
BN		 1110 #address-cells = <1>;
1111 #size-cells = <1>;
6d0e3a45
HS		 1112
1113 pmu_io_domains: io-domains {
1114 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1115 status = "disabled";
1116 };
f048b9a4
JX		 1117 };
1118
1119 spi3: spi@ff350000 {
1120 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1121 reg = <0x0 0xff350000 0x0 0x1000>;
1122 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1123 clock-names = "spiclk", "apb_pclk";
210bbd38 1124 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1125 pinctrl-names = "default";
1126 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1127 #address-cells = <1>;
1128 #size-cells = <0>;
1129 status = "disabled";
1130 };
1131
1132 uart4: serial@ff370000 {
1133 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1134 reg = <0x0 0xff370000 0x0 0x100>;
1135 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1136 clock-names = "baudclk", "apb_pclk";
210bbd38 1137 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1138 reg-shift = <2>;
1139 reg-io-width = <4>;
1140 pinctrl-names = "default";
1141 pinctrl-0 = <&uart4_xfer>;
1142 status = "disabled";
1143 };
1144
69e5a8fe
DW		 1145 i2c0: i2c@ff3c0000 {
1146 compatible = "rockchip,rk3399-i2c";
1147 reg = <0x0 0xff3c0000 0x0 0x1000>;
1148 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1149 assigned-clock-rates = <200000000>;
1150 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1151 clock-names = "i2c", "pclk";
210bbd38 1152 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 1153 pinctrl-names = "default";
1154 pinctrl-0 = <&i2c0_xfer>;
1155 #address-cells = <1>;
1156 #size-cells = <0>;
1157 status = "disabled";
1158 };
1159
1160 i2c4: i2c@ff3d0000 {
1161 compatible = "rockchip,rk3399-i2c";
1162 reg = <0x0 0xff3d0000 0x0 0x1000>;
1163 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1164 assigned-clock-rates = <200000000>;
1165 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1166 clock-names = "i2c", "pclk";
210bbd38 1167 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 1168 pinctrl-names = "default";
1169 pinctrl-0 = <&i2c4_xfer>;
1170 #address-cells = <1>;
1171 #size-cells = <0>;
1172 status = "disabled";
1173 };
1174
1175 i2c8: i2c@ff3e0000 {
1176 compatible = "rockchip,rk3399-i2c";
1177 reg = <0x0 0xff3e0000 0x0 0x1000>;
1178 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1179 assigned-clock-rates = <200000000>;
1180 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1181 clock-names = "i2c", "pclk";
210bbd38 1182 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
69e5a8fe
DW		 1183 pinctrl-names = "default";
1184 pinctrl-0 = <&i2c8_xfer>;
1185 #address-cells = <1>;
1186 #size-cells = <0>;
1187 status = "disabled";
f048b9a4
JX		 1188 };
1189
1190 pwm0: pwm@ff420000 {
1191 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1192 reg = <0x0 0xff420000 0x0 0x10>;
1193 #pwm-cells = <3>;
1194 pinctrl-names = "default";
1195 pinctrl-0 = <&pwm0_pin>;
1196 clocks = <&pmucru PCLK_RKPWM_PMU>;
1197 clock-names = "pwm";
1198 status = "disabled";
1199 };
1200
1201 pwm1: pwm@ff420010 {
1202 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1203 reg = <0x0 0xff420010 0x0 0x10>;
1204 #pwm-cells = <3>;
1205 pinctrl-names = "default";
1206 pinctrl-0 = <&pwm1_pin>;
1207 clocks = <&pmucru PCLK_RKPWM_PMU>;
1208 clock-names = "pwm";
1209 status = "disabled";
1210 };
1211
1212 pwm2: pwm@ff420020 {
1213 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1214 reg = <0x0 0xff420020 0x0 0x10>;
1215 #pwm-cells = <3>;
1216 pinctrl-names = "default";
1217 pinctrl-0 = <&pwm2_pin>;
1218 clocks = <&pmucru PCLK_RKPWM_PMU>;
1219 clock-names = "pwm";
1220 status = "disabled";
1221 };
1222
1223 pwm3: pwm@ff420030 {
1224 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1225 reg = <0x0 0xff420030 0x0 0x10>;
1226 #pwm-cells = <3>;
1227 pinctrl-names = "default";
1228 pinctrl-0 = <&pwm3a_pin>;
1229 clocks = <&pmucru PCLK_RKPWM_PMU>;
1230 clock-names = "pwm";
1231 status = "disabled";
1232 };
1233
ae4fdcca
SX		 1234 vpu_mmu: iommu@ff650800 {
1235 compatible = "rockchip,iommu";
1236 reg = <0x0 0xff650800 0x0 0x40>;
1237 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1238 interrupt-names = "vpu_mmu";
1239 #iommu-cells = <0>;
1240 status = "disabled";
1241 };
1242
1243 vdec_mmu: iommu@ff660480 {
1244 compatible = "rockchip,iommu";
1245 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1246 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1247 interrupt-names = "vdec_mmu";
1248 #iommu-cells = <0>;
1249 status = "disabled";
1250 };
1251
1252 iep_mmu: iommu@ff670800 {
1253 compatible = "rockchip,iommu";
1254 reg = <0x0 0xff670800 0x0 0x40>;
1255 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1256 interrupt-names = "iep_mmu";
1257 #iommu-cells = <0>;
1258 status = "disabled";
1259 };
1260
ec5ccfd7
JC		 1261 rga: rga@ff680000 {
1262 compatible = "rockchip,rk3399-rga";
1263 reg = <0x0 0xff680000 0x0 0x10000>;
1264 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1265 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1266 clock-names = "aclk", "hclk", "sclk";
1267 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1268 reset-names = "core", "axi", "ahb";
1269 power-domains = <&power RK3399_PD_RGA>;
1270 };
1271
b7ee3b27
FX		 1272 efuse0: efuse@ff690000 {
1273 compatible = "rockchip,rk3399-efuse";
1274 reg = <0x0 0xff690000 0x0 0x80>;
1275 #address-cells = <1>;
1276 #size-cells = <1>;
1277 clocks = <&cru PCLK_EFUSE1024NS>;
1278 clock-names = "pclk_efuse";
1279
1280 /* Data cells */
0d326927
ZX		 1281 cpu_id: cpu-id@7 {
1282 reg = <0x07 0x10>;
1283 };
b7ee3b27
FX		 1284 cpub_leakage: cpu-leakage@17 {
1285 reg = <0x17 0x1>;
1286 };
1287 gpu_leakage: gpu-leakage@18 {
1288 reg = <0x18 0x1>;
1289 };
1290 center_leakage: center-leakage@19 {
1291 reg = <0x19 0x1>;
1292 };
1293 cpul_leakage: cpu-leakage@1a {
1294 reg = <0x1a 0x1>;
1295 };
1296 logic_leakage: logic-leakage@1b {
1297 reg = <0x1b 0x1>;
1298 };
1299 wafer_info: wafer-info@1c {
1300 reg = <0x1c 0x1>;
1301 };
1302 };
1303
f048b9a4
JX		 1304 pmucru: pmu-clock-controller@ff750000 {
1305 compatible = "rockchip,rk3399-pmucru";
1306 reg = <0x0 0xff750000 0x0 0x1000>;
8cbb59af 1307 rockchip,grf = <&pmugrf>;
f048b9a4
JX		 1308 #clock-cells = <1>;
1309 #reset-cells = <1>;
1310 assigned-clocks = <&pmucru PLL_PPLL>;
1311 assigned-clock-rates = <676000000>;
1312 };
1313
1314 cru: clock-controller@ff760000 {
1315 compatible = "rockchip,rk3399-cru";
1316 reg = <0x0 0xff760000 0x0 0x1000>;
8cbb59af 1317 rockchip,grf = <&grf>;
f048b9a4
JX		 1318 #clock-cells = <1>;
1319 #reset-cells = <1>;
a09906cd
XZ		 1320 assigned-clocks =
1321 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1322 <&cru PLL_NPLL>,
1323 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1324 <&cru PCLK_PERIHP>,
1325 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
bb4b6201 1326 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
3f7f3b0f 1327 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
e702e13f
LH		 1328 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1329 <&cru ACLK_GIC_PRE>,
1330 <&cru PCLK_DDR>;
a09906cd
XZ		 1331 assigned-clock-rates =
1332 <594000000>, <800000000>,
1333 <1000000000>,
1334 <150000000>, <75000000>,
1335 <37500000>,
1336 <100000000>, <100000000>,
bb4b6201 1337 <50000000>, <600000000>,
3f7f3b0f 1338 <100000000>, <50000000>,
e702e13f
LH		 1339 <400000000>, <400000000>,
1340 <200000000>,
1341 <200000000>;
f048b9a4
JX		 1342 };
1343
1344 grf: syscon@ff770000 {
16759262 1345 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
f048b9a4 1346 reg = <0x0 0xff770000 0x0 0x10000>;
16759262
BN		 1347 #address-cells = <1>;
1348 #size-cells = <1>;
b4e87c09 1349
6d0e3a45
HS		 1350 io_domains: io-domains {
1351 compatible = "rockchip,rk3399-io-voltage-domain";
1352 status = "disabled";
1353 };
1354
103e9f85
FW		 1355 u2phy0: usb2-phy@e450 {
1356 compatible = "rockchip,rk3399-usb2phy";
1357 reg = <0xe450 0x10>;
1358 clocks = <&cru SCLK_USB2PHY0_REF>;
1359 clock-names = "phyclk";
1360 #clock-cells = <0>;
1361 clock-output-names = "clk_usbphy0_480m";
1362 status = "disabled";
1363
1364 u2phy0_host: host-port {
1365 #phy-cells = <0>;
210bbd38 1366 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
103e9f85
FW		 1367 interrupt-names = "linestate";
1368 status = "disabled";
1369 };
fe7f2de1
WW		 1370
1371 u2phy0_otg: otg-port {
1372 #phy-cells = <0>;
1373 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1374 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1375 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1376 interrupt-names = "otg-bvalid", "otg-id",
1377 "linestate";
1378 status = "disabled";
1379 };
103e9f85
FW		 1380 };
1381
1382 u2phy1: usb2-phy@e460 {
1383 compatible = "rockchip,rk3399-usb2phy";
1384 reg = <0xe460 0x10>;
1385 clocks = <&cru SCLK_USB2PHY1_REF>;
1386 clock-names = "phyclk";
1387 #clock-cells = <0>;
1388 clock-output-names = "clk_usbphy1_480m";
1389 status = "disabled";
1390
1391 u2phy1_host: host-port {
1392 #phy-cells = <0>;
210bbd38 1393 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
103e9f85
FW		 1394 interrupt-names = "linestate";
1395 status = "disabled";
1396 };
fe7f2de1
WW		 1397
1398 u2phy1_otg: otg-port {
1399 #phy-cells = <0>;
1400 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1401 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1402 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1403 interrupt-names = "otg-bvalid", "otg-id",
1404 "linestate";
1405 status = "disabled";
1406 };
103e9f85
FW		 1407 };
1408
b4e87c09
BN		 1409 emmc_phy: phy@f780 {
1410 compatible = "rockchip,rk3399-emmc-phy";
1411 reg = <0xf780 0x24>;
ed388cdd
DA		 1412 clocks = <&sdhci>;
1413 clock-names = "emmcclk";
b4e87c09
BN		 1414 #phy-cells = <0>;
1415 status = "disabled";
1416 };
29a0be1c
SL		 1417
1418 pcie_phy: pcie-phy {
1419 compatible = "rockchip,rk3399-pcie-phy";
1420 clocks = <&cru SCLK_PCIEPHY_REF>;
1421 clock-names = "refclk";
e9a60cac 1422 #phy-cells = <1>;
29a0be1c
SL		 1423 resets = <&cru SRST_PCIEPHY>;
1424 reset-names = "phy";
1425 status = "disabled";
1426 };
f048b9a4
JX		 1427 };
1428
f606193a
CZ		 1429 tcphy0: phy@ff7c0000 {
1430 compatible = "rockchip,rk3399-typec-phy";
1431 reg = <0x0 0xff7c0000 0x0 0x40000>;
1432 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1433 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1434 clock-names = "tcpdcore", "tcpdphy-ref";
1435 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1436 assigned-clock-rates = <50000000>;
06ad4b2f 1437 power-domains = <&power RK3399_PD_TCPD0>;
f606193a
CZ		 1438 resets = <&cru SRST_UPHY0>,
1439 <&cru SRST_UPHY0_PIPE_L00>,
1440 <&cru SRST_P_UPHY0_TCPHY>;
1441 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1442 rockchip,grf = <&grf>;
1443 rockchip,typec-conn-dir = <0xe580 0 16>;
1444 rockchip,usb3tousb2-en = <0xe580 3 19>;
1445 rockchip,external-psm = <0xe588 14 30>;
1446 rockchip,pipe-status = <0xe5c0 0 0>;
1447 status = "disabled";
1448
1449 tcphy0_dp: dp-port {
1450 #phy-cells = <0>;
1451 };
1452
1453 tcphy0_usb3: usb3-port {
1454 #phy-cells = <0>;
1455 };
1456 };
1457
1458 tcphy1: phy@ff800000 {
1459 compatible = "rockchip,rk3399-typec-phy";
1460 reg = <0x0 0xff800000 0x0 0x40000>;
1461 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1462 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1463 clock-names = "tcpdcore", "tcpdphy-ref";
1464 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1465 assigned-clock-rates = <50000000>;
06ad4b2f 1466 power-domains = <&power RK3399_PD_TCPD1>;
f606193a
CZ		 1467 resets = <&cru SRST_UPHY1>,
1468 <&cru SRST_UPHY1_PIPE_L00>,
1469 <&cru SRST_P_UPHY1_TCPHY>;
1470 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1471 rockchip,grf = <&grf>;
1472 rockchip,typec-conn-dir = <0xe58c 0 16>;
1473 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1474 rockchip,external-psm = <0xe594 14 30>;
1475 rockchip,pipe-status = <0xe5c0 16 16>;
1476 status = "disabled";
1477
1478 tcphy1_dp: dp-port {
1479 #phy-cells = <0>;
1480 };
1481
1482 tcphy1_usb3: usb3-port {
1483 #phy-cells = <0>;
1484 };
1485 };
1486
0895b3a8 1487 watchdog@ff848000 {
f048b9a4 1488 compatible = "snps,dw-wdt";
0895b3a8 1489 reg = <0x0 0xff848000 0x0 0x100>;
f048b9a4 1490 clocks = <&cru PCLK_WDT>;
210bbd38 1491 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1492 };
1493
1e8567d5
HT		 1494 rktimer: rktimer@ff850000 {
1495 compatible = "rockchip,rk3399-timer";
1496 reg = <0x0 0xff850000 0x0 0x1000>;
210bbd38 1497 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1e8567d5
HT		 1498 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1499 clock-names = "pclk", "timer";
1500 };
1501
f048b9a4
JX		 1502 spdif: spdif@ff870000 {
1503 compatible = "rockchip,rk3399-spdif";
1504 reg = <0x0 0xff870000 0x0 0x1000>;
210bbd38 1505 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1506 dmas = <&dmac_bus 7>;
1507 dma-names = "tx";
1508 clock-names = "mclk", "hclk";
1509 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1510 pinctrl-names = "default";
1511 pinctrl-0 = <&spdif_bus>;
b0f2110a 1512 power-domains = <&power RK3399_PD_SDIOAUDIO>;
f048b9a4
JX		 1513 status = "disabled";
1514 };
1515
1516 i2s0: i2s@ff880000 {
1517 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1518 reg = <0x0 0xff880000 0x0 0x1000>;
1519 rockchip,grf = <&grf>;
210bbd38 1520 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1521 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1522 dma-names = "tx", "rx";
1523 clock-names = "i2s_clk", "i2s_hclk";
1524 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1525 pinctrl-names = "default";
1526 pinctrl-0 = <&i2s0_8ch_bus>;
b0f2110a 1527 power-domains = <&power RK3399_PD_SDIOAUDIO>;
f048b9a4
JX		 1528 status = "disabled";
1529 };
1530
1531 i2s1: i2s@ff890000 {
1532 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1533 reg = <0x0 0xff890000 0x0 0x1000>;
210bbd38 1534 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1535 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1536 dma-names = "tx", "rx";
1537 clock-names = "i2s_clk", "i2s_hclk";
1538 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1539 pinctrl-names = "default";
1540 pinctrl-0 = <&i2s1_2ch_bus>;
b0f2110a 1541 power-domains = <&power RK3399_PD_SDIOAUDIO>;
f048b9a4
JX		 1542 status = "disabled";
1543 };
1544
1545 i2s2: i2s@ff8a0000 {
1546 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1547 reg = <0x0 0xff8a0000 0x0 0x1000>;
210bbd38 1548 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1549 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1550 dma-names = "tx", "rx";
1551 clock-names = "i2s_clk", "i2s_hclk";
1552 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
b0f2110a 1553 power-domains = <&power RK3399_PD_SDIOAUDIO>;
f048b9a4
JX		 1554 status = "disabled";
1555 };
1556
fbd4cc0e
MY		 1557 vopl: vop@ff8f0000 {
1558 compatible = "rockchip,rk3399-vop-lit";
1559 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1560 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
617f4472
KY		 1561 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1562 assigned-clock-rates = <400000000>, <100000000>;
fbd4cc0e
MY		 1563 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1564 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1565 iommus = <&vopl_mmu>;
1566 power-domains = <&power RK3399_PD_VOPL>;
1567 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1568 reset-names = "axi", "ahb", "dclk";
1569 status = "disabled";
1570
1571 vopl_out: port {
1572 #address-cells = <1>;
1573 #size-cells = <0>;
f7a29e30 1574
d3f51f49
JC		 1575 vopl_out_mipi: endpoint@0 {
1576 reg = <0>;
1577 remote-endpoint = <&mipi_in_vopl>;
1578 };
1579
f7a29e30
YY		 1580 vopl_out_edp: endpoint@1 {
1581 reg = <1>;
1582 remote-endpoint = <&edp_in_vopl>;
1583 };
1584
81e923dd
JC		 1585 vopl_out_hdmi: endpoint@2 {
1586 reg = <2>;
1587 remote-endpoint = <&hdmi_in_vopl>;
1588 };
1df5d2ab
NY		 1589
1590 vopl_out_mipi1: endpoint@3 {
1591 reg = <3>;
1592 remote-endpoint = <&mipi1_in_vopl>;
1593 };
2d3c2d56
CZ		 1594
1595 vopl_out_dp: endpoint@4 {
1596 reg = <4>;
1597 remote-endpoint = <&dp_in_vopl>;
1598 };
fbd4cc0e
MY		 1599 };
1600 };
1601
1602 vopl_mmu: iommu@ff8f3f00 {
1603 compatible = "rockchip,iommu";
1604 reg = <0x0 0xff8f3f00 0x0 0x100>;
1605 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1606 interrupt-names = "vopl_mmu";
1607 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1608 clock-names = "aclk", "hclk";
1609 power-domains = <&power RK3399_PD_VOPL>;
1610 #iommu-cells = <0>;
1611 status = "disabled";
1612 };
1613
1614 vopb: vop@ff900000 {
1615 compatible = "rockchip,rk3399-vop-big";
1616 reg = <0x0 0xff900000 0x0 0x3efc>;
1617 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
617f4472
KY		 1618 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1619 assigned-clock-rates = <400000000>, <100000000>;
fbd4cc0e
MY		 1620 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1621 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1622 iommus = <&vopb_mmu>;
1623 power-domains = <&power RK3399_PD_VOPB>;
1624 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1625 reset-names = "axi", "ahb", "dclk";
1626 status = "disabled";
1627
1628 vopb_out: port {
1629 #address-cells = <1>;
1630 #size-cells = <0>;
f7a29e30
YY		 1631
1632 vopb_out_edp: endpoint@0 {
1633 reg = <0>;
1634 remote-endpoint = <&edp_in_vopb>;
1635 };
1636
d3f51f49
JC		 1637 vopb_out_mipi: endpoint@1 {
1638 reg = <1>;
1639 remote-endpoint = <&mipi_in_vopb>;
1640 };
1641
81e923dd
JC		 1642 vopb_out_hdmi: endpoint@2 {
1643 reg = <2>;
1644 remote-endpoint = <&hdmi_in_vopb>;
1645 };
1df5d2ab
NY		 1646
1647 vopb_out_mipi1: endpoint@3 {
1648 reg = <3>;
1649 remote-endpoint = <&mipi1_in_vopb>;
1650 };
2d3c2d56
CZ		 1651
1652 vopb_out_dp: endpoint@4 {
1653 reg = <4>;
1654 remote-endpoint = <&dp_in_vopb>;
1655 };
fbd4cc0e
MY		 1656 };
1657 };
1658
1659 vopb_mmu: iommu@ff903f00 {
1660 compatible = "rockchip,iommu";
1661 reg = <0x0 0xff903f00 0x0 0x100>;
1662 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1663 interrupt-names = "vopb_mmu";
1664 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1665 clock-names = "aclk", "hclk";
1666 power-domains = <&power RK3399_PD_VOPB>;
1667 #iommu-cells = <0>;
1668 status = "disabled";
1669 };
1670
ae4fdcca
SX		 1671 isp0_mmu: iommu@ff914000 {
1672 compatible = "rockchip,iommu";
1673 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1674 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1675 interrupt-names = "isp0_mmu";
1676 #iommu-cells = <0>;
1677 rockchip,disable-mmu-reset;
1678 status = "disabled";
1679 };
1680
1681 isp1_mmu: iommu@ff924000 {
1682 compatible = "rockchip,iommu";
1683 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1684 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1685 interrupt-names = "isp1_mmu";
1686 #iommu-cells = <0>;
1687 rockchip,disable-mmu-reset;
1688 status = "disabled";
1689 };
1690
81e923dd
JC		 1691 hdmi: hdmi@ff940000 {
1692 compatible = "rockchip,rk3399-dw-hdmi";
1693 reg = <0x0 0xff940000 0x0 0x20000>;
1694 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
db2fd26d
PHH		 1695 clocks = <&cru PCLK_HDMI_CTRL>,
1696 <&cru SCLK_HDMI_SFR>,
1697 <&cru PLL_VPLL>,
1698 <&cru PCLK_VIO_GRF>,
1699 <&cru SCLK_HDMI_CEC>;
1700 clock-names = "iahb", "isfr", "vpll", "grf", "cec";
81e923dd
JC		 1701 power-domains = <&power RK3399_PD_HDCP>;
1702 reg-io-width = <4>;
1703 rockchip,grf = <&grf>;
1704 status = "disabled";
1705
1706 ports {
1707 hdmi_in: port {
1708 #address-cells = <1>;
1709 #size-cells = <0>;
1710
1711 hdmi_in_vopb: endpoint@0 {
1712 reg = <0>;
1713 remote-endpoint = <&vopb_out_hdmi>;
1714 };
1715 hdmi_in_vopl: endpoint@1 {
1716 reg = <1>;
1717 remote-endpoint = <&vopl_out_hdmi>;
1718 };
1719 };
1720 };
1721 };
1722
d3f51f49
JC		 1723 mipi_dsi: mipi@ff960000 {
1724 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1725 reg = <0x0 0xff960000 0x0 0x8000>;
1726 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
bb4e6ff0 1727 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
0bc15d85
NY		 1728 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1729 clock-names = "ref", "pclk", "phy_cfg", "grf";
d3f51f49 1730 power-domains = <&power RK3399_PD_VIO>;
3813a10a
BN		 1731 resets = <&cru SRST_P_MIPI_DSI0>;
1732 reset-names = "apb";
d3f51f49
JC		 1733 rockchip,grf = <&grf>;
1734 status = "disabled";
1735
1736 ports {
c856cb5d
NY		 1737 #address-cells = <1>;
1738 #size-cells = <0>;
1739
1740 mipi_in: port@0 {
1741 reg = <0>;
d3f51f49
JC		 1742 #address-cells = <1>;
1743 #size-cells = <0>;
1744
1745 mipi_in_vopb: endpoint@0 {
1746 reg = <0>;
1747 remote-endpoint = <&vopb_out_mipi>;
1748 };
1749 mipi_in_vopl: endpoint@1 {
1750 reg = <1>;
1751 remote-endpoint = <&vopl_out_mipi>;
1752 };
1753 };
1754 };
1755 };
1756
1df5d2ab
NY		 1757 mipi_dsi1: mipi@ff968000 {
1758 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1759 reg = <0x0 0xff968000 0x0 0x8000>;
1760 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1761 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1762 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1763 clock-names = "ref", "pclk", "phy_cfg", "grf";
1764 power-domains = <&power RK3399_PD_VIO>;
1765 resets = <&cru SRST_P_MIPI_DSI1>;
1766 reset-names = "apb";
1767 rockchip,grf = <&grf>;
1768 status = "disabled";
1769
1770 ports {
1771 #address-cells = <1>;
1772 #size-cells = <0>;
1773
1774 mipi1_in: port@0 {
1775 reg = <0>;
1776 #address-cells = <1>;
1777 #size-cells = <0>;
1778
1779 mipi1_in_vopb: endpoint@0 {
1780 reg = <0>;
1781 remote-endpoint = <&vopb_out_mipi1>;
1782 };
1783
1784 mipi1_in_vopl: endpoint@1 {
1785 reg = <1>;
1786 remote-endpoint = <&vopl_out_mipi1>;
1787 };
1788 };
1789 };
1790 };
1791
f7a29e30
YY		 1792 edp: edp@ff970000 {
1793 compatible = "rockchip,rk3399-edp";
1794 reg = <0x0 0xff970000 0x0 0x8000>;
1795 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
7b0390ea
YY		 1796 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1797 clock-names = "dp", "pclk", "grf";
f7a29e30
YY		 1798 pinctrl-names = "default";
1799 pinctrl-0 = <&edp_hpd>;
1800 power-domains = <&power RK3399_PD_EDP>;
1801 resets = <&cru SRST_P_EDP_CTRL>;
1802 reset-names = "dp";
1803 rockchip,grf = <&grf>;
1804 status = "disabled";
1805
1806 ports {
1807 #address-cells = <1>;
1808 #size-cells = <0>;
1809 edp_in: port@0 {
1810 reg = <0>;
1811 #address-cells = <1>;
1812 #size-cells = <0>;
1813
1814 edp_in_vopb: endpoint@0 {
1815 reg = <0>;
1816 remote-endpoint = <&vopb_out_edp>;
1817 };
1818
1819 edp_in_vopl: endpoint@1 {
1820 reg = <1>;
1821 remote-endpoint = <&vopl_out_edp>;
1822 };
1823 };
1824 };
1825 };
1826
68d19331
CW		 1827 gpu: gpu@ff9a0000 {
1828 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1829 reg = <0x0 0xff9a0000 0x0 0x10000>;
1830 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1831 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1832 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1833 interrupt-names = "gpu", "job", "mmu";
1834 clocks = <&cru ACLK_GPU>;
1835 power-domains = <&power RK3399_PD_GPU>;
f048b9a4
JX		 1836 status = "disabled";
1837 };
1838
1839 pinctrl: pinctrl {
1840 compatible = "rockchip,rk3399-pinctrl";
1841 rockchip,grf = <&grf>;
1842 rockchip,pmu = <&pmugrf>;
1843 #address-cells = <2>;
1844 #size-cells = <2>;
1845 ranges;
1846
1847 gpio0: gpio0@ff720000 {
1848 compatible = "rockchip,gpio-bank";
1849 reg = <0x0 0xff720000 0x0 0x100>;
1850 clocks = <&pmucru PCLK_GPIO0_PMU>;
210bbd38 1851 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1852
1853 gpio-controller;
1854 #gpio-cells = <0x2>;
1855
1856 interrupt-controller;
1857 #interrupt-cells = <0x2>;
1858 };
1859
1860 gpio1: gpio1@ff730000 {
1861 compatible = "rockchip,gpio-bank";
1862 reg = <0x0 0xff730000 0x0 0x100>;
1863 clocks = <&pmucru PCLK_GPIO1_PMU>;
210bbd38 1864 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1865
1866 gpio-controller;
1867 #gpio-cells = <0x2>;
1868
1869 interrupt-controller;
1870 #interrupt-cells = <0x2>;
1871 };
1872
1873 gpio2: gpio2@ff780000 {
1874 compatible = "rockchip,gpio-bank";
1875 reg = <0x0 0xff780000 0x0 0x100>;
1876 clocks = <&cru PCLK_GPIO2>;
210bbd38 1877 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1878
1879 gpio-controller;
1880 #gpio-cells = <0x2>;
1881
1882 interrupt-controller;
1883 #interrupt-cells = <0x2>;
1884 };
1885
1886 gpio3: gpio3@ff788000 {
1887 compatible = "rockchip,gpio-bank";
1888 reg = <0x0 0xff788000 0x0 0x100>;
1889 clocks = <&cru PCLK_GPIO3>;
210bbd38 1890 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1891
1892 gpio-controller;
1893 #gpio-cells = <0x2>;
1894
1895 interrupt-controller;
1896 #interrupt-cells = <0x2>;
1897 };
1898
1899 gpio4: gpio4@ff790000 {
1900 compatible = "rockchip,gpio-bank";
1901 reg = <0x0 0xff790000 0x0 0x100>;
1902 clocks = <&cru PCLK_GPIO4>;
210bbd38 1903 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
f048b9a4
JX		 1904
1905 gpio-controller;
1906 #gpio-cells = <0x2>;
1907
1908 interrupt-controller;
1909 #interrupt-cells = <0x2>;
1910 };
1911
1912 pcfg_pull_up: pcfg-pull-up {
1913 bias-pull-up;
1914 };
1915
1916 pcfg_pull_down: pcfg-pull-down {
1917 bias-pull-down;
1918 };
1919
1920 pcfg_pull_none: pcfg-pull-none {
1921 bias-disable;
1922 };
1923
1924 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1925 bias-disable;
1926 drive-strength = <12>;
1927 };
1928
1929 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1930 bias-pull-up;
1931 drive-strength = <8>;
1932 };
1933
1934 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1935 bias-pull-down;
1936 drive-strength = <4>;
1937 };
1938
1939 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1940 bias-pull-up;
1941 drive-strength = <2>;
1942 };
1943
1944 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1945 bias-pull-down;
1946 drive-strength = <12>;
1947 };
1948
1949 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1950 bias-disable;
1951 drive-strength = <13>;
1952 };
1953
a8bcaea7
DA		 1954 clock {
1955 clk_32k: clk-32k {
1956 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
1957 };
1958 };
1959
8742466a
BN		 1960 edp {
1961 edp_hpd: edp-hpd {
1962 rockchip,pins =
1963 <4 23 RK_FUNC_2 &pcfg_pull_none>;
1964 };
1965 };
1966
eb3a6a6a
RC		 1967 gmac {
1968 rgmii_pins: rgmii-pins {
1969 rockchip,pins =
1970 /* mac_txclk */
1971 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1972 /* mac_rxclk */
1973 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1974 /* mac_mdio */
1975 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1976 /* mac_txen */
1977 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1978 /* mac_clk */
1979 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1980 /* mac_rxdv */
1981 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1982 /* mac_mdc */
1983 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1984 /* mac_rxd1 */
1985 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1986 /* mac_rxd0 */
1987 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1988 /* mac_txd1 */
1989 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1990 /* mac_txd0 */
1991 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1992 /* mac_rxd3 */
1993 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1994 /* mac_rxd2 */
1995 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1996 /* mac_txd3 */
1997 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1998 /* mac_txd2 */
1999 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2000 };
2001
2002 rmii_pins: rmii-pins {
2003 rockchip,pins =
2004 /* mac_mdio */
2005 <3 13 RK_FUNC_1 &pcfg_pull_none>,
2006 /* mac_txen */
2007 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2008 /* mac_clk */
2009 <3 11 RK_FUNC_1 &pcfg_pull_none>,
2010 /* mac_rxer */
2011 <3 10 RK_FUNC_1 &pcfg_pull_none>,
2012 /* mac_rxdv */
2013 <3 9 RK_FUNC_1 &pcfg_pull_none>,
2014 /* mac_mdc */
2015 <3 8 RK_FUNC_1 &pcfg_pull_none>,
2016 /* mac_rxd1 */
2017 <3 7 RK_FUNC_1 &pcfg_pull_none>,
2018 /* mac_rxd0 */
2019 <3 6 RK_FUNC_1 &pcfg_pull_none>,
2020 /* mac_txd1 */
2021 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2022 /* mac_txd0 */
2023 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2024 };
2025 };
2026
f048b9a4
JX		 2027 i2c0 {
2028 i2c0_xfer: i2c0-xfer {
2029 rockchip,pins =
2030 <1 15 RK_FUNC_2 &pcfg_pull_none>,
2031 <1 16 RK_FUNC_2 &pcfg_pull_none>;
2032 };
2033 };
2034
2035 i2c1 {
2036 i2c1_xfer: i2c1-xfer {
2037 rockchip,pins =
2038 <4 2 RK_FUNC_1 &pcfg_pull_none>,
2039 <4 1 RK_FUNC_1 &pcfg_pull_none>;
2040 };
2041 };
2042
2043 i2c2 {
2044 i2c2_xfer: i2c2-xfer {
2045 rockchip,pins =
2046 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2047 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2048 };
2049 };
2050
2051 i2c3 {
2052 i2c3_xfer: i2c3-xfer {
2053 rockchip,pins =
2054 <4 17 RK_FUNC_1 &pcfg_pull_none>,
2055 <4 16 RK_FUNC_1 &pcfg_pull_none>;
2056 };
2057 };
2058
2059 i2c4 {
2060 i2c4_xfer: i2c4-xfer {
2061 rockchip,pins =
2062 <1 12 RK_FUNC_1 &pcfg_pull_none>,
2063 <1 11 RK_FUNC_1 &pcfg_pull_none>;
2064 };
2065 };
2066
2067 i2c5 {
2068 i2c5_xfer: i2c5-xfer {
2069 rockchip,pins =
2070 <3 11 RK_FUNC_2 &pcfg_pull_none>,
2071 <3 10 RK_FUNC_2 &pcfg_pull_none>;
2072 };
2073 };
2074
2075 i2c6 {
2076 i2c6_xfer: i2c6-xfer {
2077 rockchip,pins =
2078 <2 10 RK_FUNC_2 &pcfg_pull_none>,
2079 <2 9 RK_FUNC_2 &pcfg_pull_none>;
2080 };
2081 };
2082
2083 i2c7 {
2084 i2c7_xfer: i2c7-xfer {
2085 rockchip,pins =
2086 <2 8 RK_FUNC_2 &pcfg_pull_none>,
2087 <2 7 RK_FUNC_2 &pcfg_pull_none>;
2088 };
2089 };
2090
2091 i2c8 {
2092 i2c8_xfer: i2c8-xfer {
2093 rockchip,pins =
2094 <1 21 RK_FUNC_1 &pcfg_pull_none>,
2095 <1 20 RK_FUNC_1 &pcfg_pull_none>;
2096 };
2097 };
2098
2099 i2s0 {
0efaf807
KG		 2100 i2s0_2ch_bus: i2s0-2ch-bus {
2101 rockchip,pins =
2102 <3 24 RK_FUNC_1 &pcfg_pull_none>,
2103 <3 25 RK_FUNC_1 &pcfg_pull_none>,
2104 <3 26 RK_FUNC_1 &pcfg_pull_none>,
2105 <3 27 RK_FUNC_1 &pcfg_pull_none>,
2106 <3 31 RK_FUNC_1 &pcfg_pull_none>,
2107 <4 0 RK_FUNC_1 &pcfg_pull_none>;
2108 };
2109
f048b9a4
JX		 2110 i2s0_8ch_bus: i2s0-8ch-bus {
2111 rockchip,pins =
2112 <3 24 RK_FUNC_1 &pcfg_pull_none>,
2113 <3 25 RK_FUNC_1 &pcfg_pull_none>,
2114 <3 26 RK_FUNC_1 &pcfg_pull_none>,
2115 <3 27 RK_FUNC_1 &pcfg_pull_none>,
2116 <3 28 RK_FUNC_1 &pcfg_pull_none>,
2117 <3 29 RK_FUNC_1 &pcfg_pull_none>,
2118 <3 30 RK_FUNC_1 &pcfg_pull_none>,
2119 <3 31 RK_FUNC_1 &pcfg_pull_none>,
2120 <4 0 RK_FUNC_1 &pcfg_pull_none>;
2121 };
2122 };
2123
2124 i2s1 {
2125 i2s1_2ch_bus: i2s1-2ch-bus {
2126 rockchip,pins =
2127 <4 3 RK_FUNC_1 &pcfg_pull_none>,
2128 <4 4 RK_FUNC_1 &pcfg_pull_none>,
2129 <4 5 RK_FUNC_1 &pcfg_pull_none>,
2130 <4 6 RK_FUNC_1 &pcfg_pull_none>,
2131 <4 7 RK_FUNC_1 &pcfg_pull_none>;
2132 };
2133 };
2134
b74a2e98
KY		 2135 sdio0 {
2136 sdio0_bus1: sdio0-bus1 {
2137 rockchip,pins =
2138 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
2139 };
2140
2141 sdio0_bus4: sdio0-bus4 {
2142 rockchip,pins =
2143 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
2144 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
2145 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
2146 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
2147 };
2148
2149 sdio0_cmd: sdio0-cmd {
2150 rockchip,pins =
2151 <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>;
2152 };
2153
2154 sdio0_clk: sdio0-clk {
2155 rockchip,pins =
2156 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
2157 };
2158
2159 sdio0_cd: sdio0-cd {
2160 rockchip,pins =
2161 <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>;
2162 };
2163
2164 sdio0_pwr: sdio0-pwr {
2165 rockchip,pins =
2166 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>;
2167 };
2168
2169 sdio0_bkpwr: sdio0-bkpwr {
2170 rockchip,pins =
2171 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
2172 };
2173
2174 sdio0_wp: sdio0-wp {
2175 rockchip,pins =
2176 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
2177 };
2178
2179 sdio0_int: sdio0-int {
2180 rockchip,pins =
2181 <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
2182 };
2183 };
2184
2185 sdmmc {
2186 sdmmc_bus1: sdmmc-bus1 {
2187 rockchip,pins =
2188 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2189 };
2190
2191 sdmmc_bus4: sdmmc-bus4 {
2192 rockchip,pins =
2193 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>,
2194 <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
2195 <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
2196 <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
2197 };
2198
2199 sdmmc_clk: sdmmc-clk {
2200 rockchip,pins =
2201 <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
2202 };
2203
2204 sdmmc_cmd: sdmmc-cmd {
2205 rockchip,pins =
2206 <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
2207 };
2208
6122308e 2209 sdmmc_cd: sdmmc-cd {
b74a2e98
KY		 2210 rockchip,pins =
2211 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
2212 };
2213
2214 sdmmc_wp: sdmmc-wp {
2215 rockchip,pins =
2216 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2217 };
2218 };
2219
5d26ad9c
DA		 2220 sleep {
2221 ap_pwroff: ap-pwroff {
2222 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
2223 };
2224
2225 ddrio_pwroff: ddrio-pwroff {
2226 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
2227 };
2228 };
2229
f048b9a4
JX		 2230 spdif {
2231 spdif_bus: spdif-bus {
2232 rockchip,pins =
2233 <4 21 RK_FUNC_1 &pcfg_pull_none>;
2234 };
b74a2e98
KY		 2235
2236 spdif_bus_1: spdif-bus-1 {
2237 rockchip,pins =
2238 <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2239 };
f048b9a4
JX		 2240 };
2241
2242 spi0 {
2243 spi0_clk: spi0-clk {
2244 rockchip,pins =
2245 <3 6 RK_FUNC_2 &pcfg_pull_up>;
2246 };
2247 spi0_cs0: spi0-cs0 {
2248 rockchip,pins =
2249 <3 7 RK_FUNC_2 &pcfg_pull_up>;
2250 };
2251 spi0_cs1: spi0-cs1 {
2252 rockchip,pins =
2253 <3 8 RK_FUNC_2 &pcfg_pull_up>;
2254 };
2255 spi0_tx: spi0-tx {
2256 rockchip,pins =
2257 <3 5 RK_FUNC_2 &pcfg_pull_up>;
2258 };
2259 spi0_rx: spi0-rx {
2260 rockchip,pins =
2261 <3 4 RK_FUNC_2 &pcfg_pull_up>;
2262 };
2263 };
2264
2265 spi1 {
2266 spi1_clk: spi1-clk {
2267 rockchip,pins =
2268 <1 9 RK_FUNC_2 &pcfg_pull_up>;
2269 };
2270 spi1_cs0: spi1-cs0 {
2271 rockchip,pins =
2272 <1 10 RK_FUNC_2 &pcfg_pull_up>;
2273 };
2274 spi1_rx: spi1-rx {
2275 rockchip,pins =
2276 <1 7 RK_FUNC_2 &pcfg_pull_up>;
2277 };
2278 spi1_tx: spi1-tx {
2279 rockchip,pins =
2280 <1 8 RK_FUNC_2 &pcfg_pull_up>;
2281 };
2282 };
2283
2284 spi2 {
2285 spi2_clk: spi2-clk {
2286 rockchip,pins =
2287 <2 11 RK_FUNC_1 &pcfg_pull_up>;
2288 };
2289 spi2_cs0: spi2-cs0 {
2290 rockchip,pins =
2291 <2 12 RK_FUNC_1 &pcfg_pull_up>;
2292 };
2293 spi2_rx: spi2-rx {
2294 rockchip,pins =
2295 <2 9 RK_FUNC_1 &pcfg_pull_up>;
2296 };
2297 spi2_tx: spi2-tx {
2298 rockchip,pins =
2299 <2 10 RK_FUNC_1 &pcfg_pull_up>;
2300 };
2301 };
2302
2303 spi3 {
2304 spi3_clk: spi3-clk {
2305 rockchip,pins =
2306 <1 17 RK_FUNC_1 &pcfg_pull_up>;
2307 };
2308 spi3_cs0: spi3-cs0 {
2309 rockchip,pins =
2310 <1 18 RK_FUNC_1 &pcfg_pull_up>;
2311 };
2312 spi3_rx: spi3-rx {
2313 rockchip,pins =
2314 <1 15 RK_FUNC_1 &pcfg_pull_up>;
2315 };
2316 spi3_tx: spi3-tx {
2317 rockchip,pins =
2318 <1 16 RK_FUNC_1 &pcfg_pull_up>;
2319 };
2320 };
2321
2322 spi4 {
2323 spi4_clk: spi4-clk {
2324 rockchip,pins =
2325 <3 2 RK_FUNC_2 &pcfg_pull_up>;
2326 };
2327 spi4_cs0: spi4-cs0 {
2328 rockchip,pins =
2329 <3 3 RK_FUNC_2 &pcfg_pull_up>;
2330 };
2331 spi4_rx: spi4-rx {
2332 rockchip,pins =
2333 <3 0 RK_FUNC_2 &pcfg_pull_up>;
2334 };
2335 spi4_tx: spi4-tx {
2336 rockchip,pins =
2337 <3 1 RK_FUNC_2 &pcfg_pull_up>;
2338 };
2339 };
2340
2341 spi5 {
2342 spi5_clk: spi5-clk {
2343 rockchip,pins =
2344 <2 22 RK_FUNC_2 &pcfg_pull_up>;
2345 };
2346 spi5_cs0: spi5-cs0 {
2347 rockchip,pins =
2348 <2 23 RK_FUNC_2 &pcfg_pull_up>;
2349 };
2350 spi5_rx: spi5-rx {
2351 rockchip,pins =
2352 <2 20 RK_FUNC_2 &pcfg_pull_up>;
2353 };
2354 spi5_tx: spi5-tx {
2355 rockchip,pins =
2356 <2 21 RK_FUNC_2 &pcfg_pull_up>;
2357 };
2358 };
2359
ba2b043e
SZ		 2360 testclk {
2361 test_clkout0: test-clkout0 {
2362 rockchip,pins =
2363 <0 0 RK_FUNC_1 &pcfg_pull_none>;
2364 };
2365
2366 test_clkout1: test-clkout1 {
2367 rockchip,pins =
2368 <2 25 RK_FUNC_2 &pcfg_pull_none>;
2369 };
2370
2371 test_clkout2: test-clkout2 {
2372 rockchip,pins =
2373 <0 8 RK_FUNC_3 &pcfg_pull_none>;
2374 };
2375 };
2376
95c27ba7
CW		 2377 tsadc {
2378 otp_gpio: otp-gpio {
2379 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2380 };
2381
2382 otp_out: otp-out {
2383 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2384 };
2385 };
2386
f048b9a4
JX		 2387 uart0 {
2388 uart0_xfer: uart0-xfer {
2389 rockchip,pins =
2390 <2 16 RK_FUNC_1 &pcfg_pull_up>,
2391 <2 17 RK_FUNC_1 &pcfg_pull_none>;
2392 };
2393
2394 uart0_cts: uart0-cts {
2395 rockchip,pins =
2396 <2 18 RK_FUNC_1 &pcfg_pull_none>;
2397 };
2398
2399 uart0_rts: uart0-rts {
2400 rockchip,pins =
2401 <2 19 RK_FUNC_1 &pcfg_pull_none>;
2402 };
2403 };
2404
2405 uart1 {
2406 uart1_xfer: uart1-xfer {
2407 rockchip,pins =
2408 <3 12 RK_FUNC_2 &pcfg_pull_up>,
2409 <3 13 RK_FUNC_2 &pcfg_pull_none>;
2410 };
2411 };
2412
2413 uart2a {
2414 uart2a_xfer: uart2a-xfer {
2415 rockchip,pins =
2416 <4 8 RK_FUNC_2 &pcfg_pull_up>,
2417 <4 9 RK_FUNC_2 &pcfg_pull_none>;
2418 };
2419 };
2420
2421 uart2b {
2422 uart2b_xfer: uart2b-xfer {
2423 rockchip,pins =
2424 <4 16 RK_FUNC_2 &pcfg_pull_up>,
2425 <4 17 RK_FUNC_2 &pcfg_pull_none>;
2426 };
2427 };
2428
2429 uart2c {
2430 uart2c_xfer: uart2c-xfer {
2431 rockchip,pins =
2432 <4 19 RK_FUNC_1 &pcfg_pull_up>,
2433 <4 20 RK_FUNC_1 &pcfg_pull_none>;
2434 };
2435 };
2436
2437 uart3 {
2438 uart3_xfer: uart3-xfer {
2439 rockchip,pins =
2440 <3 14 RK_FUNC_2 &pcfg_pull_up>,
2441 <3 15 RK_FUNC_2 &pcfg_pull_none>;
2442 };
2443
2444 uart3_cts: uart3-cts {
2445 rockchip,pins =
2446 <3 18 RK_FUNC_2 &pcfg_pull_none>;
2447 };
2448
2449 uart3_rts: uart3-rts {
2450 rockchip,pins =
2451 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2452 };
2453 };
2454
2455 uart4 {
2456 uart4_xfer: uart4-xfer {
2457 rockchip,pins =
2458 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2459 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2460 };
2461 };
2462
2463 uarthdcp {
2464 uarthdcp_xfer: uarthdcp-xfer {
2465 rockchip,pins =
2466 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2467 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2468 };
2469 };
2470
2471 pwm0 {
2472 pwm0_pin: pwm0-pin {
2473 rockchip,pins =
2474 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2475 };
2476
2477 vop0_pwm_pin: vop0-pwm-pin {
2478 rockchip,pins =
2479 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2480 };
2481 };
2482
2483 pwm1 {
2484 pwm1_pin: pwm1-pin {
2485 rockchip,pins =
2486 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2487 };
2488
2489 vop1_pwm_pin: vop1-pwm-pin {
2490 rockchip,pins =
2491 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2492 };
2493 };
2494
2495 pwm2 {
2496 pwm2_pin: pwm2-pin {
2497 rockchip,pins =
2498 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2499 };
2500 };
2501
2502 pwm3a {
2503 pwm3a_pin: pwm3a-pin {
2504 rockchip,pins =
2505 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2506 };
2507 };
2508
2509 pwm3b {
2510 pwm3b_pin: pwm3b-pin {
2511 rockchip,pins =
2512 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2513 };
2514 };
85aaa574 2515
b74a2e98
KY		 2516 hdmi {
2517 hdmi_i2c_xfer: hdmi-i2c-xfer {
2518 rockchip,pins =
2519 <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>,
2520 <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2521 };
2522
2523 hdmi_cec: hdmi-cec {
2524 rockchip,pins =
2525 <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
2526 };
2527 };
2528
85aaa574 2529 pcie {
b74a2e98
KY		 2530 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2531 rockchip,pins =
2532 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2533 };
2534
2535 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2536 rockchip,pins =
2537 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2538 };
85aaa574
SL		 2539 };
2540
f048b9a4
JX		 2541 };
2542};
Linux 6.x block layer and io_uring tree(s)